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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3092 1 T14 6 T5 1 T15 4
auto[1] 293 1 T82 6 T83 4 T74 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 130 1 T158 2 T82 1 T20 1
auto[134217728:268435455] 96 1 T34 1 T19 1 T82 1
auto[268435456:402653183] 114 1 T83 1 T20 1 T214 1
auto[402653184:536870911] 112 1 T20 1 T77 1 T37 1
auto[536870912:671088639] 94 1 T83 1 T20 1 T157 1
auto[671088640:805306367] 98 1 T15 1 T18 1 T19 1
auto[805306368:939524095] 103 1 T65 1 T37 1 T6 1
auto[939524096:1073741823] 100 1 T83 1 T70 1 T105 1
auto[1073741824:1207959551] 101 1 T83 1 T30 1 T77 1
auto[1207959552:1342177279] 102 1 T16 2 T83 1 T74 1
auto[1342177280:1476395007] 117 1 T14 2 T16 1 T30 1
auto[1476395008:1610612735] 113 1 T72 1 T70 1 T37 1
auto[1610612736:1744830463] 118 1 T15 1 T17 1 T65 1
auto[1744830464:1879048191] 115 1 T15 1 T16 1 T69 1
auto[1879048192:2013265919] 112 1 T14 1 T18 1 T74 1
auto[2013265920:2147483647] 112 1 T82 1 T20 1 T60 1
auto[2147483648:2281701375] 104 1 T14 1 T20 1 T44 2
auto[2281701376:2415919103] 118 1 T5 1 T16 1 T44 1
auto[2415919104:2550136831] 110 1 T60 1 T21 1 T51 1
auto[2550136832:2684354559] 110 1 T82 2 T138 1 T30 1
auto[2684354560:2818572287] 102 1 T16 1 T18 1 T82 1
auto[2818572288:2952790015] 98 1 T34 1 T83 1 T20 1
auto[2952790016:3087007743] 106 1 T17 1 T18 1 T82 1
auto[3087007744:3221225471] 102 1 T82 1 T70 1 T6 2
auto[3221225472:3355443199] 96 1 T74 1 T51 1 T6 1
auto[3355443200:3489660927] 86 1 T19 1 T69 1 T20 1
auto[3489660928:3623878655] 116 1 T16 1 T82 1 T83 1
auto[3623878656:3758096383] 101 1 T138 1 T83 1 T65 1
auto[3758096384:3892314111] 98 1 T14 2 T83 1 T72 1
auto[3892314112:4026531839] 103 1 T70 1 T48 1 T217 2
auto[4026531840:4160749567] 99 1 T15 1 T16 1 T65 1
auto[4160749568:4294967295] 99 1 T82 1 T138 1 T65 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 121 1 T158 2 T20 1 T44 1
auto[0:134217727] auto[1] 9 1 T82 1 T263 1 T349 1
auto[134217728:268435455] auto[0] 89 1 T34 1 T19 1 T82 1
auto[134217728:268435455] auto[1] 7 1 T269 1 T208 1 T363 1
auto[268435456:402653183] auto[0] 103 1 T83 1 T20 1 T214 1
auto[268435456:402653183] auto[1] 11 1 T269 1 T112 1 T245 1
auto[402653184:536870911] auto[0] 102 1 T20 1 T77 1 T37 1
auto[402653184:536870911] auto[1] 10 1 T107 1 T208 1 T245 1
auto[536870912:671088639] auto[0] 88 1 T83 1 T20 1 T157 1
auto[536870912:671088639] auto[1] 6 1 T363 1 T430 1 T432 1
auto[671088640:805306367] auto[0] 94 1 T15 1 T18 1 T19 1
auto[671088640:805306367] auto[1] 4 1 T82 1 T444 1 T429 2
auto[805306368:939524095] auto[0] 97 1 T65 1 T37 1 T6 1
auto[805306368:939524095] auto[1] 6 1 T244 1 T264 1 T268 1
auto[939524096:1073741823] auto[0] 93 1 T70 1 T131 1 T280 1
auto[939524096:1073741823] auto[1] 7 1 T83 1 T105 1 T363 1
auto[1073741824:1207959551] auto[0] 95 1 T83 1 T30 1 T77 1
auto[1073741824:1207959551] auto[1] 6 1 T349 1 T363 1 T440 1
auto[1207959552:1342177279] auto[0] 93 1 T16 2 T74 1 T70 1
auto[1207959552:1342177279] auto[1] 9 1 T83 1 T430 1 T440 2
auto[1342177280:1476395007] auto[0] 110 1 T14 2 T16 1 T30 1
auto[1342177280:1476395007] auto[1] 7 1 T269 1 T430 2 T428 2
auto[1476395008:1610612735] auto[0] 101 1 T72 1 T70 1 T37 1
auto[1476395008:1610612735] auto[1] 12 1 T269 2 T244 1 T283 1
auto[1610612736:1744830463] auto[0] 112 1 T15 1 T17 1 T65 1
auto[1610612736:1744830463] auto[1] 6 1 T268 1 T438 1 T439 1
auto[1744830464:1879048191] auto[0] 104 1 T15 1 T16 1 T69 1
auto[1744830464:1879048191] auto[1] 11 1 T255 1 T208 1 T244 1
auto[1879048192:2013265919] auto[0] 102 1 T14 1 T18 1 T74 1
auto[1879048192:2013265919] auto[1] 10 1 T269 1 T363 1 T431 1
auto[2013265920:2147483647] auto[0] 104 1 T82 1 T20 1 T60 1
auto[2013265920:2147483647] auto[1] 8 1 T430 1 T428 1 T445 1
auto[2147483648:2281701375] auto[0] 97 1 T14 1 T20 1 T44 2
auto[2147483648:2281701375] auto[1] 7 1 T269 1 T255 1 T432 1
auto[2281701376:2415919103] auto[0] 110 1 T5 1 T16 1 T44 1
auto[2281701376:2415919103] auto[1] 8 1 T245 1 T349 1 T363 2
auto[2415919104:2550136831] auto[0] 93 1 T60 1 T21 1 T51 1
auto[2415919104:2550136831] auto[1] 17 1 T351 1 T349 1 T363 1
auto[2550136832:2684354559] auto[0] 101 1 T138 1 T30 1 T74 1
auto[2550136832:2684354559] auto[1] 9 1 T82 2 T244 1 T194 1
auto[2684354560:2818572287] auto[0] 91 1 T16 1 T18 1 T82 1
auto[2684354560:2818572287] auto[1] 11 1 T269 1 T351 1 T433 1
auto[2818572288:2952790015] auto[0] 90 1 T34 1 T20 1 T70 1
auto[2818572288:2952790015] auto[1] 8 1 T83 1 T74 1 T269 1
auto[2952790016:3087007743] auto[0] 96 1 T17 1 T18 1 T82 1
auto[2952790016:3087007743] auto[1] 10 1 T269 3 T244 1 T263 1
auto[3087007744:3221225471] auto[0] 94 1 T70 1 T6 2 T304 1
auto[3087007744:3221225471] auto[1] 8 1 T82 1 T122 1 T269 1
auto[3221225472:3355443199] auto[0] 88 1 T51 1 T6 1 T316 1
auto[3221225472:3355443199] auto[1] 8 1 T74 1 T363 1 T283 1
auto[3355443200:3489660927] auto[0] 75 1 T19 1 T69 1 T20 1
auto[3355443200:3489660927] auto[1] 11 1 T363 1 T283 2 T379 1
auto[3489660928:3623878655] auto[0] 108 1 T16 1 T82 1 T66 1
auto[3489660928:3623878655] auto[1] 8 1 T83 1 T283 1 T431 1
auto[3623878656:3758096383] auto[0] 86 1 T138 1 T83 1 T65 1
auto[3623878656:3758096383] auto[1] 15 1 T208 1 T245 2 T363 2
auto[3758096384:3892314111] auto[0] 88 1 T14 2 T83 1 T72 1
auto[3758096384:3892314111] auto[1] 10 1 T244 1 T296 1 T379 1
auto[3892314112:4026531839] auto[0] 91 1 T70 1 T48 1 T217 2
auto[3892314112:4026531839] auto[1] 12 1 T269 1 T244 1 T433 1
auto[4026531840:4160749567] auto[0] 92 1 T15 1 T16 1 T65 1
auto[4026531840:4160749567] auto[1] 7 1 T245 1 T424 1 T283 1
auto[4160749568:4294967295] auto[0] 84 1 T138 1 T65 1 T6 1
auto[4160749568:4294967295] auto[1] 15 1 T82 1 T269 2 T351 1

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