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 LINE       3180
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T78,T90,T91
1	1	1	Covered	T14,T5,T15

 LINE       3183
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T65,T78,T90
1	1	1	Covered	T14,T5,T15

 LINE       3186
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T65,T78,T90
1	1	1	Covered	T14,T5,T15

 LINE       3189
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T66,T78,T90
1	1	1	Covered	T14,T5,T15

 LINE       3192
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T65,T78,T90
1	1	1	Covered	T14,T5,T15

 LINE       3195
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T78,T90,T91
1	1	1	Covered	T14,T5,T15

 LINE       3198
 EXPRESSION (addr_hit[37] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T168,T169
1	1	1	Covered	T65,T66,T78

 LINE       3199
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T90,T91,T93
1	1	1	Covered	T14,T5,T15

 LINE       3202
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T65,T78,T90
1	1	1	Covered	T14,T15,T16

 LINE       3205
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T170
1	1	1	Covered	T65,T66,T78

 LINE       3206
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T78,T91,T92
1	1	1	Covered	T14,T5,T15

 LINE       3209
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T78,T90,T91
1	1	1	Covered	T14,T5,T15

 LINE       3212
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T171
1	1	1	Covered	T65,T66,T78

 LINE       3213
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T65,T78,T91
1	1	1	Covered	T14,T5,T15

 LINE       3216
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T172
1	1	1	Covered	T1,T2,T3

 LINE       3219
 EXPRESSION (addr_hit[43] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T167,T173,T174
1	1	1	Covered	T1,T2,T3

 LINE       3222
 EXPRESSION (addr_hit[44] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T175,T169,T172
1	1	1	Covered	T1,T2,T3

 LINE       3225
 EXPRESSION (addr_hit[45] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T169,T176,T165
1	1	1	Covered	T1,T2,T3

 LINE       3228
 EXPRESSION (addr_hit[46] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T177
1	1	1	Covered	T1,T2,T3

 LINE       3231
 EXPRESSION (addr_hit[47] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       3234
 EXPRESSION (addr_hit[48] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T163,T172
1	1	1	Covered	T1,T2,T3

 LINE       3237
 EXPRESSION (addr_hit[49] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T178,T163,T179
1	1	1	Covered	T1,T2,T3

 LINE       3240
 EXPRESSION (addr_hit[50] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T180,T179
1	1	1	Covered	T1,T2,T3

 LINE       3243
 EXPRESSION (addr_hit[51] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T167,T180,T163
1	1	1	Covered	T1,T2,T3

 LINE       3246
 EXPRESSION (addr_hit[52] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       3249
 EXPRESSION (addr_hit[53] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T165,T166
1	1	1	Covered	T1,T2,T3

 LINE       3252
 EXPRESSION (addr_hit[54] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T181,T182
1	1	1	Covered	T1,T2,T3

 LINE       3255
 EXPRESSION (addr_hit[55] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T169
1	1	1	Covered	T1,T2,T3

 LINE       3258
 EXPRESSION (addr_hit[56] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T165
1	1	1	Covered	T1,T2,T3

 LINE       3261
 EXPRESSION (addr_hit[57] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T183
1	1	1	Covered	T1,T2,T3

 LINE       3264
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T66,T78,T90
1	1	1	Covered	T160,T161,T113

 LINE       3267
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T90,T91
1	1	1	Covered	T1,T2,T3

 LINE       3274
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T65,T78,T90
1	1	1	Covered	T5,T19,T20

 LINE       3665
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T79,T84,T80
1	0	Covered	T79,T84,T80
1	1	Covered	T1,T2,T3