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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.04 98.11 98.60 100.00 99.02 98.63 91.12


Total test records in report: 1079
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1004 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.797682768 Aug 25 07:38:09 AM UTC 24 Aug 25 07:38:33 AM UTC 24 886731904 ps
T1005 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4203732276 Aug 25 07:38:29 AM UTC 24 Aug 25 07:38:33 AM UTC 24 34196682 ps
T1006 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.3426265880 Aug 25 07:38:33 AM UTC 24 Aug 25 07:38:39 AM UTC 24 742305508 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.2993366587 Aug 25 07:38:36 AM UTC 24 Aug 25 07:38:40 AM UTC 24 47855132 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1718613851 Aug 25 07:38:29 AM UTC 24 Aug 25 07:38:33 AM UTC 24 304657056 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3147095668 Aug 25 07:38:22 AM UTC 24 Aug 25 07:38:33 AM UTC 24 530740808 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.297313503 Aug 25 07:38:30 AM UTC 24 Aug 25 07:38:34 AM UTC 24 280106885 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2068184310 Aug 25 07:38:29 AM UTC 24 Aug 25 07:38:34 AM UTC 24 121990186 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.20681673 Aug 25 07:38:31 AM UTC 24 Aug 25 07:38:34 AM UTC 24 16300046 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1767370755 Aug 25 07:38:29 AM UTC 24 Aug 25 07:38:34 AM UTC 24 205869969 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.702602817 Aug 25 07:38:29 AM UTC 24 Aug 25 07:38:34 AM UTC 24 35381553 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1518987854 Aug 25 07:38:31 AM UTC 24 Aug 25 07:38:34 AM UTC 24 22169711 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3346099790 Aug 25 07:38:29 AM UTC 24 Aug 25 07:38:35 AM UTC 24 102404635 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2799026332 Aug 25 07:38:31 AM UTC 24 Aug 25 07:38:35 AM UTC 24 159529716 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.3671709133 Aug 25 07:38:33 AM UTC 24 Aug 25 07:38:36 AM UTC 24 14033811 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.1301569066 Aug 25 07:38:33 AM UTC 24 Aug 25 07:38:36 AM UTC 24 27389084 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.2856090416 Aug 25 07:38:25 AM UTC 24 Aug 25 07:38:36 AM UTC 24 1839997121 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2566691055 Aug 25 07:38:31 AM UTC 24 Aug 25 07:38:36 AM UTC 24 51455209 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3099064407 Aug 25 07:38:31 AM UTC 24 Aug 25 07:38:37 AM UTC 24 123676102 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3735417475 Aug 25 07:38:33 AM UTC 24 Aug 25 07:38:37 AM UTC 24 58087929 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1415105653 Aug 25 07:38:31 AM UTC 24 Aug 25 07:38:37 AM UTC 24 182606097 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4236782981 Aug 25 07:38:33 AM UTC 24 Aug 25 07:38:37 AM UTC 24 85040589 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1494886107 Aug 25 07:38:31 AM UTC 24 Aug 25 07:38:38 AM UTC 24 77955071 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3389537048 Aug 25 07:38:35 AM UTC 24 Aug 25 07:38:38 AM UTC 24 29675091 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4151311574 Aug 25 07:38:29 AM UTC 24 Aug 25 07:38:38 AM UTC 24 917021418 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2910330280 Aug 25 07:38:33 AM UTC 24 Aug 25 07:38:39 AM UTC 24 1040822294 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2781926636 Aug 25 07:38:35 AM UTC 24 Aug 25 07:38:39 AM UTC 24 17637323 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1277716756 Aug 25 07:38:36 AM UTC 24 Aug 25 07:38:39 AM UTC 24 25178220 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.4108382244 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:40 AM UTC 24 27242344 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.1340620985 Aug 25 07:38:35 AM UTC 24 Aug 25 07:38:40 AM UTC 24 137931161 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2527868493 Aug 25 07:38:35 AM UTC 24 Aug 25 07:38:41 AM UTC 24 185841996 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.2516419927 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:41 AM UTC 24 91164966 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.829575611 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:41 AM UTC 24 17482859 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2065565208 Aug 25 07:38:36 AM UTC 24 Aug 25 07:38:42 AM UTC 24 109180817 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.1184003450 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:42 AM UTC 24 31170694 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2268872575 Aug 25 07:38:36 AM UTC 24 Aug 25 07:38:42 AM UTC 24 93296021 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3581986641 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:42 AM UTC 24 31716424 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1483770439 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:42 AM UTC 24 92504420 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.880600012 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:43 AM UTC 24 87632498 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1627621114 Aug 25 07:38:33 AM UTC 24 Aug 25 07:38:43 AM UTC 24 844910768 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.3749614844 Aug 25 07:38:40 AM UTC 24 Aug 25 07:38:43 AM UTC 24 48576151 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2689720216 Aug 25 07:38:40 AM UTC 24 Aug 25 07:38:43 AM UTC 24 24995444 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2597131744 Aug 25 07:38:40 AM UTC 24 Aug 25 07:38:43 AM UTC 24 13050621 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2973191785 Aug 25 07:38:40 AM UTC 24 Aug 25 07:38:43 AM UTC 24 30209020 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.27010802 Aug 25 07:38:36 AM UTC 24 Aug 25 07:38:43 AM UTC 24 715478866 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.931817430 Aug 25 07:38:36 AM UTC 24 Aug 25 07:38:43 AM UTC 24 77470812 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3654808794 Aug 25 07:38:40 AM UTC 24 Aug 25 07:38:44 AM UTC 24 40725114 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2193019572 Aug 25 07:38:42 AM UTC 24 Aug 25 07:38:44 AM UTC 24 14182592 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3934683591 Aug 25 07:38:42 AM UTC 24 Aug 25 07:38:45 AM UTC 24 11050855 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.14493507 Aug 25 07:38:42 AM UTC 24 Aug 25 07:38:45 AM UTC 24 122910847 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2631649452 Aug 25 07:38:42 AM UTC 24 Aug 25 07:38:45 AM UTC 24 9447404 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.48762381 Aug 25 07:38:42 AM UTC 24 Aug 25 07:38:45 AM UTC 24 18108432 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1372485957 Aug 25 07:38:42 AM UTC 24 Aug 25 07:38:45 AM UTC 24 41123917 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.973179212 Aug 25 07:38:40 AM UTC 24 Aug 25 07:38:45 AM UTC 24 110083631 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.436572043 Aug 25 07:38:35 AM UTC 24 Aug 25 07:38:45 AM UTC 24 139253353 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.743112521 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:45 AM UTC 24 183315879 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.311502874 Aug 25 07:38:44 AM UTC 24 Aug 25 07:38:47 AM UTC 24 23098819 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1877444048 Aug 25 07:38:44 AM UTC 24 Aug 25 07:38:47 AM UTC 24 31271175 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2070159370 Aug 25 07:38:44 AM UTC 24 Aug 25 07:38:47 AM UTC 24 62068156 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.407405766 Aug 25 07:38:44 AM UTC 24 Aug 25 07:38:47 AM UTC 24 34883163 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2411135791 Aug 25 07:38:44 AM UTC 24 Aug 25 07:38:47 AM UTC 24 17112801 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.2712129854 Aug 25 07:38:44 AM UTC 24 Aug 25 07:38:47 AM UTC 24 16615677 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3975772859 Aug 25 07:38:45 AM UTC 24 Aug 25 07:38:47 AM UTC 24 29381739 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3548157694 Aug 25 07:38:35 AM UTC 24 Aug 25 07:38:48 AM UTC 24 411632632 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.4177243212 Aug 25 07:38:45 AM UTC 24 Aug 25 07:38:48 AM UTC 24 11853497 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.3658686461 Aug 25 07:38:45 AM UTC 24 Aug 25 07:38:48 AM UTC 24 14926166 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2120771067 Aug 25 07:38:45 AM UTC 24 Aug 25 07:38:48 AM UTC 24 8914338 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3918983955 Aug 25 07:38:45 AM UTC 24 Aug 25 07:38:48 AM UTC 24 29190868 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1049432031 Aug 25 07:38:45 AM UTC 24 Aug 25 07:38:48 AM UTC 24 12770959 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1747707918 Aug 25 07:38:30 AM UTC 24 Aug 25 07:38:48 AM UTC 24 1419964574 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.1347737787 Aug 25 07:38:45 AM UTC 24 Aug 25 07:38:48 AM UTC 24 22035159 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1941236140 Aug 25 07:38:38 AM UTC 24 Aug 25 07:38:48 AM UTC 24 937850293 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1328063860 Aug 25 07:38:47 AM UTC 24 Aug 25 07:38:50 AM UTC 24 26694022 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3467218629 Aug 25 07:38:47 AM UTC 24 Aug 25 07:38:50 AM UTC 24 14808038 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.3929380675 Aug 25 07:38:47 AM UTC 24 Aug 25 07:38:50 AM UTC 24 13787498 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.109752458 Aug 25 07:38:47 AM UTC 24 Aug 25 07:38:50 AM UTC 24 34624367 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3961186432 Aug 25 07:38:47 AM UTC 24 Aug 25 07:38:50 AM UTC 24 10346301 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.2569325131 Aug 25 07:38:47 AM UTC 24 Aug 25 07:38:50 AM UTC 24 21212089 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.860505999 Aug 25 07:38:47 AM UTC 24 Aug 25 07:38:50 AM UTC 24 17484017 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.3677862761
Short name T5
Test name
Test status
Simulation time 536762532 ps
CPU time 4.5 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:07 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677862761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3677862761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.2155298066
Short name T6
Test name
Test status
Simulation time 3422560358 ps
CPU time 35.89 seconds
Started Aug 25 07:29:22 AM UTC 24
Finished Aug 25 07:29:59 AM UTC 24
Peak memory 232568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155298066 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2155298066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.3926182175
Short name T19
Test name
Test status
Simulation time 185671620 ps
CPU time 10.78 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:13 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926182175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3926182175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.2416192367
Short name T70
Test name
Test status
Simulation time 3026329143 ps
CPU time 30.82 seconds
Started Aug 25 07:29:10 AM UTC 24
Finished Aug 25 07:29:43 AM UTC 24
Peak memory 232136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416192367 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2416192367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.1143883701
Short name T11
Test name
Test status
Simulation time 4427784890 ps
CPU time 22.41 seconds
Started Aug 25 07:29:10 AM UTC 24
Finished Aug 25 07:29:34 AM UTC 24
Peak memory 256480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143883701 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1143883701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.2370052521
Short name T92
Test name
Test status
Simulation time 2207505116 ps
CPU time 24.94 seconds
Started Aug 25 07:31:01 AM UTC 24
Finished Aug 25 07:31:28 AM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2370052521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr
_stress_all_with_rand_reset.2370052521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2495999921
Short name T86
Test name
Test status
Simulation time 492741096 ps
CPU time 11.09 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:37:57 AM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495999921 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.2495999921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.3594398655
Short name T82
Test name
Test status
Simulation time 1130210863 ps
CPU time 18.04 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:20 AM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594398655 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3594398655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.2077315952
Short name T136
Test name
Test status
Simulation time 2646443609 ps
CPU time 82.07 seconds
Started Aug 25 07:30:08 AM UTC 24
Finished Aug 25 07:31:32 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077315952 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2077315952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.829735381
Short name T16
Test name
Test status
Simulation time 119234132 ps
CPU time 7.34 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:10 AM UTC 24
Peak memory 226132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829735381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.829735381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3335856848
Short name T269
Test name
Test status
Simulation time 500716207 ps
CPU time 16.96 seconds
Started Aug 25 07:30:25 AM UTC 24
Finished Aug 25 07:30:43 AM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335856848 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3335856848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.3707797235
Short name T108
Test name
Test status
Simulation time 3961522430 ps
CPU time 38.7 seconds
Started Aug 25 07:30:17 AM UTC 24
Finished Aug 25 07:30:57 AM UTC 24
Peak memory 232312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707797235 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3707797235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.3149251245
Short name T9
Test name
Test status
Simulation time 108797795 ps
CPU time 4.01 seconds
Started Aug 25 07:34:44 AM UTC 24
Finished Aug 25 07:34:49 AM UTC 24
Peak memory 218244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149251245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3149251245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.462099418
Short name T78
Test name
Test status
Simulation time 876400217 ps
CPU time 20.65 seconds
Started Aug 25 07:29:39 AM UTC 24
Finished Aug 25 07:30:01 AM UTC 24
Peak memory 232464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=462099418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_
stress_all_with_rand_reset.462099418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.1242606140
Short name T891
Test name
Test status
Simulation time 7116868177 ps
CPU time 127.84 seconds
Started Aug 25 07:35:32 AM UTC 24
Finished Aug 25 07:37:43 AM UTC 24
Peak memory 228188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242606140 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1242606140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.866185816
Short name T27
Test name
Test status
Simulation time 144020438 ps
CPU time 8.73 seconds
Started Aug 25 07:32:16 AM UTC 24
Finished Aug 25 07:32:26 AM UTC 24
Peak memory 220356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866185816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.866185816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.712121878
Short name T49
Test name
Test status
Simulation time 57280726 ps
CPU time 3.38 seconds
Started Aug 25 07:32:06 AM UTC 24
Finished Aug 25 07:32:10 AM UTC 24
Peak memory 232416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712121878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.712121878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3747964142
Short name T79
Test name
Test status
Simulation time 282060507 ps
CPU time 5.64 seconds
Started Aug 25 07:37:42 AM UTC 24
Finished Aug 25 07:37:49 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747964142 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.3747964142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.812290018
Short name T218
Test name
Test status
Simulation time 1828342720 ps
CPU time 30.96 seconds
Started Aug 25 07:29:52 AM UTC 24
Finished Aug 25 07:30:24 AM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812290018 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.812290018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.1443760402
Short name T363
Test name
Test status
Simulation time 849140192 ps
CPU time 13.81 seconds
Started Aug 25 07:33:20 AM UTC 24
Finished Aug 25 07:33:35 AM UTC 24
Peak memory 232208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443760402 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1443760402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.4289475208
Short name T20
Test name
Test status
Simulation time 93691926 ps
CPU time 4.35 seconds
Started Aug 25 07:29:17 AM UTC 24
Finished Aug 25 07:29:23 AM UTC 24
Peak memory 232220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289475208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4289475208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.3512613849
Short name T90
Test name
Test status
Simulation time 1212167183 ps
CPU time 23.83 seconds
Started Aug 25 07:30:18 AM UTC 24
Finished Aug 25 07:30:44 AM UTC 24
Peak memory 232312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3512613849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr
_stress_all_with_rand_reset.3512613849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.2970517104
Short name T244
Test name
Test status
Simulation time 256848065 ps
CPU time 9.84 seconds
Started Aug 25 07:31:45 AM UTC 24
Finished Aug 25 07:31:57 AM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970517104 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2970517104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1006904228
Short name T80
Test name
Test status
Simulation time 181754425 ps
CPU time 4.34 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:37:51 AM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006904228 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.1006904228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.929866458
Short name T37
Test name
Test status
Simulation time 314693292 ps
CPU time 5.33 seconds
Started Aug 25 07:29:50 AM UTC 24
Finished Aug 25 07:29:57 AM UTC 24
Peak memory 224528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929866458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.929866458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.344004439
Short name T65
Test name
Test status
Simulation time 319426752 ps
CPU time 15.64 seconds
Started Aug 25 07:29:10 AM UTC 24
Finished Aug 25 07:29:27 AM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=344004439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_
stress_all_with_rand_reset.344004439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.2438052702
Short name T22
Test name
Test status
Simulation time 49484518 ps
CPU time 4.83 seconds
Started Aug 25 07:31:22 AM UTC 24
Finished Aug 25 07:31:28 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438052702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2438052702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.693205989
Short name T123
Test name
Test status
Simulation time 162179905 ps
CPU time 5.44 seconds
Started Aug 25 07:32:40 AM UTC 24
Finished Aug 25 07:32:46 AM UTC 24
Peak memory 228580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693205989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.693205989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.1268179551
Short name T283
Test name
Test status
Simulation time 608882835 ps
CPU time 40.83 seconds
Started Aug 25 07:33:40 AM UTC 24
Finished Aug 25 07:34:22 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268179551 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1268179551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.4071485635
Short name T148
Test name
Test status
Simulation time 2569967737 ps
CPU time 35.5 seconds
Started Aug 25 07:33:15 AM UTC 24
Finished Aug 25 07:33:53 AM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4071485635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymg
r_stress_all_with_rand_reset.4071485635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.744706851
Short name T248
Test name
Test status
Simulation time 1883164326 ps
CPU time 28.36 seconds
Started Aug 25 07:31:25 AM UTC 24
Finished Aug 25 07:31:55 AM UTC 24
Peak memory 232324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744706851 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.744706851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.2497989103
Short name T440
Test name
Test status
Simulation time 4883752195 ps
CPU time 54.2 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:35:28 AM UTC 24
Peak memory 226580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497989103 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2497989103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3126388556
Short name T135
Test name
Test status
Simulation time 1912472259 ps
CPU time 19.15 seconds
Started Aug 25 07:30:29 AM UTC 24
Finished Aug 25 07:30:50 AM UTC 24
Peak memory 219488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126388556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3126388556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.901978059
Short name T235
Test name
Test status
Simulation time 962072846 ps
CPU time 33.98 seconds
Started Aug 25 07:31:38 AM UTC 24
Finished Aug 25 07:32:14 AM UTC 24
Peak memory 232332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901978059 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.901978059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.2926885183
Short name T146
Test name
Test status
Simulation time 1504533163 ps
CPU time 60.39 seconds
Started Aug 25 07:31:13 AM UTC 24
Finished Aug 25 07:32:16 AM UTC 24
Peak memory 232516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926885183 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2926885183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.1073834836
Short name T427
Test name
Test status
Simulation time 410060954 ps
CPU time 25.21 seconds
Started Aug 25 07:37:06 AM UTC 24
Finished Aug 25 07:37:33 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073834836 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1073834836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.3681757790
Short name T163
Test name
Test status
Simulation time 260530005 ps
CPU time 10.06 seconds
Started Aug 25 07:38:09 AM UTC 24
Finished Aug 25 07:38:20 AM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681757790 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.3681757790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.1113082190
Short name T62
Test name
Test status
Simulation time 19925294 ps
CPU time 1.23 seconds
Started Aug 25 07:29:10 AM UTC 24
Finished Aug 25 07:29:13 AM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113082190 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1113082190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.531153447
Short name T60
Test name
Test status
Simulation time 148581341 ps
CPU time 4.67 seconds
Started Aug 25 07:29:35 AM UTC 24
Finished Aug 25 07:29:40 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531153447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.531153447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.3024775402
Short name T139
Test name
Test status
Simulation time 3178969495 ps
CPU time 26.43 seconds
Started Aug 25 07:32:17 AM UTC 24
Finished Aug 25 07:32:45 AM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024775402 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3024775402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.4174787696
Short name T299
Test name
Test status
Simulation time 1175436003 ps
CPU time 50.92 seconds
Started Aug 25 07:35:21 AM UTC 24
Finished Aug 25 07:36:14 AM UTC 24
Peak memory 226112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174787696 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4174787696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.2543021936
Short name T268
Test name
Test status
Simulation time 3390177973 ps
CPU time 121.9 seconds
Started Aug 25 07:32:22 AM UTC 24
Finished Aug 25 07:34:27 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543021936 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2543021936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.604599251
Short name T216
Test name
Test status
Simulation time 1368233347 ps
CPU time 10.18 seconds
Started Aug 25 07:30:29 AM UTC 24
Finished Aug 25 07:30:41 AM UTC 24
Peak memory 215612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604599251 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.604599251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.713884233
Short name T230
Test name
Test status
Simulation time 35446499 ps
CPU time 3.73 seconds
Started Aug 25 07:31:36 AM UTC 24
Finished Aug 25 07:31:41 AM UTC 24
Peak memory 230288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713884233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.713884233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.2281575505
Short name T165
Test name
Test status
Simulation time 879336479 ps
CPU time 3.14 seconds
Started Aug 25 07:38:18 AM UTC 24
Finished Aug 25 07:38:23 AM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281575505 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.2281575505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.490256789
Short name T46
Test name
Test status
Simulation time 146015032 ps
CPU time 2.87 seconds
Started Aug 25 07:30:43 AM UTC 24
Finished Aug 25 07:30:48 AM UTC 24
Peak memory 232480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490256789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.490256789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.1589927896
Short name T125
Test name
Test status
Simulation time 62840844 ps
CPU time 3.68 seconds
Started Aug 25 07:34:30 AM UTC 24
Finished Aug 25 07:34:35 AM UTC 24
Peak memory 226544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589927896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1589927896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.4093737830
Short name T17
Test name
Test status
Simulation time 88184694 ps
CPU time 2.86 seconds
Started Aug 25 07:29:06 AM UTC 24
Finished Aug 25 07:29:11 AM UTC 24
Peak memory 218184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093737830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4093737830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.432315960
Short name T310
Test name
Test status
Simulation time 74199765 ps
CPU time 3.08 seconds
Started Aug 25 07:33:03 AM UTC 24
Finished Aug 25 07:33:07 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432315960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.432315960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.1275554368
Short name T238
Test name
Test status
Simulation time 2898054547 ps
CPU time 36.05 seconds
Started Aug 25 07:33:05 AM UTC 24
Finished Aug 25 07:33:43 AM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275554368 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1275554368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.2466075831
Short name T284
Test name
Test status
Simulation time 14774267867 ps
CPU time 70.44 seconds
Started Aug 25 07:34:18 AM UTC 24
Finished Aug 25 07:35:30 AM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466075831 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2466075831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.1428840599
Short name T169
Test name
Test status
Simulation time 393872853 ps
CPU time 12 seconds
Started Aug 25 07:37:50 AM UTC 24
Finished Aug 25 07:38:03 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428840599 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.1428840599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.1327246763
Short name T183
Test name
Test status
Simulation time 79111727 ps
CPU time 2.72 seconds
Started Aug 25 07:31:12 AM UTC 24
Finished Aug 25 07:31:16 AM UTC 24
Peak memory 220296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327246763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1327246763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.17701179
Short name T25
Test name
Test status
Simulation time 276537457 ps
CPU time 4.4 seconds
Started Aug 25 07:30:02 AM UTC 24
Finished Aug 25 07:30:08 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17701179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.17701179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.835186463
Short name T124
Test name
Test status
Simulation time 163031141 ps
CPU time 6.52 seconds
Started Aug 25 07:35:41 AM UTC 24
Finished Aug 25 07:35:49 AM UTC 24
Peak memory 232540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835186463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.835186463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.3582607593
Short name T127
Test name
Test status
Simulation time 57242905 ps
CPU time 3.77 seconds
Started Aug 25 07:35:48 AM UTC 24
Finished Aug 25 07:35:53 AM UTC 24
Peak memory 228736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582607593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3582607593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.1009861940
Short name T111
Test name
Test status
Simulation time 263751419 ps
CPU time 5.29 seconds
Started Aug 25 07:30:58 AM UTC 24
Finished Aug 25 07:31:05 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009861940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1009861940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.1630223991
Short name T14
Test name
Test status
Simulation time 147443836 ps
CPU time 3.73 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:06 AM UTC 24
Peak memory 226224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630223991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1630223991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.1079726693
Short name T351
Test name
Test status
Simulation time 53801911 ps
CPU time 6.27 seconds
Started Aug 25 07:31:19 AM UTC 24
Finished Aug 25 07:31:27 AM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079726693 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1079726693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.3212359409
Short name T349
Test name
Test status
Simulation time 723201701 ps
CPU time 47.39 seconds
Started Aug 25 07:32:35 AM UTC 24
Finished Aug 25 07:33:24 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212359409 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3212359409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.3888262919
Short name T382
Test name
Test status
Simulation time 85852295 ps
CPU time 5.76 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:55 AM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888262919 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3888262919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.1325580314
Short name T152
Test name
Test status
Simulation time 5850373855 ps
CPU time 93.83 seconds
Started Aug 25 07:34:36 AM UTC 24
Finished Aug 25 07:36:13 AM UTC 24
Peak memory 232572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325580314 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1325580314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.675391108
Short name T58
Test name
Test status
Simulation time 156013009 ps
CPU time 4.49 seconds
Started Aug 25 07:34:52 AM UTC 24
Finished Aug 25 07:34:58 AM UTC 24
Peak memory 230444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675391108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.675391108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.106075083
Short name T346
Test name
Test status
Simulation time 648274826 ps
CPU time 7.05 seconds
Started Aug 25 07:35:19 AM UTC 24
Finished Aug 25 07:35:27 AM UTC 24
Peak memory 231272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106075083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.106075083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.3017639667
Short name T374
Test name
Test status
Simulation time 69144199 ps
CPU time 6.27 seconds
Started Aug 25 07:35:39 AM UTC 24
Finished Aug 25 07:35:46 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017639667 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3017639667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.810090371
Short name T167
Test name
Test status
Simulation time 1515964311 ps
CPU time 8.78 seconds
Started Aug 25 07:37:43 AM UTC 24
Finished Aug 25 07:37:53 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810090371 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.810090371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.303130514
Short name T24
Test name
Test status
Simulation time 35993753 ps
CPU time 3.68 seconds
Started Aug 25 07:32:06 AM UTC 24
Finished Aug 25 07:32:11 AM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303130514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.303130514
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.1017443773
Short name T256
Test name
Test status
Simulation time 914966460 ps
CPU time 6.88 seconds
Started Aug 25 07:32:16 AM UTC 24
Finished Aug 25 07:32:24 AM UTC 24
Peak memory 224060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017443773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1017443773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.464228661
Short name T257
Test name
Test status
Simulation time 122408287 ps
CPU time 4.32 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:34:57 AM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464228661 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.464228661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1711277224
Short name T766
Test name
Test status
Simulation time 1193054360 ps
CPU time 53.63 seconds
Started Aug 25 07:35:34 AM UTC 24
Finished Aug 25 07:36:30 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711277224 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1711277224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.78771430
Short name T390
Test name
Test status
Simulation time 58906107 ps
CPU time 3.93 seconds
Started Aug 25 07:31:04 AM UTC 24
Finished Aug 25 07:31:09 AM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78771430 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.78771430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3346099790
Short name T182
Test name
Test status
Simulation time 102404635 ps
CPU time 4.2 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:35 AM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346099790 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.3346099790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.1797677642
Short name T177
Test name
Test status
Simulation time 635875052 ps
CPU time 3.43 seconds
Started Aug 25 07:34:30 AM UTC 24
Finished Aug 25 07:34:35 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797677642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1797677642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.1979093891
Short name T126
Test name
Test status
Simulation time 801444372 ps
CPU time 6.19 seconds
Started Aug 25 07:37:08 AM UTC 24
Finished Aug 25 07:37:16 AM UTC 24
Peak memory 230532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979093891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1979093891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.2815453562
Short name T88
Test name
Test status
Simulation time 270015203 ps
CPU time 4.17 seconds
Started Aug 25 07:29:11 AM UTC 24
Finished Aug 25 07:29:16 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815453562 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2815453562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.1886660931
Short name T47
Test name
Test status
Simulation time 284029618 ps
CPU time 3.97 seconds
Started Aug 25 07:31:48 AM UTC 24
Finished Aug 25 07:31:53 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886660931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1886660931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.2768808274
Short name T199
Test name
Test status
Simulation time 1302280927 ps
CPU time 42.98 seconds
Started Aug 25 07:32:58 AM UTC 24
Finished Aug 25 07:33:43 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768808274 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2768808274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.3671936304
Short name T279
Test name
Test status
Simulation time 40949551 ps
CPU time 2.92 seconds
Started Aug 25 07:34:16 AM UTC 24
Finished Aug 25 07:34:20 AM UTC 24
Peak memory 226016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671936304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3671936304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.3505879993
Short name T233
Test name
Test status
Simulation time 72698399 ps
CPU time 4.27 seconds
Started Aug 25 07:37:06 AM UTC 24
Finished Aug 25 07:37:12 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505879993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3505879993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.1119625157
Short name T867
Test name
Test status
Simulation time 591645781 ps
CPU time 3.22 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:29 AM UTC 24
Peak memory 231060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119625157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1119625157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.2856090416
Short name T172
Test name
Test status
Simulation time 1839997121 ps
CPU time 9.02 seconds
Started Aug 25 07:38:25 AM UTC 24
Finished Aug 25 07:38:36 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856090416 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.2856090416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.27010802
Short name T179
Test name
Test status
Simulation time 715478866 ps
CPU time 5.95 seconds
Started Aug 25 07:38:36 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27010802 -assert nopostproc +UVM_TESTNAM
E=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.27010802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.2309380369
Short name T170
Test name
Test status
Simulation time 356542286 ps
CPU time 7.27 seconds
Started Aug 25 07:37:58 AM UTC 24
Finished Aug 25 07:38:07 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309380369 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.2309380369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.3755862849
Short name T12
Test name
Test status
Simulation time 1594746265 ps
CPU time 12.37 seconds
Started Aug 25 07:29:23 AM UTC 24
Finished Aug 25 07:29:37 AM UTC 24
Peak memory 254508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755862849 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3755862849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.3729786294
Short name T171
Test name
Test status
Simulation time 1725630765 ps
CPU time 5.98 seconds
Started Aug 25 07:34:18 AM UTC 24
Finished Aug 25 07:34:25 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729786294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3729786294
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.3335588200
Short name T121
Test name
Test status
Simulation time 58131565 ps
CPU time 4.77 seconds
Started Aug 25 07:30:03 AM UTC 24
Finished Aug 25 07:30:09 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335588200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3335588200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.770813958
Short name T129
Test name
Test status
Simulation time 327652604 ps
CPU time 6.24 seconds
Started Aug 25 07:37:17 AM UTC 24
Finished Aug 25 07:37:24 AM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770813958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.770813958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.1615223764
Short name T34
Test name
Test status
Simulation time 767824964 ps
CPU time 10.22 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:12 AM UTC 24
Peak memory 226400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615223764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1615223764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.647973697
Short name T83
Test name
Test status
Simulation time 683855543 ps
CPU time 7.04 seconds
Started Aug 25 07:29:13 AM UTC 24
Finished Aug 25 07:29:21 AM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647973697 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.647973697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.305960109
Short name T214
Test name
Test status
Simulation time 343411200 ps
CPU time 4.83 seconds
Started Aug 25 07:29:20 AM UTC 24
Finished Aug 25 07:29:27 AM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305960109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.305960109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.2605319929
Short name T277
Test name
Test status
Simulation time 51110749 ps
CPU time 2.88 seconds
Started Aug 25 07:31:22 AM UTC 24
Finished Aug 25 07:31:26 AM UTC 24
Peak memory 224296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605319929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2605319929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_random.3969877869
Short name T396
Test name
Test status
Simulation time 1103017321 ps
CPU time 53.98 seconds
Started Aug 25 07:31:18 AM UTC 24
Finished Aug 25 07:32:15 AM UTC 24
Peak memory 228276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969877869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3969877869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.430543815
Short name T463
Test name
Test status
Simulation time 77911707 ps
CPU time 4.51 seconds
Started Aug 25 07:31:17 AM UTC 24
Finished Aug 25 07:31:23 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430543815 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.430543815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.2185395563
Short name T402
Test name
Test status
Simulation time 797401998 ps
CPU time 5.32 seconds
Started Aug 25 07:31:30 AM UTC 24
Finished Aug 25 07:31:37 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185395563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2185395563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.758070636
Short name T309
Test name
Test status
Simulation time 522979851 ps
CPU time 4.12 seconds
Started Aug 25 07:31:50 AM UTC 24
Finished Aug 25 07:31:55 AM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758070636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.758070636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.75799187
Short name T263
Test name
Test status
Simulation time 44901658 ps
CPU time 4.53 seconds
Started Aug 25 07:31:58 AM UTC 24
Finished Aug 25 07:32:03 AM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75799187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keym
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.75799187
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.3427381862
Short name T329
Test name
Test status
Simulation time 204908652 ps
CPU time 7.74 seconds
Started Aug 25 07:32:09 AM UTC 24
Finished Aug 25 07:32:18 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427381862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3427381862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.2793806796
Short name T8
Test name
Test status
Simulation time 61977673 ps
CPU time 6.14 seconds
Started Aug 25 07:32:36 AM UTC 24
Finished Aug 25 07:32:44 AM UTC 24
Peak memory 220052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793806796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2793806796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.3398864697
Short name T308
Test name
Test status
Simulation time 510620387 ps
CPU time 8.71 seconds
Started Aug 25 07:32:52 AM UTC 24
Finished Aug 25 07:33:02 AM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398864697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3398864697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.1362051536
Short name T369
Test name
Test status
Simulation time 262538379 ps
CPU time 5.37 seconds
Started Aug 25 07:33:11 AM UTC 24
Finished Aug 25 07:33:18 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362051536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1362051536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.7277106
Short name T243
Test name
Test status
Simulation time 333238235 ps
CPU time 5.09 seconds
Started Aug 25 07:34:05 AM UTC 24
Finished Aug 25 07:34:11 AM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7277106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.7277106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.3902312417
Short name T228
Test name
Test status
Simulation time 638505304 ps
CPU time 22.05 seconds
Started Aug 25 07:34:45 AM UTC 24
Finished Aug 25 07:35:09 AM UTC 24
Peak memory 231884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3902312417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg
r_stress_all_with_rand_reset.3902312417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.2611931781
Short name T222
Test name
Test status
Simulation time 305500526 ps
CPU time 8.9 seconds
Started Aug 25 07:35:09 AM UTC 24
Finished Aug 25 07:35:19 AM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611931781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2611931781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.1385471479
Short name T366
Test name
Test status
Simulation time 441050261 ps
CPU time 4.31 seconds
Started Aug 25 07:35:25 AM UTC 24
Finished Aug 25 07:35:31 AM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385471479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1385471479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3131209465
Short name T239
Test name
Test status
Simulation time 238680452 ps
CPU time 4.35 seconds
Started Aug 25 07:35:40 AM UTC 24
Finished Aug 25 07:35:45 AM UTC 24
Peak memory 217868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131209465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3131209465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.1122766130
Short name T332
Test name
Test status
Simulation time 98121533 ps
CPU time 4.88 seconds
Started Aug 25 07:36:43 AM UTC 24
Finished Aug 25 07:36:49 AM UTC 24
Peak memory 228220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122766130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1122766130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.915971888
Short name T290
Test name
Test status
Simulation time 1147599325 ps
CPU time 15.39 seconds
Started Aug 25 07:36:51 AM UTC 24
Finished Aug 25 07:37:08 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915971888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.915971888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.238049945
Short name T242
Test name
Test status
Simulation time 170833115 ps
CPU time 4.43 seconds
Started Aug 25 07:37:08 AM UTC 24
Finished Aug 25 07:37:14 AM UTC 24
Peak memory 218304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238049945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.238049945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.2917099271
Short name T318
Test name
Test status
Simulation time 122496217 ps
CPU time 6.62 seconds
Started Aug 25 07:37:36 AM UTC 24
Finished Aug 25 07:37:45 AM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917099271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2917099271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.3364704272
Short name T109
Test name
Test status
Simulation time 172071747 ps
CPU time 6.35 seconds
Started Aug 25 07:31:07 AM UTC 24
Finished Aug 25 07:31:15 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364704272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3364704272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.3999472906
Short name T942
Test name
Test status
Simulation time 2025791670 ps
CPU time 23.88 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:38:10 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999472906 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3999472906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1528744116
Short name T974
Test name
Test status
Simulation time 3578994857 ps
CPU time 36.3 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:38:23 AM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528744116 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1528744116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3216511198
Short name T160
Test name
Test status
Simulation time 117021743 ps
CPU time 1.49 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:37:47 AM UTC 24
Peak memory 213648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216511198 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3216511198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.12947509
Short name T162
Test name
Test status
Simulation time 31335750 ps
CPU time 2.45 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:37:49 AM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=12947509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_wit
h_rand_reset.12947509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.3770991560
Short name T161
Test name
Test status
Simulation time 53593081 ps
CPU time 2.38 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:37:48 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770991560 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3770991560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.674943912
Short name T910
Test name
Test status
Simulation time 29458409 ps
CPU time 1.1 seconds
Started Aug 25 07:37:43 AM UTC 24
Finished Aug 25 07:37:46 AM UTC 24
Peak memory 214868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674943912 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.674943912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1637978483
Short name T113
Test name
Test status
Simulation time 83178481 ps
CPU time 2.29 seconds
Started Aug 25 07:37:45 AM UTC 24
Finished Aug 25 07:37:48 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637978483 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1637978483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3781736541
Short name T84
Test name
Test status
Simulation time 131956360 ps
CPU time 6.45 seconds
Started Aug 25 07:37:42 AM UTC 24
Finished Aug 25 07:37:50 AM UTC 24
Peak memory 225948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781736541 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.3781736541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.2609890171
Short name T911
Test name
Test status
Simulation time 38924079 ps
CPU time 4.44 seconds
Started Aug 25 07:37:42 AM UTC 24
Finished Aug 25 07:37:48 AM UTC 24
Peak memory 226104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609890171 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2609890171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.3909619848
Short name T937
Test name
Test status
Simulation time 713396550 ps
CPU time 19.26 seconds
Started Aug 25 07:37:47 AM UTC 24
Finished Aug 25 07:38:08 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909619848 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3909619848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3271401217
Short name T931
Test name
Test status
Simulation time 2215322238 ps
CPU time 17.63 seconds
Started Aug 25 07:37:46 AM UTC 24
Finished Aug 25 07:38:05 AM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271401217 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3271401217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3214898950
Short name T913
Test name
Test status
Simulation time 20067840 ps
CPU time 1.72 seconds
Started Aug 25 07:37:46 AM UTC 24
Finished Aug 25 07:37:49 AM UTC 24
Peak memory 223956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214898950 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3214898950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1447744346
Short name T189
Test name
Test status
Simulation time 84703623 ps
CPU time 1.65 seconds
Started Aug 25 07:37:49 AM UTC 24
Finished Aug 25 07:37:53 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1447744346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w
ith_rand_reset.1447744346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.1670118890
Short name T114
Test name
Test status
Simulation time 19347300 ps
CPU time 1.43 seconds
Started Aug 25 07:37:46 AM UTC 24
Finished Aug 25 07:37:49 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670118890 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1670118890
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.3815193344
Short name T912
Test name
Test status
Simulation time 12632283 ps
CPU time 1.1 seconds
Started Aug 25 07:37:46 AM UTC 24
Finished Aug 25 07:37:48 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815193344 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3815193344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.34644530
Short name T115
Test name
Test status
Simulation time 351431885 ps
CPU time 3.88 seconds
Started Aug 25 07:37:48 AM UTC 24
Finished Aug 25 07:37:54 AM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34644530 -assert nopostproc +UV
M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.34644530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.1597420781
Short name T914
Test name
Test status
Simulation time 88433967 ps
CPU time 2.39 seconds
Started Aug 25 07:37:46 AM UTC 24
Finished Aug 25 07:37:50 AM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597420781 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1597420781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.2795953786
Short name T178
Test name
Test status
Simulation time 54800044 ps
CPU time 3.55 seconds
Started Aug 25 07:37:46 AM UTC 24
Finished Aug 25 07:37:51 AM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795953786 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.2795953786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.262041419
Short name T973
Test name
Test status
Simulation time 30274551 ps
CPU time 1.99 seconds
Started Aug 25 07:38:19 AM UTC 24
Finished Aug 25 07:38:22 AM UTC 24
Peak memory 223828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=262041419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_w
ith_rand_reset.262041419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.305928408
Short name T971
Test name
Test status
Simulation time 48662208 ps
CPU time 1.22 seconds
Started Aug 25 07:38:18 AM UTC 24
Finished Aug 25 07:38:22 AM UTC 24
Peak memory 213476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305928408 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.305928408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.3959278171
Short name T970
Test name
Test status
Simulation time 33704063 ps
CPU time 1.18 seconds
Started Aug 25 07:38:18 AM UTC 24
Finished Aug 25 07:38:22 AM UTC 24
Peak memory 213312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959278171 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3959278171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4225300209
Short name T984
Test name
Test status
Simulation time 1006152430 ps
CPU time 5.69 seconds
Started Aug 25 07:38:19 AM UTC 24
Finished Aug 25 07:38:26 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225300209 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.4225300209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3279795418
Short name T972
Test name
Test status
Simulation time 330847544 ps
CPU time 3.5 seconds
Started Aug 25 07:38:17 AM UTC 24
Finished Aug 25 07:38:22 AM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279795418 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.3279795418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2687180521
Short name T989
Test name
Test status
Simulation time 194512968 ps
CPU time 8.74 seconds
Started Aug 25 07:38:17 AM UTC 24
Finished Aug 25 07:38:28 AM UTC 24
Peak memory 226572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687180521 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.2687180521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.2938268651
Short name T975
Test name
Test status
Simulation time 330590704 ps
CPU time 4.54 seconds
Started Aug 25 07:38:17 AM UTC 24
Finished Aug 25 07:38:24 AM UTC 24
Peak memory 228224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938268651 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2938268651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1920775723
Short name T985
Test name
Test status
Simulation time 39709897 ps
CPU time 2.98 seconds
Started Aug 25 07:38:22 AM UTC 24
Finished Aug 25 07:38:26 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1920775723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_
with_rand_reset.1920775723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.3686746715
Short name T978
Test name
Test status
Simulation time 17292413 ps
CPU time 1.34 seconds
Started Aug 25 07:38:21 AM UTC 24
Finished Aug 25 07:38:24 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686746715 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3686746715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.2723731539
Short name T977
Test name
Test status
Simulation time 12693540 ps
CPU time 1.22 seconds
Started Aug 25 07:38:21 AM UTC 24
Finished Aug 25 07:38:24 AM UTC 24
Peak memory 213140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723731539 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2723731539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3635993756
Short name T988
Test name
Test status
Simulation time 125167515 ps
CPU time 4.98 seconds
Started Aug 25 07:38:21 AM UTC 24
Finished Aug 25 07:38:28 AM UTC 24
Peak memory 215792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635993756 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.3635993756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1384795355
Short name T981
Test name
Test status
Simulation time 359836244 ps
CPU time 4.21 seconds
Started Aug 25 07:38:20 AM UTC 24
Finished Aug 25 07:38:26 AM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384795355 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.1384795355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2452965607
Short name T987
Test name
Test status
Simulation time 87707596 ps
CPU time 5.72 seconds
Started Aug 25 07:38:20 AM UTC 24
Finished Aug 25 07:38:27 AM UTC 24
Peak memory 230080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452965607 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.2452965607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.2198341655
Short name T979
Test name
Test status
Simulation time 67263376 ps
CPU time 2.79 seconds
Started Aug 25 07:38:20 AM UTC 24
Finished Aug 25 07:38:25 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198341655 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2198341655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.2901669218
Short name T166
Test name
Test status
Simulation time 335474178 ps
CPU time 10.37 seconds
Started Aug 25 07:38:20 AM UTC 24
Finished Aug 25 07:38:32 AM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901669218 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.2901669218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.851656644
Short name T990
Test name
Test status
Simulation time 44584284 ps
CPU time 1.3 seconds
Started Aug 25 07:38:25 AM UTC 24
Finished Aug 25 07:38:28 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=851656644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_w
ith_rand_reset.851656644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.1534969051
Short name T983
Test name
Test status
Simulation time 122408017 ps
CPU time 1.18 seconds
Started Aug 25 07:38:24 AM UTC 24
Finished Aug 25 07:38:26 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534969051 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1534969051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.4092826402
Short name T982
Test name
Test status
Simulation time 13506079 ps
CPU time 1.23 seconds
Started Aug 25 07:38:24 AM UTC 24
Finished Aug 25 07:38:26 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092826402 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4092826402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1160643306
Short name T999
Test name
Test status
Simulation time 114347326 ps
CPU time 5.36 seconds
Started Aug 25 07:38:25 AM UTC 24
Finished Aug 25 07:38:32 AM UTC 24
Peak memory 216104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160643306 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.1160643306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2219046253
Short name T994
Test name
Test status
Simulation time 343653126 ps
CPU time 6.21 seconds
Started Aug 25 07:38:22 AM UTC 24
Finished Aug 25 07:38:30 AM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219046253 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.2219046253
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3147095668
Short name T1009
Test name
Test status
Simulation time 530740808 ps
CPU time 9.87 seconds
Started Aug 25 07:38:22 AM UTC 24
Finished Aug 25 07:38:33 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147095668 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.3147095668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.3829566342
Short name T995
Test name
Test status
Simulation time 430569372 ps
CPU time 6.69 seconds
Started Aug 25 07:38:22 AM UTC 24
Finished Aug 25 07:38:30 AM UTC 24
Peak memory 226464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829566342 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3829566342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.3290678686
Short name T174
Test name
Test status
Simulation time 57377212 ps
CPU time 3.83 seconds
Started Aug 25 07:38:23 AM UTC 24
Finished Aug 25 07:38:29 AM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290678686 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.3290678686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4203732276
Short name T1005
Test name
Test status
Simulation time 34196682 ps
CPU time 2.74 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:33 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4203732276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_
with_rand_reset.4203732276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.462174112
Short name T992
Test name
Test status
Simulation time 64485464 ps
CPU time 1.47 seconds
Started Aug 25 07:38:26 AM UTC 24
Finished Aug 25 07:38:29 AM UTC 24
Peak memory 213468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462174112 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.462174112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.2137423826
Short name T991
Test name
Test status
Simulation time 9752987 ps
CPU time 1.24 seconds
Started Aug 25 07:38:26 AM UTC 24
Finished Aug 25 07:38:29 AM UTC 24
Peak memory 213488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137423826 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2137423826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1767370755
Short name T1013
Test name
Test status
Simulation time 205869969 ps
CPU time 3.4 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:34 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767370755 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.1767370755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3107314336
Short name T993
Test name
Test status
Simulation time 151496716 ps
CPU time 2.83 seconds
Started Aug 25 07:38:25 AM UTC 24
Finished Aug 25 07:38:30 AM UTC 24
Peak memory 226512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107314336 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.3107314336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.531896423
Short name T998
Test name
Test status
Simulation time 72660260 ps
CPU time 4.68 seconds
Started Aug 25 07:38:25 AM UTC 24
Finished Aug 25 07:38:31 AM UTC 24
Peak memory 233116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531896423 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.531896423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.1936736318
Short name T1001
Test name
Test status
Simulation time 117819754 ps
CPU time 5.47 seconds
Started Aug 25 07:38:25 AM UTC 24
Finished Aug 25 07:38:32 AM UTC 24
Peak memory 226048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936736318 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1936736318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2068184310
Short name T1011
Test name
Test status
Simulation time 121990186 ps
CPU time 2.9 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:34 AM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2068184310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_
with_rand_reset.2068184310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.420303434
Short name T1003
Test name
Test status
Simulation time 222056469 ps
CPU time 2.27 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:33 AM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420303434 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.420303434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.452005166
Short name T1000
Test name
Test status
Simulation time 59240860 ps
CPU time 1.29 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:32 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452005166 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.452005166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3378428674
Short name T1002
Test name
Test status
Simulation time 44974593 ps
CPU time 1.78 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:32 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378428674 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.3378428674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1718613851
Short name T1008
Test name
Test status
Simulation time 304657056 ps
CPU time 3.02 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:33 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718613851 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.1718613851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4151311574
Short name T1026
Test name
Test status
Simulation time 917021418 ps
CPU time 7.19 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:38 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151311574 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.4151311574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.702602817
Short name T1014
Test name
Test status
Simulation time 35381553 ps
CPU time 3.24 seconds
Started Aug 25 07:38:29 AM UTC 24
Finished Aug 25 07:38:34 AM UTC 24
Peak memory 226464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702602817 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.702602817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2566691055
Short name T1019
Test name
Test status
Simulation time 51455209 ps
CPU time 3.6 seconds
Started Aug 25 07:38:31 AM UTC 24
Finished Aug 25 07:38:36 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2566691055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_
with_rand_reset.2566691055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1518987854
Short name T1015
Test name
Test status
Simulation time 22169711 ps
CPU time 1.49 seconds
Started Aug 25 07:38:31 AM UTC 24
Finished Aug 25 07:38:34 AM UTC 24
Peak memory 212708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518987854 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1518987854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.20681673
Short name T1012
Test name
Test status
Simulation time 16300046 ps
CPU time 1.29 seconds
Started Aug 25 07:38:31 AM UTC 24
Finished Aug 25 07:38:34 AM UTC 24
Peak memory 213120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20681673 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.20681673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1415105653
Short name T1022
Test name
Test status
Simulation time 182606097 ps
CPU time 3.93 seconds
Started Aug 25 07:38:31 AM UTC 24
Finished Aug 25 07:38:37 AM UTC 24
Peak memory 215936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415105653 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.1415105653
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.297313503
Short name T1010
Test name
Test status
Simulation time 280106885 ps
CPU time 2.67 seconds
Started Aug 25 07:38:30 AM UTC 24
Finished Aug 25 07:38:34 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297313503 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.297313503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1747707918
Short name T1070
Test name
Test status
Simulation time 1419964574 ps
CPU time 16.93 seconds
Started Aug 25 07:38:30 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747707918 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.1747707918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3099064407
Short name T1020
Test name
Test status
Simulation time 123676102 ps
CPU time 4.1 seconds
Started Aug 25 07:38:31 AM UTC 24
Finished Aug 25 07:38:37 AM UTC 24
Peak memory 226236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099064407 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3099064407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1494886107
Short name T1024
Test name
Test status
Simulation time 77955071 ps
CPU time 5.1 seconds
Started Aug 25 07:38:31 AM UTC 24
Finished Aug 25 07:38:38 AM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494886107 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.1494886107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4236782981
Short name T1023
Test name
Test status
Simulation time 85040589 ps
CPU time 2.32 seconds
Started Aug 25 07:38:33 AM UTC 24
Finished Aug 25 07:38:37 AM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4236782981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_
with_rand_reset.4236782981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.3671709133
Short name T1017
Test name
Test status
Simulation time 14033811 ps
CPU time 1.25 seconds
Started Aug 25 07:38:33 AM UTC 24
Finished Aug 25 07:38:36 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671709133 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3671709133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.1301569066
Short name T1018
Test name
Test status
Simulation time 27389084 ps
CPU time 1.24 seconds
Started Aug 25 07:38:33 AM UTC 24
Finished Aug 25 07:38:36 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301569066 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1301569066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3735417475
Short name T1021
Test name
Test status
Simulation time 58087929 ps
CPU time 2.3 seconds
Started Aug 25 07:38:33 AM UTC 24
Finished Aug 25 07:38:37 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735417475 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.3735417475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2799026332
Short name T1016
Test name
Test status
Simulation time 159529716 ps
CPU time 2.48 seconds
Started Aug 25 07:38:31 AM UTC 24
Finished Aug 25 07:38:35 AM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799026332 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.2799026332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1627621114
Short name T1041
Test name
Test status
Simulation time 844910768 ps
CPU time 8.48 seconds
Started Aug 25 07:38:33 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627621114 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.1627621114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2910330280
Short name T1027
Test name
Test status
Simulation time 1040822294 ps
CPU time 4.42 seconds
Started Aug 25 07:38:33 AM UTC 24
Finished Aug 25 07:38:39 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910330280 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2910330280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.3426265880
Short name T1006
Test name
Test status
Simulation time 742305508 ps
CPU time 5 seconds
Started Aug 25 07:38:33 AM UTC 24
Finished Aug 25 07:38:39 AM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426265880 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.3426265880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1277716756
Short name T1029
Test name
Test status
Simulation time 25178220 ps
CPU time 2.2 seconds
Started Aug 25 07:38:36 AM UTC 24
Finished Aug 25 07:38:39 AM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1277716756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_
with_rand_reset.1277716756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.2781926636
Short name T1028
Test name
Test status
Simulation time 17637323 ps
CPU time 1.78 seconds
Started Aug 25 07:38:35 AM UTC 24
Finished Aug 25 07:38:39 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781926636 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2781926636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3389537048
Short name T1025
Test name
Test status
Simulation time 29675091 ps
CPU time 1.03 seconds
Started Aug 25 07:38:35 AM UTC 24
Finished Aug 25 07:38:38 AM UTC 24
Peak memory 213108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389537048 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3389537048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2065565208
Short name T1035
Test name
Test status
Simulation time 109180817 ps
CPU time 4.56 seconds
Started Aug 25 07:38:36 AM UTC 24
Finished Aug 25 07:38:42 AM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065565208 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.2065565208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2527868493
Short name T1032
Test name
Test status
Simulation time 185841996 ps
CPU time 4.2 seconds
Started Aug 25 07:38:35 AM UTC 24
Finished Aug 25 07:38:41 AM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527868493 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.2527868493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3548157694
Short name T1064
Test name
Test status
Simulation time 411632632 ps
CPU time 10.74 seconds
Started Aug 25 07:38:35 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 226604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548157694 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.3548157694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.1340620985
Short name T1031
Test name
Test status
Simulation time 137931161 ps
CPU time 3.47 seconds
Started Aug 25 07:38:35 AM UTC 24
Finished Aug 25 07:38:40 AM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340620985 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1340620985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.436572043
Short name T1055
Test name
Test status
Simulation time 139253353 ps
CPU time 8.28 seconds
Started Aug 25 07:38:35 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436572043 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.436572043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3581986641
Short name T1038
Test name
Test status
Simulation time 31716424 ps
CPU time 2.9 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:42 AM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3581986641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_
with_rand_reset.3581986641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.3456619976
Short name T997
Test name
Test status
Simulation time 41348970 ps
CPU time 1.74 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:41 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456619976 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3456619976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.4108382244
Short name T1030
Test name
Test status
Simulation time 27242344 ps
CPU time 1.08 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:40 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108382244 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4108382244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1483770439
Short name T1039
Test name
Test status
Simulation time 92504420 ps
CPU time 3.34 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:42 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483770439 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.1483770439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2268872575
Short name T1037
Test name
Test status
Simulation time 93296021 ps
CPU time 4.55 seconds
Started Aug 25 07:38:36 AM UTC 24
Finished Aug 25 07:38:42 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268872575 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.2268872575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.931817430
Short name T1046
Test name
Test status
Simulation time 77470812 ps
CPU time 6.04 seconds
Started Aug 25 07:38:36 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931817430 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.931817430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.2993366587
Short name T1007
Test name
Test status
Simulation time 47855132 ps
CPU time 2.39 seconds
Started Aug 25 07:38:36 AM UTC 24
Finished Aug 25 07:38:40 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993366587 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2993366587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3654808794
Short name T1047
Test name
Test status
Simulation time 40725114 ps
CPU time 2.29 seconds
Started Aug 25 07:38:40 AM UTC 24
Finished Aug 25 07:38:44 AM UTC 24
Peak memory 226244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3654808794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_
with_rand_reset.3654808794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.829575611
Short name T1034
Test name
Test status
Simulation time 17482859 ps
CPU time 1.53 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:41 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829575611 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.829575611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.2516419927
Short name T1033
Test name
Test status
Simulation time 91164966 ps
CPU time 1.28 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:41 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516419927 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2516419927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.973179212
Short name T1054
Test name
Test status
Simulation time 110083631 ps
CPU time 3.62 seconds
Started Aug 25 07:38:40 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 216040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973179212 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.973179212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.880600012
Short name T1040
Test name
Test status
Simulation time 87632498 ps
CPU time 3.37 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880600012 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.880600012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1941236140
Short name T1072
Test name
Test status
Simulation time 937850293 ps
CPU time 8.88 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 232748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941236140 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.1941236140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.1184003450
Short name T1036
Test name
Test status
Simulation time 31170694 ps
CPU time 2.39 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:42 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184003450 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1184003450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.743112521
Short name T1056
Test name
Test status
Simulation time 183315879 ps
CPU time 6 seconds
Started Aug 25 07:38:38 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 226164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743112521 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.743112521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.388653818
Short name T939
Test name
Test status
Simulation time 1619864420 ps
CPU time 16.88 seconds
Started Aug 25 07:37:51 AM UTC 24
Finished Aug 25 07:38:09 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388653818 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.388653818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1193323099
Short name T958
Test name
Test status
Simulation time 1135927932 ps
CPU time 23.84 seconds
Started Aug 25 07:37:51 AM UTC 24
Finished Aug 25 07:38:16 AM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193323099 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1193323099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2350772475
Short name T916
Test name
Test status
Simulation time 53001311 ps
CPU time 1.55 seconds
Started Aug 25 07:37:50 AM UTC 24
Finished Aug 25 07:37:53 AM UTC 24
Peak memory 213128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350772475 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2350772475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1147102497
Short name T917
Test name
Test status
Simulation time 34671309 ps
CPU time 2.87 seconds
Started Aug 25 07:37:52 AM UTC 24
Finished Aug 25 07:37:56 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1147102497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w
ith_rand_reset.1147102497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.1108315646
Short name T116
Test name
Test status
Simulation time 22596304 ps
CPU time 2 seconds
Started Aug 25 07:37:51 AM UTC 24
Finished Aug 25 07:37:54 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108315646 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1108315646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.1943545898
Short name T915
Test name
Test status
Simulation time 20118778 ps
CPU time 1.52 seconds
Started Aug 25 07:37:50 AM UTC 24
Finished Aug 25 07:37:53 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943545898 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1943545898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2978318014
Short name T117
Test name
Test status
Simulation time 38237978 ps
CPU time 2.74 seconds
Started Aug 25 07:37:52 AM UTC 24
Finished Aug 25 07:37:56 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978318014 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.2978318014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1341891015
Short name T85
Test name
Test status
Simulation time 206787386 ps
CPU time 4.83 seconds
Started Aug 25 07:37:50 AM UTC 24
Finished Aug 25 07:37:56 AM UTC 24
Peak memory 226684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341891015 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1341891015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2944033125
Short name T118
Test name
Test status
Simulation time 871851599 ps
CPU time 7.74 seconds
Started Aug 25 07:37:50 AM UTC 24
Finished Aug 25 07:37:59 AM UTC 24
Peak memory 226696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944033125 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.2944033125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3916361642
Short name T190
Test name
Test status
Simulation time 230130078 ps
CPU time 6.22 seconds
Started Aug 25 07:37:50 AM UTC 24
Finished Aug 25 07:37:57 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916361642 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3916361642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.3749614844
Short name T1042
Test name
Test status
Simulation time 48576151 ps
CPU time 1.1 seconds
Started Aug 25 07:38:40 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 213120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749614844 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3749614844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2689720216
Short name T1043
Test name
Test status
Simulation time 24995444 ps
CPU time 1.31 seconds
Started Aug 25 07:38:40 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 213560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689720216 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2689720216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2973191785
Short name T1045
Test name
Test status
Simulation time 30209020 ps
CPU time 1.17 seconds
Started Aug 25 07:38:40 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 213120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973191785 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2973191785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2597131744
Short name T1044
Test name
Test status
Simulation time 13050621 ps
CPU time 1.09 seconds
Started Aug 25 07:38:40 AM UTC 24
Finished Aug 25 07:38:43 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597131744 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2597131744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1372485957
Short name T1053
Test name
Test status
Simulation time 41123917 ps
CPU time 1.21 seconds
Started Aug 25 07:38:42 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372485957 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1372485957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2631649452
Short name T1051
Test name
Test status
Simulation time 9447404 ps
CPU time 1.08 seconds
Started Aug 25 07:38:42 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631649452 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2631649452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.14493507
Short name T1050
Test name
Test status
Simulation time 122910847 ps
CPU time 1.22 seconds
Started Aug 25 07:38:42 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14493507 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.14493507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3934683591
Short name T1049
Test name
Test status
Simulation time 11050855 ps
CPU time 1.03 seconds
Started Aug 25 07:38:42 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 213104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934683591 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3934683591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2193019572
Short name T1048
Test name
Test status
Simulation time 14182592 ps
CPU time 1.04 seconds
Started Aug 25 07:38:42 AM UTC 24
Finished Aug 25 07:38:44 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193019572 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2193019572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.48762381
Short name T1052
Test name
Test status
Simulation time 18108432 ps
CPU time 1.22 seconds
Started Aug 25 07:38:42 AM UTC 24
Finished Aug 25 07:38:45 AM UTC 24
Peak memory 213532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48762381 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.48762381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.962467308
Short name T947
Test name
Test status
Simulation time 472551107 ps
CPU time 14.24 seconds
Started Aug 25 07:37:56 AM UTC 24
Finished Aug 25 07:38:11 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962467308 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.962467308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.100400542
Short name T933
Test name
Test status
Simulation time 517738545 ps
CPU time 9.58 seconds
Started Aug 25 07:37:56 AM UTC 24
Finished Aug 25 07:38:07 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100400542 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.100400542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3774013231
Short name T920
Test name
Test status
Simulation time 135694283 ps
CPU time 1.71 seconds
Started Aug 25 07:37:54 AM UTC 24
Finished Aug 25 07:37:57 AM UTC 24
Peak memory 213716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774013231 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3774013231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2103615128
Short name T922
Test name
Test status
Simulation time 43210507 ps
CPU time 2.42 seconds
Started Aug 25 07:37:57 AM UTC 24
Finished Aug 25 07:38:00 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2103615128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w
ith_rand_reset.2103615128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.3743205328
Short name T119
Test name
Test status
Simulation time 316683990 ps
CPU time 2.16 seconds
Started Aug 25 07:37:56 AM UTC 24
Finished Aug 25 07:37:59 AM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743205328 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3743205328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.1741928378
Short name T918
Test name
Test status
Simulation time 21380059 ps
CPU time 1.06 seconds
Started Aug 25 07:37:54 AM UTC 24
Finished Aug 25 07:37:57 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741928378 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1741928378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3186466012
Short name T120
Test name
Test status
Simulation time 145688454 ps
CPU time 3.93 seconds
Started Aug 25 07:37:57 AM UTC 24
Finished Aug 25 07:38:02 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186466012 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.3186466012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4294958077
Short name T87
Test name
Test status
Simulation time 131834681 ps
CPU time 4.88 seconds
Started Aug 25 07:37:53 AM UTC 24
Finished Aug 25 07:37:59 AM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294958077 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.4294958077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2226782363
Short name T927
Test name
Test status
Simulation time 203984731 ps
CPU time 9.64 seconds
Started Aug 25 07:37:53 AM UTC 24
Finished Aug 25 07:38:04 AM UTC 24
Peak memory 232648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226782363 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.2226782363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.3766798054
Short name T919
Test name
Test status
Simulation time 39013726 ps
CPU time 2.24 seconds
Started Aug 25 07:37:53 AM UTC 24
Finished Aug 25 07:37:57 AM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766798054 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3766798054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.432750071
Short name T924
Test name
Test status
Simulation time 127801177 ps
CPU time 5.59 seconds
Started Aug 25 07:37:54 AM UTC 24
Finished Aug 25 07:38:01 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432750071 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.432750071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.311502874
Short name T1057
Test name
Test status
Simulation time 23098819 ps
CPU time 1.12 seconds
Started Aug 25 07:38:44 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311502874 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.311502874
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.2070159370
Short name T1059
Test name
Test status
Simulation time 62068156 ps
CPU time 1.04 seconds
Started Aug 25 07:38:44 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070159370 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2070159370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1877444048
Short name T1058
Test name
Test status
Simulation time 31271175 ps
CPU time 1.13 seconds
Started Aug 25 07:38:44 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877444048 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1877444048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.2712129854
Short name T1062
Test name
Test status
Simulation time 16615677 ps
CPU time 1.3 seconds
Started Aug 25 07:38:44 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 213120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712129854 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2712129854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.407405766
Short name T1060
Test name
Test status
Simulation time 34883163 ps
CPU time 1.05 seconds
Started Aug 25 07:38:44 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407405766 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.407405766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2411135791
Short name T1061
Test name
Test status
Simulation time 17112801 ps
CPU time 1.18 seconds
Started Aug 25 07:38:44 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411135791 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2411135791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.3975772859
Short name T1063
Test name
Test status
Simulation time 29381739 ps
CPU time 1.03 seconds
Started Aug 25 07:38:45 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975772859 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3975772859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.4177243212
Short name T1065
Test name
Test status
Simulation time 11853497 ps
CPU time 1.01 seconds
Started Aug 25 07:38:45 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 213396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177243212 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4177243212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3918983955
Short name T1068
Test name
Test status
Simulation time 29190868 ps
CPU time 1.21 seconds
Started Aug 25 07:38:45 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 213556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918983955 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3918983955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.1347737787
Short name T1071
Test name
Test status
Simulation time 22035159 ps
CPU time 1.56 seconds
Started Aug 25 07:38:45 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 213120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347737787 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1347737787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.364023818
Short name T935
Test name
Test status
Simulation time 139346103 ps
CPU time 5.83 seconds
Started Aug 25 07:38:00 AM UTC 24
Finished Aug 25 07:38:07 AM UTC 24
Peak memory 215936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364023818 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.364023818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2367890950
Short name T967
Test name
Test status
Simulation time 1039065936 ps
CPU time 17.98 seconds
Started Aug 25 07:38:00 AM UTC 24
Finished Aug 25 07:38:20 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367890950 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2367890950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2894033461
Short name T923
Test name
Test status
Simulation time 20436933 ps
CPU time 1.36 seconds
Started Aug 25 07:37:58 AM UTC 24
Finished Aug 25 07:38:01 AM UTC 24
Peak memory 213716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894033461 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2894033461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2584642070
Short name T932
Test name
Test status
Simulation time 62797168 ps
CPU time 2.76 seconds
Started Aug 25 07:38:01 AM UTC 24
Finished Aug 25 07:38:06 AM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2584642070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w
ith_rand_reset.2584642070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.1693201131
Short name T925
Test name
Test status
Simulation time 24759109 ps
CPU time 1.72 seconds
Started Aug 25 07:37:59 AM UTC 24
Finished Aug 25 07:38:02 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693201131 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1693201131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.2849943667
Short name T921
Test name
Test status
Simulation time 10421471 ps
CPU time 0.98 seconds
Started Aug 25 07:37:58 AM UTC 24
Finished Aug 25 07:38:00 AM UTC 24
Peak memory 213472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849943667 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2849943667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3252212218
Short name T929
Test name
Test status
Simulation time 95963887 ps
CPU time 2.3 seconds
Started Aug 25 07:38:01 AM UTC 24
Finished Aug 25 07:38:05 AM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252212218 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.3252212218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2527809857
Short name T926
Test name
Test status
Simulation time 452096034 ps
CPU time 5.72 seconds
Started Aug 25 07:37:57 AM UTC 24
Finished Aug 25 07:38:04 AM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527809857 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.2527809857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.115575984
Short name T959
Test name
Test status
Simulation time 1792186882 ps
CPU time 17.53 seconds
Started Aug 25 07:37:58 AM UTC 24
Finished Aug 25 07:38:17 AM UTC 24
Peak memory 226740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115575984 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.115575984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.2144522029
Short name T928
Test name
Test status
Simulation time 113834642 ps
CPU time 5.04 seconds
Started Aug 25 07:37:58 AM UTC 24
Finished Aug 25 07:38:04 AM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144522029 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2144522029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.2120771067
Short name T1067
Test name
Test status
Simulation time 8914338 ps
CPU time 1.08 seconds
Started Aug 25 07:38:45 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120771067 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2120771067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.3658686461
Short name T1066
Test name
Test status
Simulation time 14926166 ps
CPU time 0.99 seconds
Started Aug 25 07:38:45 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658686461 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3658686461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1049432031
Short name T1069
Test name
Test status
Simulation time 12770959 ps
CPU time 1.09 seconds
Started Aug 25 07:38:45 AM UTC 24
Finished Aug 25 07:38:48 AM UTC 24
Peak memory 213188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049432031 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1049432031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3961186432
Short name T1077
Test name
Test status
Simulation time 10346301 ps
CPU time 1.23 seconds
Started Aug 25 07:38:47 AM UTC 24
Finished Aug 25 07:38:50 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961186432 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3961186432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3467218629
Short name T1074
Test name
Test status
Simulation time 14808038 ps
CPU time 1.24 seconds
Started Aug 25 07:38:47 AM UTC 24
Finished Aug 25 07:38:50 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467218629 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3467218629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.3929380675
Short name T1075
Test name
Test status
Simulation time 13787498 ps
CPU time 1.21 seconds
Started Aug 25 07:38:47 AM UTC 24
Finished Aug 25 07:38:50 AM UTC 24
Peak memory 213520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929380675 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3929380675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1328063860
Short name T1073
Test name
Test status
Simulation time 26694022 ps
CPU time 1.08 seconds
Started Aug 25 07:38:47 AM UTC 24
Finished Aug 25 07:38:50 AM UTC 24
Peak memory 213552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328063860 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1328063860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.109752458
Short name T1076
Test name
Test status
Simulation time 34624367 ps
CPU time 1.17 seconds
Started Aug 25 07:38:47 AM UTC 24
Finished Aug 25 07:38:50 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109752458 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.109752458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.2569325131
Short name T1078
Test name
Test status
Simulation time 21212089 ps
CPU time 1.13 seconds
Started Aug 25 07:38:47 AM UTC 24
Finished Aug 25 07:38:50 AM UTC 24
Peak memory 213188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569325131 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2569325131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.860505999
Short name T1079
Test name
Test status
Simulation time 17484017 ps
CPU time 1.1 seconds
Started Aug 25 07:38:47 AM UTC 24
Finished Aug 25 07:38:50 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860505999 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.860505999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2167461857
Short name T940
Test name
Test status
Simulation time 167179738 ps
CPU time 2.97 seconds
Started Aug 25 07:38:05 AM UTC 24
Finished Aug 25 07:38:09 AM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2167461857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w
ith_rand_reset.2167461857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1077394004
Short name T936
Test name
Test status
Simulation time 269737158 ps
CPU time 1.72 seconds
Started Aug 25 07:38:05 AM UTC 24
Finished Aug 25 07:38:08 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077394004 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1077394004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.710959577
Short name T934
Test name
Test status
Simulation time 71358856 ps
CPU time 1.4 seconds
Started Aug 25 07:38:04 AM UTC 24
Finished Aug 25 07:38:07 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710959577 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.710959577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1588684221
Short name T943
Test name
Test status
Simulation time 303185416 ps
CPU time 4.13 seconds
Started Aug 25 07:38:05 AM UTC 24
Finished Aug 25 07:38:10 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588684221 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.1588684221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2200659100
Short name T930
Test name
Test status
Simulation time 161750420 ps
CPU time 2.29 seconds
Started Aug 25 07:38:02 AM UTC 24
Finished Aug 25 07:38:05 AM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200659100 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.2200659100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1447501625
Short name T976
Test name
Test status
Simulation time 1528059432 ps
CPU time 19.43 seconds
Started Aug 25 07:38:03 AM UTC 24
Finished Aug 25 07:38:24 AM UTC 24
Peak memory 226528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447501625 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.1447501625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.1539168473
Short name T944
Test name
Test status
Simulation time 227686363 ps
CPU time 6.6 seconds
Started Aug 25 07:38:03 AM UTC 24
Finished Aug 25 07:38:11 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539168473 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1539168473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.3686760362
Short name T180
Test name
Test status
Simulation time 559067934 ps
CPU time 10.55 seconds
Started Aug 25 07:38:03 AM UTC 24
Finished Aug 25 07:38:15 AM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686760362 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.3686760362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1355940532
Short name T946
Test name
Test status
Simulation time 37140803 ps
CPU time 2.22 seconds
Started Aug 25 07:38:08 AM UTC 24
Finished Aug 25 07:38:11 AM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1355940532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w
ith_rand_reset.1355940532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.1494772647
Short name T941
Test name
Test status
Simulation time 16758440 ps
CPU time 1.43 seconds
Started Aug 25 07:38:08 AM UTC 24
Finished Aug 25 07:38:10 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494772647 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1494772647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.603138336
Short name T938
Test name
Test status
Simulation time 27785095 ps
CPU time 1.14 seconds
Started Aug 25 07:38:06 AM UTC 24
Finished Aug 25 07:38:09 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603138336 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.603138336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.713789238
Short name T948
Test name
Test status
Simulation time 74534471 ps
CPU time 3.35 seconds
Started Aug 25 07:38:08 AM UTC 24
Finished Aug 25 07:38:12 AM UTC 24
Peak memory 216008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713789238 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.713789238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3134648038
Short name T945
Test name
Test status
Simulation time 59818364 ps
CPU time 3.43 seconds
Started Aug 25 07:38:06 AM UTC 24
Finished Aug 25 07:38:11 AM UTC 24
Peak memory 226684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134648038 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.3134648038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2356229170
Short name T996
Test name
Test status
Simulation time 7029661638 ps
CPU time 22.69 seconds
Started Aug 25 07:38:06 AM UTC 24
Finished Aug 25 07:38:31 AM UTC 24
Peak memory 226624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356229170 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.2356229170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.1109860082
Short name T950
Test name
Test status
Simulation time 127553213 ps
CPU time 5.15 seconds
Started Aug 25 07:38:06 AM UTC 24
Finished Aug 25 07:38:13 AM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109860082 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1109860082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.2148663911
Short name T176
Test name
Test status
Simulation time 479023970 ps
CPU time 9.28 seconds
Started Aug 25 07:38:06 AM UTC 24
Finished Aug 25 07:38:17 AM UTC 24
Peak memory 225964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148663911 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.2148663911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.971545791
Short name T953
Test name
Test status
Simulation time 55676957 ps
CPU time 1.7 seconds
Started Aug 25 07:38:11 AM UTC 24
Finished Aug 25 07:38:15 AM UTC 24
Peak memory 216200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=971545791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_wi
th_rand_reset.971545791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.3805451053
Short name T952
Test name
Test status
Simulation time 49815659 ps
CPU time 1.8 seconds
Started Aug 25 07:38:10 AM UTC 24
Finished Aug 25 07:38:13 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805451053 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3805451053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.3657391942
Short name T949
Test name
Test status
Simulation time 7188062 ps
CPU time 1.22 seconds
Started Aug 25 07:38:10 AM UTC 24
Finished Aug 25 07:38:13 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657391942 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3657391942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.583651535
Short name T957
Test name
Test status
Simulation time 89869958 ps
CPU time 4.54 seconds
Started Aug 25 07:38:10 AM UTC 24
Finished Aug 25 07:38:16 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583651535 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.583651535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1710164053
Short name T951
Test name
Test status
Simulation time 347397221 ps
CPU time 4.18 seconds
Started Aug 25 07:38:08 AM UTC 24
Finished Aug 25 07:38:13 AM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710164053 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.1710164053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.797682768
Short name T1004
Test name
Test status
Simulation time 886731904 ps
CPU time 22.31 seconds
Started Aug 25 07:38:09 AM UTC 24
Finished Aug 25 07:38:33 AM UTC 24
Peak memory 226676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797682768 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.797682768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.2221188229
Short name T956
Test name
Test status
Simulation time 493466256 ps
CPU time 5.56 seconds
Started Aug 25 07:38:09 AM UTC 24
Finished Aug 25 07:38:16 AM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221188229 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2221188229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1075115890
Short name T962
Test name
Test status
Simulation time 30694868 ps
CPU time 2.86 seconds
Started Aug 25 07:38:14 AM UTC 24
Finished Aug 25 07:38:18 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1075115890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w
ith_rand_reset.1075115890
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.3426679568
Short name T955
Test name
Test status
Simulation time 50882878 ps
CPU time 1.62 seconds
Started Aug 25 07:38:12 AM UTC 24
Finished Aug 25 07:38:16 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426679568 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3426679568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.2823441255
Short name T954
Test name
Test status
Simulation time 15365642 ps
CPU time 1.1 seconds
Started Aug 25 07:38:12 AM UTC 24
Finished Aug 25 07:38:15 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823441255 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2823441255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1686428631
Short name T960
Test name
Test status
Simulation time 46283666 ps
CPU time 2.62 seconds
Started Aug 25 07:38:14 AM UTC 24
Finished Aug 25 07:38:17 AM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686428631 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.1686428631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.411530252
Short name T961
Test name
Test status
Simulation time 630233986 ps
CPU time 4.53 seconds
Started Aug 25 07:38:11 AM UTC 24
Finished Aug 25 07:38:17 AM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411530252 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.411530252
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2232011793
Short name T986
Test name
Test status
Simulation time 1619787263 ps
CPU time 13.62 seconds
Started Aug 25 07:38:11 AM UTC 24
Finished Aug 25 07:38:27 AM UTC 24
Peak memory 226788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232011793 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.2232011793
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.1418996652
Short name T965
Test name
Test status
Simulation time 340619838 ps
CPU time 5.45 seconds
Started Aug 25 07:38:11 AM UTC 24
Finished Aug 25 07:38:18 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418996652 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1418996652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.3599175178
Short name T164
Test name
Test status
Simulation time 441518814 ps
CPU time 13.71 seconds
Started Aug 25 07:38:12 AM UTC 24
Finished Aug 25 07:38:28 AM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599175178 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.3599175178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4002774088
Short name T968
Test name
Test status
Simulation time 79614195 ps
CPU time 2.14 seconds
Started Aug 25 07:38:17 AM UTC 24
Finished Aug 25 07:38:21 AM UTC 24
Peak memory 225904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4002774088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w
ith_rand_reset.4002774088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.585599682
Short name T966
Test name
Test status
Simulation time 107854307 ps
CPU time 2.2 seconds
Started Aug 25 07:38:16 AM UTC 24
Finished Aug 25 07:38:19 AM UTC 24
Peak memory 216064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585599682 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.585599682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.1605238400
Short name T964
Test name
Test status
Simulation time 14990845 ps
CPU time 1.21 seconds
Started Aug 25 07:38:16 AM UTC 24
Finished Aug 25 07:38:18 AM UTC 24
Peak memory 213472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605238400 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1605238400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.152706704
Short name T969
Test name
Test status
Simulation time 62360591 ps
CPU time 2.44 seconds
Started Aug 25 07:38:17 AM UTC 24
Finished Aug 25 07:38:21 AM UTC 24
Peak memory 215588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152706704 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.152706704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.663253714
Short name T81
Test name
Test status
Simulation time 400327173 ps
CPU time 3.31 seconds
Started Aug 25 07:38:14 AM UTC 24
Finished Aug 25 07:38:18 AM UTC 24
Peak memory 226332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663253714 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.663253714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.129762053
Short name T980
Test name
Test status
Simulation time 210086029 ps
CPU time 10.66 seconds
Started Aug 25 07:38:14 AM UTC 24
Finished Aug 25 07:38:26 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129762053 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.129762053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.1546363975
Short name T963
Test name
Test status
Simulation time 68153004 ps
CPU time 2.21 seconds
Started Aug 25 07:38:15 AM UTC 24
Finished Aug 25 07:38:18 AM UTC 24
Peak memory 226104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546363975 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1546363975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.515343436
Short name T173
Test name
Test status
Simulation time 141593366 ps
CPU time 7.1 seconds
Started Aug 25 07:38:16 AM UTC 24
Finished Aug 25 07:38:24 AM UTC 24
Peak memory 226400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515343436 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.515343436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.3778198807
Short name T15
Test name
Test status
Simulation time 393247296 ps
CPU time 6.52 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:09 AM UTC 24
Peak memory 218256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778198807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3778198807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_random.1183205287
Short name T18
Test name
Test status
Simulation time 199598924 ps
CPU time 10.03 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:12 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183205287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1183205287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.3271992673
Short name T1
Test name
Test status
Simulation time 114375157 ps
CPU time 4 seconds
Started Aug 25 07:28:58 AM UTC 24
Finished Aug 25 07:29:04 AM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271992673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3271992673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.2173055892
Short name T4
Test name
Test status
Simulation time 373703608 ps
CPU time 6.55 seconds
Started Aug 25 07:28:58 AM UTC 24
Finished Aug 25 07:29:06 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173055892 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2173055892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.2091343349
Short name T43
Test name
Test status
Simulation time 1415344372 ps
CPU time 14.76 seconds
Started Aug 25 07:28:58 AM UTC 24
Finished Aug 25 07:29:15 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091343349 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2091343349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.259836087
Short name T3
Test name
Test status
Simulation time 99239663 ps
CPU time 4.25 seconds
Started Aug 25 07:29:01 AM UTC 24
Finished Aug 25 07:29:06 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259836087 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.259836087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.3730701967
Short name T2
Test name
Test status
Simulation time 184815819 ps
CPU time 4.47 seconds
Started Aug 25 07:28:58 AM UTC 24
Finished Aug 25 07:29:04 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730701967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3730701967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.2768158688
Short name T35
Test name
Test status
Simulation time 910190021 ps
CPU time 8.42 seconds
Started Aug 25 07:29:07 AM UTC 24
Finished Aug 25 07:29:16 AM UTC 24
Peak memory 220264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768158688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2768158688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.897458859
Short name T63
Test name
Test status
Simulation time 60467344 ps
CPU time 1.26 seconds
Started Aug 25 07:29:23 AM UTC 24
Finished Aug 25 07:29:25 AM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897458859 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.897458859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.3760695956
Short name T30
Test name
Test status
Simulation time 98398552 ps
CPU time 5.27 seconds
Started Aug 25 07:29:17 AM UTC 24
Finished Aug 25 07:29:24 AM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760695956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3760695956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.2333674607
Short name T138
Test name
Test status
Simulation time 692199859 ps
CPU time 5.81 seconds
Started Aug 25 07:29:14 AM UTC 24
Finished Aug 25 07:29:21 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333674607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2333674607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.706544277
Short name T44
Test name
Test status
Simulation time 529448740 ps
CPU time 8.14 seconds
Started Aug 25 07:29:17 AM UTC 24
Finished Aug 25 07:29:27 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706544277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.706544277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.1875373544
Short name T69
Test name
Test status
Simulation time 348400515 ps
CPU time 6.29 seconds
Started Aug 25 07:29:14 AM UTC 24
Finished Aug 25 07:29:22 AM UTC 24
Peak memory 230280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875373544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1875373544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_random.1089022885
Short name T158
Test name
Test status
Simulation time 56835952 ps
CPU time 4.78 seconds
Started Aug 25 07:29:13 AM UTC 24
Finished Aug 25 07:29:19 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089022885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1089022885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.3521426467
Short name T104
Test name
Test status
Simulation time 629249559 ps
CPU time 30.06 seconds
Started Aug 25 07:29:11 AM UTC 24
Finished Aug 25 07:29:42 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521426467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3521426467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.1068247986
Short name T67
Test name
Test status
Simulation time 25337879 ps
CPU time 3.16 seconds
Started Aug 25 07:29:12 AM UTC 24
Finished Aug 25 07:29:16 AM UTC 24
Peak memory 217548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068247986 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1068247986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.260380217
Short name T159
Test name
Test status
Simulation time 208353351 ps
CPU time 6.57 seconds
Started Aug 25 07:29:12 AM UTC 24
Finished Aug 25 07:29:20 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260380217 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.260380217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3228589781
Short name T203
Test name
Test status
Simulation time 2894103950 ps
CPU time 30.79 seconds
Started Aug 25 07:29:10 AM UTC 24
Finished Aug 25 07:29:43 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228589781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3228589781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.2357071270
Short name T66
Test name
Test status
Simulation time 542343219 ps
CPU time 14.48 seconds
Started Aug 25 07:29:22 AM UTC 24
Finished Aug 25 07:29:38 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2357071270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr
_stress_all_with_rand_reset.2357071270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.124406344
Short name T297
Test name
Test status
Simulation time 8641324213 ps
CPU time 112.76 seconds
Started Aug 25 07:29:15 AM UTC 24
Finished Aug 25 07:31:11 AM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124406344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.124406344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.4027491947
Short name T36
Test name
Test status
Simulation time 561059071 ps
CPU time 20.07 seconds
Started Aug 25 07:29:20 AM UTC 24
Finished Aug 25 07:29:42 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027491947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4027491947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.3345861326
Short name T466
Test name
Test status
Simulation time 111752421 ps
CPU time 1.24 seconds
Started Aug 25 07:31:26 AM UTC 24
Finished Aug 25 07:31:29 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345861326 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3345861326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.2400291262
Short name T32
Test name
Test status
Simulation time 227581456 ps
CPU time 4.69 seconds
Started Aug 25 07:31:24 AM UTC 24
Finished Aug 25 07:31:30 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400291262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2400291262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.3184132688
Short name T464
Test name
Test status
Simulation time 28031116 ps
CPU time 2.42 seconds
Started Aug 25 07:31:20 AM UTC 24
Finished Aug 25 07:31:24 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184132688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3184132688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.814657620
Short name T441
Test name
Test status
Simulation time 331014134 ps
CPU time 6.26 seconds
Started Aug 25 07:31:21 AM UTC 24
Finished Aug 25 07:31:28 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814657620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.814657620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.449180428
Short name T313
Test name
Test status
Simulation time 25299590 ps
CPU time 3.08 seconds
Started Aug 25 07:31:16 AM UTC 24
Finished Aug 25 07:31:21 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449180428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.449180428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.1733905073
Short name T249
Test name
Test status
Simulation time 79271949 ps
CPU time 5.56 seconds
Started Aug 25 07:31:17 AM UTC 24
Finished Aug 25 07:31:24 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733905073 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1733905073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.758839017
Short name T468
Test name
Test status
Simulation time 400780998 ps
CPU time 10.61 seconds
Started Aug 25 07:31:17 AM UTC 24
Finished Aug 25 07:31:29 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758839017 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.758839017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.1066167168
Short name T465
Test name
Test status
Simulation time 48977070 ps
CPU time 1.95 seconds
Started Aug 25 07:31:25 AM UTC 24
Finished Aug 25 07:31:28 AM UTC 24
Peak memory 215620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066167168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1066167168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.375551307
Short name T462
Test name
Test status
Simulation time 57701716 ps
CPU time 3.2 seconds
Started Aug 25 07:31:16 AM UTC 24
Finished Aug 25 07:31:21 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375551307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.375551307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.3704523629
Short name T342
Test name
Test status
Simulation time 696029733 ps
CPU time 8.93 seconds
Started Aug 25 07:31:21 AM UTC 24
Finished Aug 25 07:31:31 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704523629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3704523629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.2583469936
Short name T467
Test name
Test status
Simulation time 272326566 ps
CPU time 2.7 seconds
Started Aug 25 07:31:25 AM UTC 24
Finished Aug 25 07:31:29 AM UTC 24
Peak memory 220084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583469936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2583469936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.346344258
Short name T471
Test name
Test status
Simulation time 9559000 ps
CPU time 1.14 seconds
Started Aug 25 07:31:38 AM UTC 24
Finished Aug 25 07:31:40 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346344258 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.346344258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.3836811544
Short name T245
Test name
Test status
Simulation time 50684473 ps
CPU time 4.58 seconds
Started Aug 25 07:31:30 AM UTC 24
Finished Aug 25 07:31:36 AM UTC 24
Peak memory 226516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836811544 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3836811544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.736989587
Short name T59
Test name
Test status
Simulation time 52133188 ps
CPU time 4.36 seconds
Started Aug 25 07:31:32 AM UTC 24
Finished Aug 25 07:31:38 AM UTC 24
Peak memory 230496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736989587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.736989587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.3436682944
Short name T322
Test name
Test status
Simulation time 182080863 ps
CPU time 2.66 seconds
Started Aug 25 07:31:33 AM UTC 24
Finished Aug 25 07:31:37 AM UTC 24
Peak memory 219872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436682944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3436682944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.1288053511
Short name T371
Test name
Test status
Simulation time 88639741 ps
CPU time 3.49 seconds
Started Aug 25 07:31:31 AM UTC 24
Finished Aug 25 07:31:36 AM UTC 24
Peak memory 216008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288053511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1288053511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_random.3181605259
Short name T473
Test name
Test status
Simulation time 2608741522 ps
CPU time 12.85 seconds
Started Aug 25 07:31:30 AM UTC 24
Finished Aug 25 07:31:44 AM UTC 24
Peak memory 226536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181605259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3181605259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.57579314
Short name T293
Test name
Test status
Simulation time 865876538 ps
CPU time 30.5 seconds
Started Aug 25 07:31:29 AM UTC 24
Finished Aug 25 07:32:01 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57579314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.57579314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.1403097397
Short name T502
Test name
Test status
Simulation time 3518097275 ps
CPU time 64.03 seconds
Started Aug 25 07:31:29 AM UTC 24
Finished Aug 25 07:32:35 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403097397 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1403097397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.2056026316
Short name T479
Test name
Test status
Simulation time 894906903 ps
CPU time 32.46 seconds
Started Aug 25 07:31:29 AM UTC 24
Finished Aug 25 07:32:03 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056026316 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2056026316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.2914805554
Short name T421
Test name
Test status
Simulation time 1607202288 ps
CPU time 12.51 seconds
Started Aug 25 07:31:30 AM UTC 24
Finished Aug 25 07:31:44 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914805554 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2914805554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.288169423
Short name T472
Test name
Test status
Simulation time 366230533 ps
CPU time 4.09 seconds
Started Aug 25 07:31:37 AM UTC 24
Finished Aug 25 07:31:42 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288169423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.288169423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.3679008089
Short name T470
Test name
Test status
Simulation time 180926024 ps
CPU time 6.33 seconds
Started Aug 25 07:31:27 AM UTC 24
Finished Aug 25 07:31:35 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679008089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3679008089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.2355570760
Short name T442
Test name
Test status
Simulation time 71189685 ps
CPU time 4.03 seconds
Started Aug 25 07:31:31 AM UTC 24
Finished Aug 25 07:31:36 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355570760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2355570760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.1784725537
Short name T100
Test name
Test status
Simulation time 684327981 ps
CPU time 8.46 seconds
Started Aug 25 07:31:37 AM UTC 24
Finished Aug 25 07:31:47 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784725537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1784725537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.1199410403
Short name T476
Test name
Test status
Simulation time 21613673 ps
CPU time 1.41 seconds
Started Aug 25 07:31:54 AM UTC 24
Finished Aug 25 07:31:57 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199410403 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1199410403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.745370676
Short name T23
Test name
Test status
Simulation time 120367289 ps
CPU time 3.23 seconds
Started Aug 25 07:31:50 AM UTC 24
Finished Aug 25 07:31:54 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745370676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.745370676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.883273882
Short name T397
Test name
Test status
Simulation time 126072681 ps
CPU time 5.82 seconds
Started Aug 25 07:31:47 AM UTC 24
Finished Aug 25 07:31:54 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883273882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.883273882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.415481380
Short name T294
Test name
Test status
Simulation time 305290873 ps
CPU time 4.58 seconds
Started Aug 25 07:31:48 AM UTC 24
Finished Aug 25 07:31:53 AM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415481380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.415481380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_random.1056803925
Short name T491
Test name
Test status
Simulation time 886535193 ps
CPU time 34.42 seconds
Started Aug 25 07:31:44 AM UTC 24
Finished Aug 25 07:32:21 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056803925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1056803925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.2553147680
Short name T400
Test name
Test status
Simulation time 48033857 ps
CPU time 3.55 seconds
Started Aug 25 07:31:41 AM UTC 24
Finished Aug 25 07:31:46 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553147680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2553147680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.2006689937
Short name T474
Test name
Test status
Simulation time 79724789 ps
CPU time 3.84 seconds
Started Aug 25 07:31:43 AM UTC 24
Finished Aug 25 07:31:49 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006689937 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2006689937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.1940162080
Short name T391
Test name
Test status
Simulation time 194226991 ps
CPU time 3.98 seconds
Started Aug 25 07:31:41 AM UTC 24
Finished Aug 25 07:31:47 AM UTC 24
Peak memory 218292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940162080 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1940162080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.305962683
Short name T475
Test name
Test status
Simulation time 73920523 ps
CPU time 3.76 seconds
Started Aug 25 07:31:44 AM UTC 24
Finished Aug 25 07:31:49 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305962683 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.305962683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.596335921
Short name T347
Test name
Test status
Simulation time 81256815 ps
CPU time 4.11 seconds
Started Aug 25 07:31:50 AM UTC 24
Finished Aug 25 07:31:55 AM UTC 24
Peak memory 220428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596335921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.596335921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.2712922813
Short name T416
Test name
Test status
Simulation time 186456725 ps
CPU time 3.22 seconds
Started Aug 25 07:31:39 AM UTC 24
Finished Aug 25 07:31:43 AM UTC 24
Peak memory 217820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712922813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2712922813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.393780408
Short name T398
Test name
Test status
Simulation time 17965843583 ps
CPU time 214.43 seconds
Started Aug 25 07:31:53 AM UTC 24
Finished Aug 25 07:35:32 AM UTC 24
Peak memory 228192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393780408 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.393780408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.3147437308
Short name T320
Test name
Test status
Simulation time 52318129 ps
CPU time 2.97 seconds
Started Aug 25 07:31:48 AM UTC 24
Finished Aug 25 07:31:52 AM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147437308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3147437308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.542525863
Short name T482
Test name
Test status
Simulation time 562079916 ps
CPU time 14.23 seconds
Started Aug 25 07:31:51 AM UTC 24
Finished Aug 25 07:32:07 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542525863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.542525863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.4054249507
Short name T485
Test name
Test status
Simulation time 60504105 ps
CPU time 1.41 seconds
Started Aug 25 07:32:09 AM UTC 24
Finished Aug 25 07:32:12 AM UTC 24
Peak memory 213724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054249507 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4054249507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.1898669049
Short name T481
Test name
Test status
Simulation time 80996685 ps
CPU time 3.83 seconds
Started Aug 25 07:32:01 AM UTC 24
Finished Aug 25 07:32:06 AM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898669049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1898669049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.2588063232
Short name T54
Test name
Test status
Simulation time 145019247 ps
CPU time 7.99 seconds
Started Aug 25 07:32:06 AM UTC 24
Finished Aug 25 07:32:15 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588063232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2588063232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.519952575
Short name T237
Test name
Test status
Simulation time 119740914 ps
CPU time 7.35 seconds
Started Aug 25 07:32:02 AM UTC 24
Finished Aug 25 07:32:11 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519952575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.519952575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_random.333563042
Short name T295
Test name
Test status
Simulation time 218898784 ps
CPU time 9.67 seconds
Started Aug 25 07:31:58 AM UTC 24
Finished Aug 25 07:32:09 AM UTC 24
Peak memory 228164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333563042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.333563042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.2746021448
Short name T512
Test name
Test status
Simulation time 6393708146 ps
CPU time 58.3 seconds
Started Aug 25 07:31:55 AM UTC 24
Finished Aug 25 07:32:56 AM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746021448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2746021448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.1527080401
Short name T478
Test name
Test status
Simulation time 78451089 ps
CPU time 2.93 seconds
Started Aug 25 07:31:57 AM UTC 24
Finished Aug 25 07:32:01 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527080401 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1527080401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.2866164171
Short name T480
Test name
Test status
Simulation time 88666311 ps
CPU time 5.32 seconds
Started Aug 25 07:31:56 AM UTC 24
Finished Aug 25 07:32:03 AM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866164171 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2866164171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.2349401946
Short name T324
Test name
Test status
Simulation time 79428131 ps
CPU time 5.74 seconds
Started Aug 25 07:31:57 AM UTC 24
Finished Aug 25 07:32:03 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349401946 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2349401946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.2294603521
Short name T484
Test name
Test status
Simulation time 291764506 ps
CPU time 3.85 seconds
Started Aug 25 07:32:06 AM UTC 24
Finished Aug 25 07:32:11 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294603521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2294603521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1529239152
Short name T477
Test name
Test status
Simulation time 82782168 ps
CPU time 2.95 seconds
Started Aug 25 07:31:55 AM UTC 24
Finished Aug 25 07:32:00 AM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529239152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1529239152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.3621933883
Short name T356
Test name
Test status
Simulation time 721529566 ps
CPU time 12.92 seconds
Started Aug 25 07:32:06 AM UTC 24
Finished Aug 25 07:32:20 AM UTC 24
Peak memory 228388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621933883 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3621933883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.2979943350
Short name T94
Test name
Test status
Simulation time 416213222 ps
CPU time 21.1 seconds
Started Aug 25 07:32:09 AM UTC 24
Finished Aug 25 07:32:32 AM UTC 24
Peak memory 232304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2979943350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymg
r_stress_all_with_rand_reset.2979943350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.2309147457
Short name T486
Test name
Test status
Simulation time 272122840 ps
CPU time 9.77 seconds
Started Aug 25 07:32:02 AM UTC 24
Finished Aug 25 07:32:13 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309147457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2309147457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.1345462771
Short name T483
Test name
Test status
Simulation time 902484671 ps
CPU time 3.83 seconds
Started Aug 25 07:32:06 AM UTC 24
Finished Aug 25 07:32:11 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345462771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1345462771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.3230842771
Short name T493
Test name
Test status
Simulation time 139048701 ps
CPU time 1.45 seconds
Started Aug 25 07:32:19 AM UTC 24
Finished Aug 25 07:32:22 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230842771 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3230842771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.2035655805
Short name T296
Test name
Test status
Simulation time 171486094 ps
CPU time 5.17 seconds
Started Aug 25 07:32:12 AM UTC 24
Finished Aug 25 07:32:19 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035655805 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2035655805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.2034603195
Short name T469
Test name
Test status
Simulation time 33400200 ps
CPU time 2.54 seconds
Started Aug 25 07:32:13 AM UTC 24
Finished Aug 25 07:32:16 AM UTC 24
Peak memory 216116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034603195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2034603195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.1006503749
Short name T254
Test name
Test status
Simulation time 30651590 ps
CPU time 2.54 seconds
Started Aug 25 07:32:16 AM UTC 24
Finished Aug 25 07:32:20 AM UTC 24
Peak memory 224396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006503749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1006503749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.1123448062
Short name T143
Test name
Test status
Simulation time 47218684 ps
CPU time 4.64 seconds
Started Aug 25 07:32:14 AM UTC 24
Finished Aug 25 07:32:19 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123448062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1123448062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_random.4168182432
Short name T506
Test name
Test status
Simulation time 768221238 ps
CPU time 31.02 seconds
Started Aug 25 07:32:12 AM UTC 24
Finished Aug 25 07:32:45 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168182432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4168182432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.2457346710
Short name T489
Test name
Test status
Simulation time 77913509 ps
CPU time 4.77 seconds
Started Aug 25 07:32:11 AM UTC 24
Finished Aug 25 07:32:17 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457346710 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2457346710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.3309659054
Short name T488
Test name
Test status
Simulation time 56217381 ps
CPU time 4.25 seconds
Started Aug 25 07:32:11 AM UTC 24
Finished Aug 25 07:32:17 AM UTC 24
Peak memory 217932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309659054 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3309659054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.3366036748
Short name T487
Test name
Test status
Simulation time 21890452 ps
CPU time 2.26 seconds
Started Aug 25 07:32:11 AM UTC 24
Finished Aug 25 07:32:15 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366036748 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3366036748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.1930096291
Short name T315
Test name
Test status
Simulation time 84370170 ps
CPU time 5.19 seconds
Started Aug 25 07:32:17 AM UTC 24
Finished Aug 25 07:32:24 AM UTC 24
Peak memory 226164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930096291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1930096291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.3189049253
Short name T490
Test name
Test status
Simulation time 672609660 ps
CPU time 9.24 seconds
Started Aug 25 07:32:09 AM UTC 24
Finished Aug 25 07:32:20 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189049253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3189049253
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.169363082
Short name T495
Test name
Test status
Simulation time 758957461 ps
CPU time 13.35 seconds
Started Aug 25 07:32:15 AM UTC 24
Finished Aug 25 07:32:29 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169363082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.169363082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.4033534597
Short name T492
Test name
Test status
Simulation time 45295429 ps
CPU time 2.5 seconds
Started Aug 25 07:32:17 AM UTC 24
Finished Aug 25 07:32:21 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033534597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4033534597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2952538782
Short name T501
Test name
Test status
Simulation time 42466644 ps
CPU time 1.21 seconds
Started Aug 25 07:32:32 AM UTC 24
Finished Aug 25 07:32:34 AM UTC 24
Peak memory 213568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952538782 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2952538782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.465239758
Short name T33
Test name
Test status
Simulation time 63019094 ps
CPU time 4.54 seconds
Started Aug 25 07:32:29 AM UTC 24
Finished Aug 25 07:32:35 AM UTC 24
Peak memory 218672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465239758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.465239758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.2905754500
Short name T384
Test name
Test status
Simulation time 204676008 ps
CPU time 6.53 seconds
Started Aug 25 07:32:23 AM UTC 24
Finished Aug 25 07:32:31 AM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905754500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2905754500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.249333619
Short name T271
Test name
Test status
Simulation time 63781622 ps
CPU time 4.58 seconds
Started Aug 25 07:32:26 AM UTC 24
Finished Aug 25 07:32:32 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249333619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.249333619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.1864375659
Short name T343
Test name
Test status
Simulation time 188346832 ps
CPU time 6.74 seconds
Started Aug 25 07:32:27 AM UTC 24
Finished Aug 25 07:32:35 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864375659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1864375659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.4039078332
Short name T381
Test name
Test status
Simulation time 98999551 ps
CPU time 4.86 seconds
Started Aug 25 07:32:24 AM UTC 24
Finished Aug 25 07:32:30 AM UTC 24
Peak memory 218028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039078332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4039078332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_random.2858702802
Short name T419
Test name
Test status
Simulation time 510455979 ps
CPU time 7.34 seconds
Started Aug 25 07:32:22 AM UTC 24
Finished Aug 25 07:32:30 AM UTC 24
Peak memory 232264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858702802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2858702802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.1965153604
Short name T499
Test name
Test status
Simulation time 227379831 ps
CPU time 9.88 seconds
Started Aug 25 07:32:21 AM UTC 24
Finished Aug 25 07:32:32 AM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965153604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1965153604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.3107121158
Short name T496
Test name
Test status
Simulation time 822328892 ps
CPU time 8.36 seconds
Started Aug 25 07:32:21 AM UTC 24
Finished Aug 25 07:32:30 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107121158 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3107121158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.3354568202
Short name T412
Test name
Test status
Simulation time 69728707 ps
CPU time 3.69 seconds
Started Aug 25 07:32:21 AM UTC 24
Finished Aug 25 07:32:26 AM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354568202 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3354568202
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.2040612163
Short name T498
Test name
Test status
Simulation time 134908477 ps
CPU time 7.85 seconds
Started Aug 25 07:32:22 AM UTC 24
Finished Aug 25 07:32:31 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040612163 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2040612163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.726550654
Short name T281
Test name
Test status
Simulation time 1624491315 ps
CPU time 26.09 seconds
Started Aug 25 07:32:31 AM UTC 24
Finished Aug 25 07:32:58 AM UTC 24
Peak memory 230664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726550654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.726550654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.2955105503
Short name T494
Test name
Test status
Simulation time 184867642 ps
CPU time 7.64 seconds
Started Aug 25 07:32:19 AM UTC 24
Finished Aug 25 07:32:28 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955105503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2955105503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.2878778455
Short name T509
Test name
Test status
Simulation time 570688092 ps
CPU time 13.73 seconds
Started Aug 25 07:32:32 AM UTC 24
Finished Aug 25 07:32:47 AM UTC 24
Peak memory 228196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878778455 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2878778455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.339810104
Short name T497
Test name
Test status
Simulation time 170850475 ps
CPU time 4.64 seconds
Started Aug 25 07:32:25 AM UTC 24
Finished Aug 25 07:32:31 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339810104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.339810104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.562136939
Short name T500
Test name
Test status
Simulation time 59559991 ps
CPU time 2.23 seconds
Started Aug 25 07:32:31 AM UTC 24
Finished Aug 25 07:32:34 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562136939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.562136939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.2105552811
Short name T508
Test name
Test status
Simulation time 52891214 ps
CPU time 1.16 seconds
Started Aug 25 07:32:44 AM UTC 24
Finished Aug 25 07:32:46 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105552811 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2105552811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.2295465680
Short name T275
Test name
Test status
Simulation time 34020537 ps
CPU time 3.25 seconds
Started Aug 25 07:32:36 AM UTC 24
Finished Aug 25 07:32:41 AM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295465680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2295465680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.1831166167
Short name T507
Test name
Test status
Simulation time 148921493 ps
CPU time 6.9 seconds
Started Aug 25 07:32:37 AM UTC 24
Finished Aug 25 07:32:46 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831166167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1831166167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.3825363476
Short name T386
Test name
Test status
Simulation time 108904255 ps
CPU time 7.34 seconds
Started Aug 25 07:32:39 AM UTC 24
Finished Aug 25 07:32:47 AM UTC 24
Peak memory 213800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825363476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3825363476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_random.3866398279
Short name T505
Test name
Test status
Simulation time 267776615 ps
CPU time 6.83 seconds
Started Aug 25 07:32:35 AM UTC 24
Finished Aug 25 07:32:43 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866398279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3866398279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.2748838565
Short name T504
Test name
Test status
Simulation time 290008239 ps
CPU time 4.64 seconds
Started Aug 25 07:32:32 AM UTC 24
Finished Aug 25 07:32:38 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748838565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2748838565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.3403626895
Short name T528
Test name
Test status
Simulation time 3863396194 ps
CPU time 40.25 seconds
Started Aug 25 07:32:33 AM UTC 24
Finished Aug 25 07:33:15 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403626895 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3403626895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.947746786
Short name T327
Test name
Test status
Simulation time 51121308 ps
CPU time 3.98 seconds
Started Aug 25 07:32:33 AM UTC 24
Finished Aug 25 07:32:38 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947746786 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.947746786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.3720505008
Short name T348
Test name
Test status
Simulation time 129733342 ps
CPU time 6.13 seconds
Started Aug 25 07:32:33 AM UTC 24
Finished Aug 25 07:32:41 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720505008 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3720505008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.2234637056
Short name T418
Test name
Test status
Simulation time 39352718 ps
CPU time 2.72 seconds
Started Aug 25 07:32:41 AM UTC 24
Finished Aug 25 07:32:45 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234637056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2234637056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.2025090862
Short name T503
Test name
Test status
Simulation time 34142836 ps
CPU time 3.08 seconds
Started Aug 25 07:32:32 AM UTC 24
Finished Aug 25 07:32:36 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025090862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2025090862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.2294782909
Short name T393
Test name
Test status
Simulation time 2783732451 ps
CPU time 57.21 seconds
Started Aug 25 07:32:42 AM UTC 24
Finished Aug 25 07:33:41 AM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294782909 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2294782909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all_with_rand_reset.2882545042
Short name T95
Test name
Test status
Simulation time 319243741 ps
CPU time 24.52 seconds
Started Aug 25 07:32:42 AM UTC 24
Finished Aug 25 07:33:08 AM UTC 24
Peak memory 232484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2882545042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymg
r_stress_all_with_rand_reset.2882545042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.1192321317
Short name T529
Test name
Test status
Simulation time 1285802319 ps
CPU time 39.26 seconds
Started Aug 25 07:32:36 AM UTC 24
Finished Aug 25 07:33:17 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192321317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1192321317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.2500421627
Short name T411
Test name
Test status
Simulation time 379939346 ps
CPU time 3.31 seconds
Started Aug 25 07:32:42 AM UTC 24
Finished Aug 25 07:32:46 AM UTC 24
Peak memory 218092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500421627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2500421627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.2610690448
Short name T515
Test name
Test status
Simulation time 43058279 ps
CPU time 1.3 seconds
Started Aug 25 07:32:58 AM UTC 24
Finished Aug 25 07:33:01 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610690448 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2610690448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.537041587
Short name T401
Test name
Test status
Simulation time 547782453 ps
CPU time 9.66 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:59 AM UTC 24
Peak memory 232492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537041587 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.537041587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.2235145612
Short name T223
Test name
Test status
Simulation time 164108846 ps
CPU time 5.66 seconds
Started Aug 25 07:32:56 AM UTC 24
Finished Aug 25 07:33:03 AM UTC 24
Peak memory 218628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235145612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2235145612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.4238328268
Short name T147
Test name
Test status
Simulation time 73553571 ps
CPU time 4.79 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:54 AM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238328268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.4238328268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.2992290500
Short name T513
Test name
Test status
Simulation time 345291989 ps
CPU time 5.86 seconds
Started Aug 25 07:32:49 AM UTC 24
Finished Aug 25 07:32:56 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992290500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2992290500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.1653599982
Short name T227
Test name
Test status
Simulation time 134275832 ps
CPU time 3.44 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:53 AM UTC 24
Peak memory 230208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653599982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1653599982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_random.1625292382
Short name T383
Test name
Test status
Simulation time 2935802493 ps
CPU time 12.09 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:33:01 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625292382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1625292382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.2800478697
Short name T287
Test name
Test status
Simulation time 44464212 ps
CPU time 2.48 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:51 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800478697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2800478697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.4079238046
Short name T392
Test name
Test status
Simulation time 41149524 ps
CPU time 4.13 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:53 AM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079238046 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4079238046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.2421556390
Short name T511
Test name
Test status
Simulation time 287196300 ps
CPU time 5.18 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:54 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421556390 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2421556390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.1050756921
Short name T514
Test name
Test status
Simulation time 181884020 ps
CPU time 3.19 seconds
Started Aug 25 07:32:56 AM UTC 24
Finished Aug 25 07:33:01 AM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050756921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1050756921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.146790549
Short name T510
Test name
Test status
Simulation time 412522215 ps
CPU time 5.28 seconds
Started Aug 25 07:32:45 AM UTC 24
Finished Aug 25 07:32:52 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146790549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.146790549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.1054911666
Short name T99
Test name
Test status
Simulation time 1092766051 ps
CPU time 24.76 seconds
Started Aug 25 07:32:58 AM UTC 24
Finished Aug 25 07:33:24 AM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1054911666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymg
r_stress_all_with_rand_reset.1054911666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.1323438787
Short name T355
Test name
Test status
Simulation time 685269599 ps
CPU time 8.78 seconds
Started Aug 25 07:32:48 AM UTC 24
Finished Aug 25 07:32:58 AM UTC 24
Peak memory 230500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323438787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1323438787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.1058393639
Short name T101
Test name
Test status
Simulation time 57140194 ps
CPU time 4.06 seconds
Started Aug 25 07:32:56 AM UTC 24
Finished Aug 25 07:33:01 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058393639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1058393639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.2793450766
Short name T522
Test name
Test status
Simulation time 21564113 ps
CPU time 1.15 seconds
Started Aug 25 07:33:06 AM UTC 24
Finished Aug 25 07:33:09 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793450766 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2793450766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.29314895
Short name T264
Test name
Test status
Simulation time 50976434 ps
CPU time 4.98 seconds
Started Aug 25 07:32:59 AM UTC 24
Finished Aug 25 07:33:06 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29314895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keym
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.29314895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.1475405533
Short name T38
Test name
Test status
Simulation time 198122608 ps
CPU time 4.91 seconds
Started Aug 25 07:33:03 AM UTC 24
Finished Aug 25 07:33:09 AM UTC 24
Peak memory 220044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475405533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1475405533
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.989172044
Short name T403
Test name
Test status
Simulation time 286027754 ps
CPU time 5 seconds
Started Aug 25 07:33:02 AM UTC 24
Finished Aug 25 07:33:08 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989172044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.989172044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.1808897153
Short name T344
Test name
Test status
Simulation time 271970019 ps
CPU time 2.19 seconds
Started Aug 25 07:33:03 AM UTC 24
Finished Aug 25 07:33:06 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808897153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1808897153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.284151510
Short name T226
Test name
Test status
Simulation time 310117959 ps
CPU time 3.8 seconds
Started Aug 25 07:33:02 AM UTC 24
Finished Aug 25 07:33:07 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284151510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.284151510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_random.3117229786
Short name T516
Test name
Test status
Simulation time 189829575 ps
CPU time 9.98 seconds
Started Aug 25 07:32:59 AM UTC 24
Finished Aug 25 07:33:11 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117229786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3117229786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.2546966032
Short name T364
Test name
Test status
Simulation time 195408424 ps
CPU time 3.46 seconds
Started Aug 25 07:32:58 AM UTC 24
Finished Aug 25 07:33:03 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546966032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2546966032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.4032395488
Short name T519
Test name
Test status
Simulation time 480977200 ps
CPU time 5.6 seconds
Started Aug 25 07:32:58 AM UTC 24
Finished Aug 25 07:33:05 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032395488 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.4032395488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.3759380652
Short name T518
Test name
Test status
Simulation time 461723753 ps
CPU time 4.17 seconds
Started Aug 25 07:32:58 AM UTC 24
Finished Aug 25 07:33:04 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759380652 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3759380652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.368345040
Short name T520
Test name
Test status
Simulation time 310427756 ps
CPU time 7.48 seconds
Started Aug 25 07:32:59 AM UTC 24
Finished Aug 25 07:33:08 AM UTC 24
Peak memory 218052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368345040 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.368345040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.3191674349
Short name T420
Test name
Test status
Simulation time 45019593 ps
CPU time 1.79 seconds
Started Aug 25 07:33:04 AM UTC 24
Finished Aug 25 07:33:07 AM UTC 24
Peak memory 215648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191674349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3191674349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.2107276353
Short name T517
Test name
Test status
Simulation time 18391791 ps
CPU time 2.28 seconds
Started Aug 25 07:32:58 AM UTC 24
Finished Aug 25 07:33:02 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107276353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2107276353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.84658439
Short name T521
Test name
Test status
Simulation time 248461871 ps
CPU time 4.62 seconds
Started Aug 25 07:33:03 AM UTC 24
Finished Aug 25 07:33:09 AM UTC 24
Peak memory 217540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84658439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.84658439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.2894068497
Short name T524
Test name
Test status
Simulation time 507463407 ps
CPU time 4.76 seconds
Started Aug 25 07:33:04 AM UTC 24
Finished Aug 25 07:33:10 AM UTC 24
Peak memory 219948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894068497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2894068497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.2404679824
Short name T532
Test name
Test status
Simulation time 65249075 ps
CPU time 1.39 seconds
Started Aug 25 07:33:17 AM UTC 24
Finished Aug 25 07:33:19 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404679824 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2404679824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.1169140443
Short name T433
Test name
Test status
Simulation time 117004890 ps
CPU time 4.3 seconds
Started Aug 25 07:33:09 AM UTC 24
Finished Aug 25 07:33:15 AM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169140443 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1169140443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.1438818701
Short name T531
Test name
Test status
Simulation time 53714497 ps
CPU time 3.23 seconds
Started Aug 25 07:33:13 AM UTC 24
Finished Aug 25 07:33:18 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438818701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1438818701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.2714439804
Short name T527
Test name
Test status
Simulation time 126852206 ps
CPU time 3.02 seconds
Started Aug 25 07:33:10 AM UTC 24
Finished Aug 25 07:33:15 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714439804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2714439804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.3105710667
Short name T323
Test name
Test status
Simulation time 134689538 ps
CPU time 6.58 seconds
Started Aug 25 07:33:12 AM UTC 24
Finished Aug 25 07:33:20 AM UTC 24
Peak memory 216116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105710667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3105710667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.322790148
Short name T312
Test name
Test status
Simulation time 92453086 ps
CPU time 6.48 seconds
Started Aug 25 07:33:10 AM UTC 24
Finished Aug 25 07:33:18 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322790148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.322790148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_random.857233663
Short name T578
Test name
Test status
Simulation time 2249717493 ps
CPU time 62.81 seconds
Started Aug 25 07:33:09 AM UTC 24
Finished Aug 25 07:34:14 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857233663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.857233663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.4188900244
Short name T372
Test name
Test status
Simulation time 315592446 ps
CPU time 4.1 seconds
Started Aug 25 07:33:07 AM UTC 24
Finished Aug 25 07:33:13 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188900244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4188900244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.1701769714
Short name T530
Test name
Test status
Simulation time 285685938 ps
CPU time 7.55 seconds
Started Aug 25 07:33:09 AM UTC 24
Finished Aug 25 07:33:18 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701769714 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1701769714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.2669428335
Short name T525
Test name
Test status
Simulation time 102101226 ps
CPU time 5.5 seconds
Started Aug 25 07:33:07 AM UTC 24
Finished Aug 25 07:33:14 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669428335 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2669428335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.3635339348
Short name T526
Test name
Test status
Simulation time 95564241 ps
CPU time 4.14 seconds
Started Aug 25 07:33:09 AM UTC 24
Finished Aug 25 07:33:14 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635339348 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3635339348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.1650034322
Short name T536
Test name
Test status
Simulation time 160169026 ps
CPU time 6.98 seconds
Started Aug 25 07:33:15 AM UTC 24
Finished Aug 25 07:33:24 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650034322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1650034322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.1100937777
Short name T523
Test name
Test status
Simulation time 770934258 ps
CPU time 6.79 seconds
Started Aug 25 07:33:07 AM UTC 24
Finished Aug 25 07:33:15 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100937777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1100937777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.337274355
Short name T302
Test name
Test status
Simulation time 500945504 ps
CPU time 13.92 seconds
Started Aug 25 07:33:10 AM UTC 24
Finished Aug 25 07:33:26 AM UTC 24
Peak memory 220028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337274355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.337274355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.3594883661
Short name T533
Test name
Test status
Simulation time 512436565 ps
CPU time 3.55 seconds
Started Aug 25 07:33:15 AM UTC 24
Finished Aug 25 07:33:20 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594883661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3594883661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1261552993
Short name T64
Test name
Test status
Simulation time 29017230 ps
CPU time 1.16 seconds
Started Aug 25 07:29:41 AM UTC 24
Finished Aug 25 07:29:44 AM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261552993 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1261552993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.2614421311
Short name T74
Test name
Test status
Simulation time 121885962 ps
CPU time 3.55 seconds
Started Aug 25 07:29:32 AM UTC 24
Finished Aug 25 07:29:37 AM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614421311 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2614421311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.562956917
Short name T21
Test name
Test status
Simulation time 96055307 ps
CPU time 3.29 seconds
Started Aug 25 07:29:38 AM UTC 24
Finished Aug 25 07:29:43 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562956917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.562956917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.1870315390
Short name T72
Test name
Test status
Simulation time 21930954 ps
CPU time 2.43 seconds
Started Aug 25 07:29:32 AM UTC 24
Finished Aug 25 07:29:36 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870315390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1870315390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.915732899
Short name T51
Test name
Test status
Simulation time 675849146 ps
CPU time 7.46 seconds
Started Aug 25 07:29:37 AM UTC 24
Finished Aug 25 07:29:46 AM UTC 24
Peak memory 226052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915732899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.915732899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.2996845842
Short name T77
Test name
Test status
Simulation time 102860932 ps
CPU time 2.9 seconds
Started Aug 25 07:29:37 AM UTC 24
Finished Aug 25 07:29:41 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996845842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2996845842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_random.2911013662
Short name T75
Test name
Test status
Simulation time 436727459 ps
CPU time 7.9 seconds
Started Aug 25 07:29:28 AM UTC 24
Finished Aug 25 07:29:38 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911013662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2911013662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.840709441
Short name T13
Test name
Test status
Simulation time 1640667984 ps
CPU time 16.89 seconds
Started Aug 25 07:29:41 AM UTC 24
Finished Aug 25 07:30:00 AM UTC 24
Peak memory 254284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840709441 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.840709441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.1902573023
Short name T73
Test name
Test status
Simulation time 507627274 ps
CPU time 9.67 seconds
Started Aug 25 07:29:25 AM UTC 24
Finished Aug 25 07:29:36 AM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902573023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1902573023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.2153703507
Short name T97
Test name
Test status
Simulation time 42337206 ps
CPU time 3.16 seconds
Started Aug 25 07:29:27 AM UTC 24
Finished Aug 25 07:29:32 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153703507 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2153703507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.1007565226
Short name T98
Test name
Test status
Simulation time 472792752 ps
CPU time 6.09 seconds
Started Aug 25 07:29:26 AM UTC 24
Finished Aug 25 07:29:34 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007565226 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1007565226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.1011668980
Short name T76
Test name
Test status
Simulation time 2958969064 ps
CPU time 9.31 seconds
Started Aug 25 07:29:27 AM UTC 24
Finished Aug 25 07:29:38 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011668980 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1011668980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.1706859066
Short name T103
Test name
Test status
Simulation time 63506956 ps
CPU time 2.43 seconds
Started Aug 25 07:29:38 AM UTC 24
Finished Aug 25 07:29:42 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706859066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1706859066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.2433511667
Short name T96
Test name
Test status
Simulation time 146659439 ps
CPU time 6.2 seconds
Started Aug 25 07:29:24 AM UTC 24
Finished Aug 25 07:29:32 AM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433511667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2433511667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.3321812439
Short name T154
Test name
Test status
Simulation time 649560233 ps
CPU time 10.51 seconds
Started Aug 25 07:29:39 AM UTC 24
Finished Aug 25 07:29:51 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321812439 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3321812439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.938911159
Short name T102
Test name
Test status
Simulation time 396923129 ps
CPU time 4.66 seconds
Started Aug 25 07:29:36 AM UTC 24
Finished Aug 25 07:29:42 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938911159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.938911159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.3911240431
Short name T40
Test name
Test status
Simulation time 1666122788 ps
CPU time 13.18 seconds
Started Aug 25 07:29:39 AM UTC 24
Finished Aug 25 07:29:54 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911240431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3911240431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.3949975704
Short name T543
Test name
Test status
Simulation time 50301487 ps
CPU time 1.12 seconds
Started Aug 25 07:33:27 AM UTC 24
Finished Aug 25 07:33:29 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949975704 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3949975704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.3988766744
Short name T540
Test name
Test status
Simulation time 83422322 ps
CPU time 2.53 seconds
Started Aug 25 07:33:24 AM UTC 24
Finished Aug 25 07:33:28 AM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988766744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3988766744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.3307531712
Short name T301
Test name
Test status
Simulation time 34557743 ps
CPU time 3.36 seconds
Started Aug 25 07:33:21 AM UTC 24
Finished Aug 25 07:33:26 AM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307531712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3307531712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.581486681
Short name T544
Test name
Test status
Simulation time 81072063 ps
CPU time 4.89 seconds
Started Aug 25 07:33:23 AM UTC 24
Finished Aug 25 07:33:29 AM UTC 24
Peak memory 226120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581486681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.581486681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.2375686773
Short name T276
Test name
Test status
Simulation time 131803480 ps
CPU time 3.35 seconds
Started Aug 25 07:33:23 AM UTC 24
Finished Aug 25 07:33:28 AM UTC 24
Peak memory 226052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375686773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2375686773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.2560674048
Short name T330
Test name
Test status
Simulation time 152217823 ps
CPU time 5.77 seconds
Started Aug 25 07:33:21 AM UTC 24
Finished Aug 25 07:33:28 AM UTC 24
Peak memory 232512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560674048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2560674048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_random.2716582434
Short name T539
Test name
Test status
Simulation time 117264277 ps
CPU time 6.24 seconds
Started Aug 25 07:33:19 AM UTC 24
Finished Aug 25 07:33:26 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716582434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2716582434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.260361931
Short name T338
Test name
Test status
Simulation time 243535762 ps
CPU time 8.92 seconds
Started Aug 25 07:33:19 AM UTC 24
Finished Aug 25 07:33:29 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260361931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.260361931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.1093801869
Short name T534
Test name
Test status
Simulation time 286693801 ps
CPU time 2.5 seconds
Started Aug 25 07:33:19 AM UTC 24
Finished Aug 25 07:33:22 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093801869 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1093801869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.122064103
Short name T535
Test name
Test status
Simulation time 108105814 ps
CPU time 2.8 seconds
Started Aug 25 07:33:19 AM UTC 24
Finished Aug 25 07:33:23 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122064103 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.122064103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.3046408582
Short name T538
Test name
Test status
Simulation time 82535386 ps
CPU time 5.15 seconds
Started Aug 25 07:33:19 AM UTC 24
Finished Aug 25 07:33:25 AM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046408582 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3046408582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.1693469158
Short name T545
Test name
Test status
Simulation time 141900866 ps
CPU time 3.98 seconds
Started Aug 25 07:33:24 AM UTC 24
Finished Aug 25 07:33:30 AM UTC 24
Peak memory 224168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693469158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1693469158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.987161459
Short name T537
Test name
Test status
Simulation time 251549876 ps
CPU time 5.68 seconds
Started Aug 25 07:33:17 AM UTC 24
Finished Aug 25 07:33:24 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987161459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.987161459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.2759836688
Short name T191
Test name
Test status
Simulation time 1701897637 ps
CPU time 26.02 seconds
Started Aug 25 07:33:26 AM UTC 24
Finished Aug 25 07:33:53 AM UTC 24
Peak memory 232468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759836688 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2759836688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.1841835040
Short name T185
Test name
Test status
Simulation time 10847860929 ps
CPU time 44.08 seconds
Started Aug 25 07:33:27 AM UTC 24
Finished Aug 25 07:34:13 AM UTC 24
Peak memory 231652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1841835040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg
r_stress_all_with_rand_reset.1841835040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.1491654591
Short name T548
Test name
Test status
Simulation time 720348095 ps
CPU time 9.34 seconds
Started Aug 25 07:33:23 AM UTC 24
Finished Aug 25 07:33:34 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491654591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1491654591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.4244208227
Short name T542
Test name
Test status
Simulation time 28889275 ps
CPU time 1.94 seconds
Started Aug 25 07:33:26 AM UTC 24
Finished Aug 25 07:33:29 AM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244208227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.4244208227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.3072237124
Short name T554
Test name
Test status
Simulation time 14046490 ps
CPU time 1.46 seconds
Started Aug 25 07:33:36 AM UTC 24
Finished Aug 25 07:33:39 AM UTC 24
Peak memory 213672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072237124 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3072237124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1023083718
Short name T424
Test name
Test status
Simulation time 104734373 ps
CPU time 3.12 seconds
Started Aug 25 07:33:29 AM UTC 24
Finished Aug 25 07:33:34 AM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023083718 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1023083718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.2744858168
Short name T555
Test name
Test status
Simulation time 90247932 ps
CPU time 4.55 seconds
Started Aug 25 07:33:34 AM UTC 24
Finished Aug 25 07:33:39 AM UTC 24
Peak memory 219948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744858168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2744858168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.3996326595
Short name T549
Test name
Test status
Simulation time 52884130 ps
CPU time 3.15 seconds
Started Aug 25 07:33:30 AM UTC 24
Finished Aug 25 07:33:35 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996326595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3996326595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.1284283677
Short name T259
Test name
Test status
Simulation time 600259665 ps
CPU time 10.93 seconds
Started Aug 25 07:33:31 AM UTC 24
Finished Aug 25 07:33:43 AM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284283677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1284283677
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.595944222
Short name T551
Test name
Test status
Simulation time 275299024 ps
CPU time 3.99 seconds
Started Aug 25 07:33:31 AM UTC 24
Finished Aug 25 07:33:36 AM UTC 24
Peak memory 226016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595944222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.595944222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.1075766290
Short name T352
Test name
Test status
Simulation time 548075668 ps
CPU time 5.4 seconds
Started Aug 25 07:33:30 AM UTC 24
Finished Aug 25 07:33:37 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075766290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1075766290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_random.2178257907
Short name T303
Test name
Test status
Simulation time 36161778 ps
CPU time 3.48 seconds
Started Aug 25 07:33:29 AM UTC 24
Finished Aug 25 07:33:34 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178257907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2178257907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.3056675042
Short name T380
Test name
Test status
Simulation time 813126392 ps
CPU time 12.6 seconds
Started Aug 25 07:33:28 AM UTC 24
Finished Aug 25 07:33:42 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056675042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3056675042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.1399368183
Short name T547
Test name
Test status
Simulation time 153115125 ps
CPU time 2.73 seconds
Started Aug 25 07:33:29 AM UTC 24
Finished Aug 25 07:33:33 AM UTC 24
Peak memory 217904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399368183 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1399368183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.4059602673
Short name T546
Test name
Test status
Simulation time 149801675 ps
CPU time 3.49 seconds
Started Aug 25 07:33:28 AM UTC 24
Finished Aug 25 07:33:33 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059602673 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4059602673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.1516731631
Short name T552
Test name
Test status
Simulation time 515151130 ps
CPU time 6.56 seconds
Started Aug 25 07:33:29 AM UTC 24
Finished Aug 25 07:33:37 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516731631 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1516731631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.1381562993
Short name T553
Test name
Test status
Simulation time 79533501 ps
CPU time 3.65 seconds
Started Aug 25 07:33:34 AM UTC 24
Finished Aug 25 07:33:39 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381562993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1381562993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.2478372775
Short name T550
Test name
Test status
Simulation time 467790455 ps
CPU time 6.96 seconds
Started Aug 25 07:33:27 AM UTC 24
Finished Aug 25 07:33:35 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478372775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2478372775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.244410380
Short name T334
Test name
Test status
Simulation time 4464836149 ps
CPU time 65.58 seconds
Started Aug 25 07:33:35 AM UTC 24
Finished Aug 25 07:34:43 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244410380 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.244410380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.2194303657
Short name T640
Test name
Test status
Simulation time 2094077170 ps
CPU time 90.66 seconds
Started Aug 25 07:33:30 AM UTC 24
Finished Aug 25 07:35:04 AM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194303657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2194303657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.800627603
Short name T406
Test name
Test status
Simulation time 93254030 ps
CPU time 5.75 seconds
Started Aug 25 07:33:35 AM UTC 24
Finished Aug 25 07:33:42 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800627603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.800627603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.3048986848
Short name T560
Test name
Test status
Simulation time 15258611 ps
CPU time 1.5 seconds
Started Aug 25 07:33:44 AM UTC 24
Finished Aug 25 07:33:47 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048986848 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3048986848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.608865436
Short name T562
Test name
Test status
Simulation time 787483614 ps
CPU time 5.99 seconds
Started Aug 25 07:33:43 AM UTC 24
Finished Aug 25 07:33:50 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608865436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.608865436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.2011984362
Short name T559
Test name
Test status
Simulation time 70898764 ps
CPU time 5 seconds
Started Aug 25 07:33:41 AM UTC 24
Finished Aug 25 07:33:47 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011984362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2011984362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.589615978
Short name T50
Test name
Test status
Simulation time 300574566 ps
CPU time 12.58 seconds
Started Aug 25 07:33:42 AM UTC 24
Finished Aug 25 07:33:56 AM UTC 24
Peak memory 224060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589615978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.589615978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.2944370618
Short name T241
Test name
Test status
Simulation time 326910151 ps
CPU time 6.78 seconds
Started Aug 25 07:33:43 AM UTC 24
Finished Aug 25 07:33:51 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944370618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2944370618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.2570214643
Short name T225
Test name
Test status
Simulation time 107001098 ps
CPU time 4.83 seconds
Started Aug 25 07:33:41 AM UTC 24
Finished Aug 25 07:33:47 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570214643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2570214643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_random.1908066427
Short name T564
Test name
Test status
Simulation time 247210367 ps
CPU time 9.84 seconds
Started Aug 25 07:33:40 AM UTC 24
Finished Aug 25 07:33:51 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908066427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1908066427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.1196481058
Short name T365
Test name
Test status
Simulation time 46372261 ps
CPU time 2.49 seconds
Started Aug 25 07:33:36 AM UTC 24
Finished Aug 25 07:33:40 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196481058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1196481058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.3923590721
Short name T563
Test name
Test status
Simulation time 240826080 ps
CPU time 10.18 seconds
Started Aug 25 07:33:38 AM UTC 24
Finished Aug 25 07:33:50 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923590721 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3923590721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.1978625006
Short name T557
Test name
Test status
Simulation time 32527505 ps
CPU time 3.26 seconds
Started Aug 25 07:33:37 AM UTC 24
Finished Aug 25 07:33:42 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978625006 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1978625006
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.3828164193
Short name T558
Test name
Test status
Simulation time 145077100 ps
CPU time 3.62 seconds
Started Aug 25 07:33:38 AM UTC 24
Finished Aug 25 07:33:44 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828164193 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3828164193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.158117970
Short name T567
Test name
Test status
Simulation time 1950643898 ps
CPU time 18.5 seconds
Started Aug 25 07:33:43 AM UTC 24
Finished Aug 25 07:34:03 AM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158117970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.158117970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.2990416566
Short name T556
Test name
Test status
Simulation time 95178547 ps
CPU time 3.11 seconds
Started Aug 25 07:33:36 AM UTC 24
Finished Aug 25 07:33:40 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990416566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2990416566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.4179116400
Short name T200
Test name
Test status
Simulation time 659947009 ps
CPU time 29.37 seconds
Started Aug 25 07:33:44 AM UTC 24
Finished Aug 25 07:34:15 AM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179116400 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4179116400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1481687815
Short name T591
Test name
Test status
Simulation time 963463321 ps
CPU time 39.54 seconds
Started Aug 25 07:33:42 AM UTC 24
Finished Aug 25 07:34:23 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481687815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1481687815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.712605758
Short name T192
Test name
Test status
Simulation time 1368401186 ps
CPU time 9.3 seconds
Started Aug 25 07:33:44 AM UTC 24
Finished Aug 25 07:33:55 AM UTC 24
Peak memory 220376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712605758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.712605758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.2702850139
Short name T541
Test name
Test status
Simulation time 15463308 ps
CPU time 1.11 seconds
Started Aug 25 07:33:59 AM UTC 24
Finished Aug 25 07:34:01 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702850139 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2702850139
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.1439288041
Short name T194
Test name
Test status
Simulation time 191348993 ps
CPU time 5.08 seconds
Started Aug 25 07:33:51 AM UTC 24
Finished Aug 25 07:33:57 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439288041 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1439288041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.2436094655
Short name T568
Test name
Test status
Simulation time 208887777 ps
CPU time 7.66 seconds
Started Aug 25 07:33:54 AM UTC 24
Finished Aug 25 07:34:03 AM UTC 24
Peak memory 220416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436094655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2436094655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.1243499679
Short name T193
Test name
Test status
Simulation time 45346393 ps
CPU time 1.99 seconds
Started Aug 25 07:33:52 AM UTC 24
Finished Aug 25 07:33:55 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243499679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1243499679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.1748040012
Short name T367
Test name
Test status
Simulation time 731209353 ps
CPU time 6.6 seconds
Started Aug 25 07:33:54 AM UTC 24
Finished Aug 25 07:34:02 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748040012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1748040012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.1164044586
Short name T198
Test name
Test status
Simulation time 78051683 ps
CPU time 3.36 seconds
Started Aug 25 07:33:54 AM UTC 24
Finished Aug 25 07:33:59 AM UTC 24
Peak memory 226016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164044586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1164044586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.3597056763
Short name T195
Test name
Test status
Simulation time 453223792 ps
CPU time 4.59 seconds
Started Aug 25 07:33:52 AM UTC 24
Finished Aug 25 07:33:58 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597056763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3597056763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_random.2363364904
Short name T573
Test name
Test status
Simulation time 344004721 ps
CPU time 14.29 seconds
Started Aug 25 07:33:51 AM UTC 24
Finished Aug 25 07:34:06 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363364904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2363364904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.3627619111
Short name T565
Test name
Test status
Simulation time 54659306 ps
CPU time 3.86 seconds
Started Aug 25 07:33:48 AM UTC 24
Finished Aug 25 07:33:53 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627619111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3627619111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.2261391670
Short name T197
Test name
Test status
Simulation time 224340258 ps
CPU time 9.82 seconds
Started Aug 25 07:33:48 AM UTC 24
Finished Aug 25 07:33:59 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261391670 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2261391670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.3335010951
Short name T354
Test name
Test status
Simulation time 416065039 ps
CPU time 12.95 seconds
Started Aug 25 07:33:48 AM UTC 24
Finished Aug 25 07:34:02 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335010951 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3335010951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.624190433
Short name T196
Test name
Test status
Simulation time 143568783 ps
CPU time 6.43 seconds
Started Aug 25 07:33:51 AM UTC 24
Finished Aug 25 07:33:58 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624190433 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.624190433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.3303053290
Short name T566
Test name
Test status
Simulation time 147696522 ps
CPU time 2.69 seconds
Started Aug 25 07:33:55 AM UTC 24
Finished Aug 25 07:33:59 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303053290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3303053290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2791800876
Short name T561
Test name
Test status
Simulation time 175524925 ps
CPU time 3.81 seconds
Started Aug 25 07:33:44 AM UTC 24
Finished Aug 25 07:33:50 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791800876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2791800876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.1088971219
Short name T149
Test name
Test status
Simulation time 976275191 ps
CPU time 13.88 seconds
Started Aug 25 07:33:56 AM UTC 24
Finished Aug 25 07:34:12 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088971219 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1088971219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.2916829502
Short name T186
Test name
Test status
Simulation time 2815079887 ps
CPU time 15.7 seconds
Started Aug 25 07:33:57 AM UTC 24
Finished Aug 25 07:34:15 AM UTC 24
Peak memory 230368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2916829502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymg
r_stress_all_with_rand_reset.2916829502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.3349437781
Short name T570
Test name
Test status
Simulation time 765334662 ps
CPU time 10.74 seconds
Started Aug 25 07:33:53 AM UTC 24
Finished Aug 25 07:34:05 AM UTC 24
Peak memory 232500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349437781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3349437781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.1705263962
Short name T408
Test name
Test status
Simulation time 93639516 ps
CPU time 5.24 seconds
Started Aug 25 07:33:56 AM UTC 24
Finished Aug 25 07:34:03 AM UTC 24
Peak memory 217908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705263962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1705263962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.2129821968
Short name T579
Test name
Test status
Simulation time 90924376 ps
CPU time 1.27 seconds
Started Aug 25 07:34:12 AM UTC 24
Finished Aug 25 07:34:14 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129821968 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2129821968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.2062413257
Short name T298
Test name
Test status
Simulation time 96072555 ps
CPU time 5.77 seconds
Started Aug 25 07:34:03 AM UTC 24
Finished Aug 25 07:34:10 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062413257 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2062413257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.2440887083
Short name T361
Test name
Test status
Simulation time 193590702 ps
CPU time 3.79 seconds
Started Aug 25 07:34:10 AM UTC 24
Finished Aug 25 07:34:15 AM UTC 24
Peak memory 228136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440887083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2440887083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.3145987134
Short name T575
Test name
Test status
Simulation time 519955239 ps
CPU time 2.84 seconds
Started Aug 25 07:34:04 AM UTC 24
Finished Aug 25 07:34:08 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145987134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3145987134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.148153884
Short name T278
Test name
Test status
Simulation time 53754602 ps
CPU time 3.02 seconds
Started Aug 25 07:34:06 AM UTC 24
Finished Aug 25 07:34:10 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148153884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.148153884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.240229711
Short name T576
Test name
Test status
Simulation time 171825806 ps
CPU time 3.91 seconds
Started Aug 25 07:34:04 AM UTC 24
Finished Aug 25 07:34:09 AM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240229711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.240229711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_random.3809227489
Short name T581
Test name
Test status
Simulation time 1327430167 ps
CPU time 12.41 seconds
Started Aug 25 07:34:03 AM UTC 24
Finished Aug 25 07:34:17 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809227489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3809227489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.3953687405
Short name T273
Test name
Test status
Simulation time 547774755 ps
CPU time 5.47 seconds
Started Aug 25 07:34:00 AM UTC 24
Finished Aug 25 07:34:06 AM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953687405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3953687405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.4057681116
Short name T571
Test name
Test status
Simulation time 86219350 ps
CPU time 5.03 seconds
Started Aug 25 07:34:00 AM UTC 24
Finished Aug 25 07:34:06 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057681116 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4057681116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.3730449802
Short name T572
Test name
Test status
Simulation time 71096158 ps
CPU time 5.16 seconds
Started Aug 25 07:34:00 AM UTC 24
Finished Aug 25 07:34:06 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730449802 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3730449802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.4236920012
Short name T574
Test name
Test status
Simulation time 299937844 ps
CPU time 4.3 seconds
Started Aug 25 07:34:02 AM UTC 24
Finished Aug 25 07:34:07 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236920012 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4236920012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.455766719
Short name T586
Test name
Test status
Simulation time 465840265 ps
CPU time 5.77 seconds
Started Aug 25 07:34:10 AM UTC 24
Finished Aug 25 07:34:18 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455766719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.455766719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.4184288798
Short name T569
Test name
Test status
Simulation time 398277145 ps
CPU time 3.23 seconds
Started Aug 25 07:34:00 AM UTC 24
Finished Aug 25 07:34:04 AM UTC 24
Peak memory 218248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184288798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4184288798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.808052189
Short name T336
Test name
Test status
Simulation time 2393407168 ps
CPU time 30.57 seconds
Started Aug 25 07:34:11 AM UTC 24
Finished Aug 25 07:34:43 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808052189 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.808052189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.1445342140
Short name T577
Test name
Test status
Simulation time 393207371 ps
CPU time 7.19 seconds
Started Aug 25 07:34:04 AM UTC 24
Finished Aug 25 07:34:13 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445342140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1445342140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.537999071
Short name T580
Test name
Test status
Simulation time 485062771 ps
CPU time 2.6 seconds
Started Aug 25 07:34:11 AM UTC 24
Finished Aug 25 07:34:14 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537999071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.537999071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.1520304087
Short name T589
Test name
Test status
Simulation time 120927774 ps
CPU time 1.14 seconds
Started Aug 25 07:34:18 AM UTC 24
Finished Aug 25 07:34:20 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520304087 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1520304087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.2585362348
Short name T379
Test name
Test status
Simulation time 170728380 ps
CPU time 13.83 seconds
Started Aug 25 07:34:13 AM UTC 24
Finished Aug 25 07:34:28 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585362348 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2585362348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.1634214822
Short name T145
Test name
Test status
Simulation time 148505064 ps
CPU time 4.56 seconds
Started Aug 25 07:34:17 AM UTC 24
Finished Aug 25 07:34:23 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634214822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1634214822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.627957016
Short name T597
Test name
Test status
Simulation time 388662904 ps
CPU time 13.89 seconds
Started Aug 25 07:34:13 AM UTC 24
Finished Aug 25 07:34:28 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627957016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.627957016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.1839230531
Short name T684
Test name
Test status
Simulation time 28751511052 ps
CPU time 77.64 seconds
Started Aug 25 07:34:15 AM UTC 24
Finished Aug 25 07:35:35 AM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839230531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1839230531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.3464332599
Short name T622
Test name
Test status
Simulation time 4286169834 ps
CPU time 34.33 seconds
Started Aug 25 07:34:14 AM UTC 24
Finished Aug 25 07:34:50 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464332599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3464332599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_random.4191589389
Short name T588
Test name
Test status
Simulation time 97551981 ps
CPU time 4.66 seconds
Started Aug 25 07:34:13 AM UTC 24
Finished Aug 25 07:34:19 AM UTC 24
Peak memory 215472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191589389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4191589389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.276069862
Short name T584
Test name
Test status
Simulation time 43452129 ps
CPU time 4.32 seconds
Started Aug 25 07:34:12 AM UTC 24
Finished Aug 25 07:34:17 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276069862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.276069862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.3419261018
Short name T587
Test name
Test status
Simulation time 152631043 ps
CPU time 5.57 seconds
Started Aug 25 07:34:12 AM UTC 24
Finished Aug 25 07:34:19 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419261018 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3419261018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.3828529011
Short name T583
Test name
Test status
Simulation time 219818297 ps
CPU time 4.12 seconds
Started Aug 25 07:34:12 AM UTC 24
Finished Aug 25 07:34:17 AM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828529011 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3828529011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.3360794745
Short name T614
Test name
Test status
Simulation time 3191291228 ps
CPU time 28.05 seconds
Started Aug 25 07:34:13 AM UTC 24
Finished Aug 25 07:34:43 AM UTC 24
Peak memory 218336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360794745 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3360794745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.3297563497
Short name T590
Test name
Test status
Simulation time 233645444 ps
CPU time 3.07 seconds
Started Aug 25 07:34:17 AM UTC 24
Finished Aug 25 07:34:21 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297563497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3297563497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.1479817579
Short name T582
Test name
Test status
Simulation time 116544019 ps
CPU time 3.71 seconds
Started Aug 25 07:34:12 AM UTC 24
Finished Aug 25 07:34:17 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479817579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1479817579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all_with_rand_reset.2800912385
Short name T187
Test name
Test status
Simulation time 524996087 ps
CPU time 14.24 seconds
Started Aug 25 07:34:18 AM UTC 24
Finished Aug 25 07:34:34 AM UTC 24
Peak memory 230696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2800912385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymg
r_stress_all_with_rand_reset.2800912385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.344568769
Short name T260
Test name
Test status
Simulation time 57558233 ps
CPU time 5.08 seconds
Started Aug 25 07:34:15 AM UTC 24
Finished Aug 25 07:34:22 AM UTC 24
Peak memory 230576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344568769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.344568769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.2804515082
Short name T601
Test name
Test status
Simulation time 30058433 ps
CPU time 1.37 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:34 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804515082 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2804515082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.128477107
Short name T431
Test name
Test status
Simulation time 36895772 ps
CPU time 4.58 seconds
Started Aug 25 07:34:22 AM UTC 24
Finished Aug 25 07:34:28 AM UTC 24
Peak memory 224024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128477107 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.128477107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.2731098608
Short name T595
Test name
Test status
Simulation time 747557962 ps
CPU time 4.44 seconds
Started Aug 25 07:34:22 AM UTC 24
Finished Aug 25 07:34:27 AM UTC 24
Peak memory 218084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731098608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2731098608
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.2941711996
Short name T598
Test name
Test status
Simulation time 318543605 ps
CPU time 5.33 seconds
Started Aug 25 07:34:23 AM UTC 24
Finished Aug 25 07:34:29 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941711996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2941711996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.227356968
Short name T57
Test name
Test status
Simulation time 175919381 ps
CPU time 3.88 seconds
Started Aug 25 07:34:24 AM UTC 24
Finished Aug 25 07:34:29 AM UTC 24
Peak memory 224300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227356968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.227356968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.564453362
Short name T231
Test name
Test status
Simulation time 128781154 ps
CPU time 8.43 seconds
Started Aug 25 07:34:23 AM UTC 24
Finished Aug 25 07:34:32 AM UTC 24
Peak memory 232160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564453362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.564453362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_random.747773733
Short name T593
Test name
Test status
Simulation time 59967965 ps
CPU time 3.16 seconds
Started Aug 25 07:34:22 AM UTC 24
Finished Aug 25 07:34:26 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747773733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.747773733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.962259222
Short name T395
Test name
Test status
Simulation time 207148678 ps
CPU time 5.41 seconds
Started Aug 25 07:34:19 AM UTC 24
Finished Aug 25 07:34:26 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962259222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.962259222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.2432616034
Short name T594
Test name
Test status
Simulation time 199919052 ps
CPU time 4.63 seconds
Started Aug 25 07:34:22 AM UTC 24
Finished Aug 25 07:34:27 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432616034 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2432616034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.2827383071
Short name T602
Test name
Test status
Simulation time 706107883 ps
CPU time 12.26 seconds
Started Aug 25 07:34:21 AM UTC 24
Finished Aug 25 07:34:35 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827383071 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2827383071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.764423278
Short name T596
Test name
Test status
Simulation time 470341683 ps
CPU time 5.44 seconds
Started Aug 25 07:34:22 AM UTC 24
Finished Aug 25 07:34:28 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764423278 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.764423278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.1292575379
Short name T600
Test name
Test status
Simulation time 22736960 ps
CPU time 2.3 seconds
Started Aug 25 07:34:30 AM UTC 24
Finished Aug 25 07:34:34 AM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292575379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1292575379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.1046565197
Short name T592
Test name
Test status
Simulation time 633689116 ps
CPU time 5.28 seconds
Started Aug 25 07:34:19 AM UTC 24
Finished Aug 25 07:34:26 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046565197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1046565197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.3838579772
Short name T201
Test name
Test status
Simulation time 2071381544 ps
CPU time 45.12 seconds
Started Aug 25 07:34:30 AM UTC 24
Finished Aug 25 07:35:17 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838579772 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3838579772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.2720902818
Short name T599
Test name
Test status
Simulation time 176215487 ps
CPU time 5.58 seconds
Started Aug 25 07:34:23 AM UTC 24
Finished Aug 25 07:34:30 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720902818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2720902818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.4116945934
Short name T610
Test name
Test status
Simulation time 22147727 ps
CPU time 1.2 seconds
Started Aug 25 07:34:39 AM UTC 24
Finished Aug 25 07:34:41 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116945934 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.4116945934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.1018631566
Short name T611
Test name
Test status
Simulation time 84995066 ps
CPU time 4.06 seconds
Started Aug 25 07:34:35 AM UTC 24
Finished Aug 25 07:34:41 AM UTC 24
Peak memory 231364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018631566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1018631566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.3935584419
Short name T603
Test name
Test status
Simulation time 190193490 ps
CPU time 3.64 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:37 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935584419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3935584419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.3781322768
Short name T609
Test name
Test status
Simulation time 74470349 ps
CPU time 4.84 seconds
Started Aug 25 07:34:34 AM UTC 24
Finished Aug 25 07:34:41 AM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781322768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3781322768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.725464545
Short name T615
Test name
Test status
Simulation time 128314960 ps
CPU time 6.44 seconds
Started Aug 25 07:34:35 AM UTC 24
Finished Aug 25 07:34:44 AM UTC 24
Peak memory 224300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725464545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.725464545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.2036129418
Short name T144
Test name
Test status
Simulation time 45572613 ps
CPU time 4.27 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:38 AM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036129418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2036129418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_random.525114319
Short name T286
Test name
Test status
Simulation time 73218350 ps
CPU time 4.77 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:38 AM UTC 24
Peak memory 216196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525114319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.525114319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.1173798356
Short name T612
Test name
Test status
Simulation time 164197363 ps
CPU time 8.81 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:42 AM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173798356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1173798356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.2226215709
Short name T604
Test name
Test status
Simulation time 313042498 ps
CPU time 5.03 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:38 AM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226215709 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2226215709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.2039296792
Short name T608
Test name
Test status
Simulation time 117547321 ps
CPU time 6.69 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:40 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039296792 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2039296792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.3529769505
Short name T607
Test name
Test status
Simulation time 725788114 ps
CPU time 5.72 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:39 AM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529769505 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3529769505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.1345225605
Short name T613
Test name
Test status
Simulation time 391785371 ps
CPU time 4.86 seconds
Started Aug 25 07:34:36 AM UTC 24
Finished Aug 25 07:34:43 AM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345225605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1345225605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.4077311928
Short name T605
Test name
Test status
Simulation time 278465244 ps
CPU time 5.73 seconds
Started Aug 25 07:34:32 AM UTC 24
Finished Aug 25 07:34:39 AM UTC 24
Peak memory 217932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077311928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.4077311928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.3702327257
Short name T606
Test name
Test status
Simulation time 145717154 ps
CPU time 4.06 seconds
Started Aug 25 07:34:33 AM UTC 24
Finished Aug 25 07:34:39 AM UTC 24
Peak memory 220360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702327257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3702327257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.1525099664
Short name T407
Test name
Test status
Simulation time 62392218 ps
CPU time 3.29 seconds
Started Aug 25 07:34:36 AM UTC 24
Finished Aug 25 07:34:41 AM UTC 24
Peak memory 219944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525099664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1525099664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.1715425287
Short name T620
Test name
Test status
Simulation time 37937174 ps
CPU time 1.21 seconds
Started Aug 25 07:34:46 AM UTC 24
Finished Aug 25 07:34:48 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715425287 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1715425287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.4000940439
Short name T430
Test name
Test status
Simulation time 195013714 ps
CPU time 13.95 seconds
Started Aug 25 07:34:42 AM UTC 24
Finished Aug 25 07:34:58 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000940439 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4000940439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.171473672
Short name T389
Test name
Test status
Simulation time 369214254 ps
CPU time 5 seconds
Started Aug 25 07:34:42 AM UTC 24
Finished Aug 25 07:34:49 AM UTC 24
Peak memory 218320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171473672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.171473672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.836433779
Short name T621
Test name
Test status
Simulation time 401489178 ps
CPU time 4.21 seconds
Started Aug 25 07:34:43 AM UTC 24
Finished Aug 25 07:34:50 AM UTC 24
Peak memory 226048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836433779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.836433779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.974557570
Short name T387
Test name
Test status
Simulation time 87750169 ps
CPU time 5.26 seconds
Started Aug 25 07:34:44 AM UTC 24
Finished Aug 25 07:34:51 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974557570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.974557570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.895081858
Short name T619
Test name
Test status
Simulation time 704609012 ps
CPU time 3.62 seconds
Started Aug 25 07:34:42 AM UTC 24
Finished Aug 25 07:34:48 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895081858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.895081858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_random.2604331649
Short name T626
Test name
Test status
Simulation time 575208689 ps
CPU time 12.33 seconds
Started Aug 25 07:34:41 AM UTC 24
Finished Aug 25 07:34:55 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604331649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2604331649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.3153080885
Short name T340
Test name
Test status
Simulation time 579892767 ps
CPU time 9.53 seconds
Started Aug 25 07:34:39 AM UTC 24
Finished Aug 25 07:34:50 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153080885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3153080885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.1752578112
Short name T617
Test name
Test status
Simulation time 246828066 ps
CPU time 3.09 seconds
Started Aug 25 07:34:40 AM UTC 24
Finished Aug 25 07:34:44 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752578112 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1752578112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.861883651
Short name T618
Test name
Test status
Simulation time 195957934 ps
CPU time 4.05 seconds
Started Aug 25 07:34:40 AM UTC 24
Finished Aug 25 07:34:45 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861883651 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.861883651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.4143697174
Short name T585
Test name
Test status
Simulation time 131668775 ps
CPU time 4.47 seconds
Started Aug 25 07:34:40 AM UTC 24
Finished Aug 25 07:34:46 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143697174 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4143697174
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.2584515815
Short name T624
Test name
Test status
Simulation time 315539057 ps
CPU time 5.33 seconds
Started Aug 25 07:34:44 AM UTC 24
Finished Aug 25 07:34:51 AM UTC 24
Peak memory 218008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584515815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2584515815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.232849037
Short name T616
Test name
Test status
Simulation time 63505841 ps
CPU time 4.24 seconds
Started Aug 25 07:34:39 AM UTC 24
Finished Aug 25 07:34:44 AM UTC 24
Peak memory 213720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232849037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.232849037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.1297059695
Short name T202
Test name
Test status
Simulation time 5331246123 ps
CPU time 37.26 seconds
Started Aug 25 07:34:45 AM UTC 24
Finished Aug 25 07:35:24 AM UTC 24
Peak memory 228452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297059695 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1297059695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.1137533696
Short name T625
Test name
Test status
Simulation time 228136094 ps
CPU time 10.44 seconds
Started Aug 25 07:34:42 AM UTC 24
Finished Aug 25 07:34:55 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137533696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1137533696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.1130654965
Short name T629
Test name
Test status
Simulation time 380116486 ps
CPU time 10.96 seconds
Started Aug 25 07:34:44 AM UTC 24
Finished Aug 25 07:34:56 AM UTC 24
Peak memory 217872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130654965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1130654965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.3450608759
Short name T634
Test name
Test status
Simulation time 20374448 ps
CPU time 1.21 seconds
Started Aug 25 07:34:57 AM UTC 24
Finished Aug 25 07:34:59 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450608759 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3450608759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.3563083901
Short name T258
Test name
Test status
Simulation time 34085986 ps
CPU time 3.31 seconds
Started Aug 25 07:34:52 AM UTC 24
Finished Aug 25 07:34:57 AM UTC 24
Peak memory 224716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563083901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3563083901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.2403263546
Short name T632
Test name
Test status
Simulation time 88159925 ps
CPU time 5.07 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:34:57 AM UTC 24
Peak memory 227748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403263546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2403263546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.132361421
Short name T633
Test name
Test status
Simulation time 307132872 ps
CPU time 4.88 seconds
Started Aug 25 07:34:52 AM UTC 24
Finished Aug 25 07:34:59 AM UTC 24
Peak memory 223972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132361421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.132361421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_random.294675527
Short name T628
Test name
Test status
Simulation time 142883835 ps
CPU time 3.25 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:34:55 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294675527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.294675527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.586310600
Short name T635
Test name
Test status
Simulation time 199976602 ps
CPU time 7.63 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:35:00 AM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586310600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.586310600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.1950689120
Short name T639
Test name
Test status
Simulation time 614777453 ps
CPU time 11.03 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:35:03 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950689120 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1950689120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.3697505737
Short name T627
Test name
Test status
Simulation time 34908101 ps
CPU time 3.45 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:34:55 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697505737 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3697505737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.3446689137
Short name T630
Test name
Test status
Simulation time 317236665 ps
CPU time 4.19 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:34:56 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446689137 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3446689137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.14772895
Short name T399
Test name
Test status
Simulation time 75338197 ps
CPU time 4.81 seconds
Started Aug 25 07:34:52 AM UTC 24
Finished Aug 25 07:34:59 AM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14772895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.14772895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.1984972808
Short name T623
Test name
Test status
Simulation time 158731322 ps
CPU time 3.31 seconds
Started Aug 25 07:34:46 AM UTC 24
Finished Aug 25 07:34:51 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984972808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1984972808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.2654831474
Short name T675
Test name
Test status
Simulation time 3843040819 ps
CPU time 32.76 seconds
Started Aug 25 07:34:57 AM UTC 24
Finished Aug 25 07:35:31 AM UTC 24
Peak memory 230236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654831474 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2654831474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.942401168
Short name T150
Test name
Test status
Simulation time 2212866978 ps
CPU time 31.99 seconds
Started Aug 25 07:34:57 AM UTC 24
Finished Aug 25 07:35:30 AM UTC 24
Peak memory 232368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=942401168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr
_stress_all_with_rand_reset.942401168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.1556912140
Short name T631
Test name
Test status
Simulation time 433208566 ps
CPU time 4.8 seconds
Started Aug 25 07:34:51 AM UTC 24
Finished Aug 25 07:34:57 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556912140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1556912140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.3710813658
Short name T636
Test name
Test status
Simulation time 158009357 ps
CPU time 2.78 seconds
Started Aug 25 07:34:55 AM UTC 24
Finished Aug 25 07:35:00 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710813658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3710813658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.1357867154
Short name T446
Test name
Test status
Simulation time 40863817 ps
CPU time 1.08 seconds
Started Aug 25 07:29:55 AM UTC 24
Finished Aug 25 07:29:57 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357867154 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1357867154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.755563620
Short name T105
Test name
Test status
Simulation time 120509734 ps
CPU time 3.68 seconds
Started Aug 25 07:29:44 AM UTC 24
Finished Aug 25 07:29:49 AM UTC 24
Peak memory 224060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755563620 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.755563620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.2655237304
Short name T131
Test name
Test status
Simulation time 62589796 ps
CPU time 4.27 seconds
Started Aug 25 07:29:45 AM UTC 24
Finished Aug 25 07:29:50 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655237304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2655237304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.2921127561
Short name T52
Test name
Test status
Simulation time 165878035 ps
CPU time 7.94 seconds
Started Aug 25 07:29:49 AM UTC 24
Finished Aug 25 07:29:58 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921127561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2921127561
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.3471293883
Short name T48
Test name
Test status
Simulation time 213876954 ps
CPU time 3.59 seconds
Started Aug 25 07:29:49 AM UTC 24
Finished Aug 25 07:29:54 AM UTC 24
Peak memory 224300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471293883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3471293883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.3503987917
Short name T130
Test name
Test status
Simulation time 94852256 ps
CPU time 6.36 seconds
Started Aug 25 07:29:49 AM UTC 24
Finished Aug 25 07:29:57 AM UTC 24
Peak memory 231980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503987917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3503987917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_random.1309775967
Short name T157
Test name
Test status
Simulation time 253194683 ps
CPU time 9.86 seconds
Started Aug 25 07:29:44 AM UTC 24
Finished Aug 25 07:29:55 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309775967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1309775967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.2553292341
Short name T42
Test name
Test status
Simulation time 1114484254 ps
CPU time 24.46 seconds
Started Aug 25 07:29:55 AM UTC 24
Finished Aug 25 07:30:21 AM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553292341 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2553292341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.3603744632
Short name T204
Test name
Test status
Simulation time 178188986 ps
CPU time 3.8 seconds
Started Aug 25 07:29:43 AM UTC 24
Finished Aug 25 07:29:48 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603744632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3603744632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.414289340
Short name T156
Test name
Test status
Simulation time 111874534 ps
CPU time 6.04 seconds
Started Aug 25 07:29:44 AM UTC 24
Finished Aug 25 07:29:51 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414289340 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.414289340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.2645667169
Short name T205
Test name
Test status
Simulation time 1013778592 ps
CPU time 4.46 seconds
Started Aug 25 07:29:43 AM UTC 24
Finished Aug 25 07:29:48 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645667169 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2645667169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.722628383
Short name T247
Test name
Test status
Simulation time 636496847 ps
CPU time 24.53 seconds
Started Aug 25 07:29:44 AM UTC 24
Finished Aug 25 07:30:10 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722628383 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.722628383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.1126293043
Short name T316
Test name
Test status
Simulation time 2102015287 ps
CPU time 24.24 seconds
Started Aug 25 07:29:51 AM UTC 24
Finished Aug 25 07:30:17 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126293043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1126293043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.1090207564
Short name T155
Test name
Test status
Simulation time 166619476 ps
CPU time 7.24 seconds
Started Aug 25 07:29:43 AM UTC 24
Finished Aug 25 07:29:51 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090207564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1090207564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.414550475
Short name T217
Test name
Test status
Simulation time 619146704 ps
CPU time 9.49 seconds
Started Aug 25 07:29:49 AM UTC 24
Finished Aug 25 07:30:00 AM UTC 24
Peak memory 223796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414550475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.414550475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.3977365969
Short name T61
Test name
Test status
Simulation time 31104030 ps
CPU time 2.61 seconds
Started Aug 25 07:29:51 AM UTC 24
Finished Aug 25 07:29:55 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977365969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3977365969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.2834157069
Short name T643
Test name
Test status
Simulation time 11039845 ps
CPU time 1.33 seconds
Started Aug 25 07:35:04 AM UTC 24
Finished Aug 25 07:35:07 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834157069 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2834157069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.1614823560
Short name T432
Test name
Test status
Simulation time 69182273 ps
CPU time 6.19 seconds
Started Aug 25 07:34:58 AM UTC 24
Finished Aug 25 07:35:06 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614823560 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1614823560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.2353333021
Short name T648
Test name
Test status
Simulation time 122007817 ps
CPU time 6.73 seconds
Started Aug 25 07:35:01 AM UTC 24
Finished Aug 25 07:35:09 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353333021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2353333021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.2690222492
Short name T655
Test name
Test status
Simulation time 2644431338 ps
CPU time 13.24 seconds
Started Aug 25 07:34:59 AM UTC 24
Finished Aug 25 07:35:14 AM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690222492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2690222492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.1591795875
Short name T53
Test name
Test status
Simulation time 1007567646 ps
CPU time 6.57 seconds
Started Aug 25 07:34:59 AM UTC 24
Finished Aug 25 07:35:07 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591795875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1591795875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.3154172071
Short name T646
Test name
Test status
Simulation time 192256230 ps
CPU time 5.36 seconds
Started Aug 25 07:35:01 AM UTC 24
Finished Aug 25 07:35:07 AM UTC 24
Peak memory 230884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154172071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3154172071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.1922678477
Short name T140
Test name
Test status
Simulation time 90849926 ps
CPU time 4.56 seconds
Started Aug 25 07:34:59 AM UTC 24
Finished Aug 25 07:35:05 AM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922678477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1922678477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_random.1045576915
Short name T642
Test name
Test status
Simulation time 148568007 ps
CPU time 5.53 seconds
Started Aug 25 07:34:58 AM UTC 24
Finished Aug 25 07:35:05 AM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045576915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1045576915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.1555049142
Short name T638
Test name
Test status
Simulation time 56936364 ps
CPU time 4.04 seconds
Started Aug 25 07:34:58 AM UTC 24
Finished Aug 25 07:35:03 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555049142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1555049142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.2657126749
Short name T641
Test name
Test status
Simulation time 92038559 ps
CPU time 5.09 seconds
Started Aug 25 07:34:58 AM UTC 24
Finished Aug 25 07:35:04 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657126749 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2657126749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.2746658900
Short name T637
Test name
Test status
Simulation time 267727457 ps
CPU time 3.67 seconds
Started Aug 25 07:34:58 AM UTC 24
Finished Aug 25 07:35:03 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746658900 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2746658900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.855627043
Short name T644
Test name
Test status
Simulation time 155982991 ps
CPU time 7.71 seconds
Started Aug 25 07:34:58 AM UTC 24
Finished Aug 25 07:35:07 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855627043 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.855627043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.478600335
Short name T645
Test name
Test status
Simulation time 108566747 ps
CPU time 5.15 seconds
Started Aug 25 07:35:01 AM UTC 24
Finished Aug 25 07:35:07 AM UTC 24
Peak memory 216268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478600335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.478600335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.3902232938
Short name T651
Test name
Test status
Simulation time 516787675 ps
CPU time 14.42 seconds
Started Aug 25 07:34:57 AM UTC 24
Finished Aug 25 07:35:13 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902232938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3902232938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.230608787
Short name T663
Test name
Test status
Simulation time 796079513 ps
CPU time 16.35 seconds
Started Aug 25 07:35:04 AM UTC 24
Finished Aug 25 07:35:22 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230608787 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.230608787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.3370857055
Short name T650
Test name
Test status
Simulation time 533664488 ps
CPU time 8.71 seconds
Started Aug 25 07:34:59 AM UTC 24
Finished Aug 25 07:35:10 AM UTC 24
Peak memory 226164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370857055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3370857055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.231662601
Short name T647
Test name
Test status
Simulation time 97765334 ps
CPU time 5.05 seconds
Started Aug 25 07:35:01 AM UTC 24
Finished Aug 25 07:35:07 AM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231662601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.231662601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.1646751877
Short name T656
Test name
Test status
Simulation time 16679953 ps
CPU time 1.15 seconds
Started Aug 25 07:35:13 AM UTC 24
Finished Aug 25 07:35:16 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646751877 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1646751877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.463123593
Short name T328
Test name
Test status
Simulation time 229466599 ps
CPU time 4.05 seconds
Started Aug 25 07:35:08 AM UTC 24
Finished Aug 25 07:35:14 AM UTC 24
Peak memory 232580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463123593 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.463123593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.1112569654
Short name T10
Test name
Test status
Simulation time 54095441 ps
CPU time 3.99 seconds
Started Aug 25 07:35:10 AM UTC 24
Finished Aug 25 07:35:15 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112569654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1112569654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.2451399378
Short name T660
Test name
Test status
Simulation time 1156002560 ps
CPU time 10.14 seconds
Started Aug 25 07:35:08 AM UTC 24
Finished Aug 25 07:35:20 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451399378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2451399378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.1108877386
Short name T305
Test name
Test status
Simulation time 127541594 ps
CPU time 3.18 seconds
Started Aug 25 07:35:09 AM UTC 24
Finished Aug 25 07:35:13 AM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108877386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1108877386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.837859595
Short name T370
Test name
Test status
Simulation time 82298239 ps
CPU time 4.28 seconds
Started Aug 25 07:35:10 AM UTC 24
Finished Aug 25 07:35:15 AM UTC 24
Peak memory 232452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837859595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.837859595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_random.1430104573
Short name T653
Test name
Test status
Simulation time 34268435 ps
CPU time 4.48 seconds
Started Aug 25 07:35:07 AM UTC 24
Finished Aug 25 07:35:13 AM UTC 24
Peak memory 230312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430104573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1430104573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.4212417256
Short name T375
Test name
Test status
Simulation time 939470622 ps
CPU time 16.57 seconds
Started Aug 25 07:35:05 AM UTC 24
Finished Aug 25 07:35:23 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212417256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4212417256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.2941655070
Short name T654
Test name
Test status
Simulation time 200086567 ps
CPU time 5.6 seconds
Started Aug 25 07:35:06 AM UTC 24
Finished Aug 25 07:35:13 AM UTC 24
Peak memory 215856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941655070 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2941655070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.3316223909
Short name T652
Test name
Test status
Simulation time 131428117 ps
CPU time 4.85 seconds
Started Aug 25 07:35:06 AM UTC 24
Finished Aug 25 07:35:13 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316223909 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3316223909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.133800035
Short name T657
Test name
Test status
Simulation time 627918370 ps
CPU time 10.18 seconds
Started Aug 25 07:35:06 AM UTC 24
Finished Aug 25 07:35:18 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133800035 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.133800035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.3811804520
Short name T413
Test name
Test status
Simulation time 106092558 ps
CPU time 4.51 seconds
Started Aug 25 07:35:10 AM UTC 24
Finished Aug 25 07:35:16 AM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811804520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3811804520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.3641645573
Short name T649
Test name
Test status
Simulation time 84794467 ps
CPU time 2.71 seconds
Started Aug 25 07:35:05 AM UTC 24
Finished Aug 25 07:35:09 AM UTC 24
Peak memory 217860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641645573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3641645573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.1003109894
Short name T726
Test name
Test status
Simulation time 1332724231 ps
CPU time 44.74 seconds
Started Aug 25 07:35:12 AM UTC 24
Finished Aug 25 07:35:59 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003109894 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1003109894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.2394218055
Short name T658
Test name
Test status
Simulation time 493806408 ps
CPU time 8.78 seconds
Started Aug 25 07:35:09 AM UTC 24
Finished Aug 25 07:35:19 AM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394218055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2394218055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.1288258610
Short name T181
Test name
Test status
Simulation time 213153780 ps
CPU time 3.44 seconds
Started Aug 25 07:35:11 AM UTC 24
Finished Aug 25 07:35:16 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288258610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1288258610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.1473865953
Short name T666
Test name
Test status
Simulation time 10536048 ps
CPU time 1.17 seconds
Started Aug 25 07:35:21 AM UTC 24
Finished Aug 25 07:35:24 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473865953 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1473865953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.3281484945
Short name T438
Test name
Test status
Simulation time 34040785 ps
CPU time 4.39 seconds
Started Aug 25 07:35:17 AM UTC 24
Finished Aug 25 07:35:22 AM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281484945 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3281484945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.4243251409
Short name T373
Test name
Test status
Simulation time 79479950 ps
CPU time 5.22 seconds
Started Aug 25 07:35:20 AM UTC 24
Finished Aug 25 07:35:26 AM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243251409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4243251409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.1602479912
Short name T664
Test name
Test status
Simulation time 387123725 ps
CPU time 5.61 seconds
Started Aug 25 07:35:17 AM UTC 24
Finished Aug 25 07:35:23 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602479912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1602479912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.3911169389
Short name T240
Test name
Test status
Simulation time 144311957 ps
CPU time 6.48 seconds
Started Aug 25 07:35:18 AM UTC 24
Finished Aug 25 07:35:26 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911169389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3911169389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.640301563
Short name T667
Test name
Test status
Simulation time 177310766 ps
CPU time 5.76 seconds
Started Aug 25 07:35:17 AM UTC 24
Finished Aug 25 07:35:24 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640301563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.640301563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_random.267644418
Short name T665
Test name
Test status
Simulation time 179371506 ps
CPU time 5.84 seconds
Started Aug 25 07:35:17 AM UTC 24
Finished Aug 25 07:35:24 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267644418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.267644418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.3409228581
Short name T659
Test name
Test status
Simulation time 205470482 ps
CPU time 3.77 seconds
Started Aug 25 07:35:14 AM UTC 24
Finished Aug 25 07:35:19 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409228581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3409228581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.1516326614
Short name T661
Test name
Test status
Simulation time 47004677 ps
CPU time 3.53 seconds
Started Aug 25 07:35:15 AM UTC 24
Finished Aug 25 07:35:20 AM UTC 24
Peak memory 218312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516326614 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1516326614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.2094712405
Short name T755
Test name
Test status
Simulation time 2222235159 ps
CPU time 64.65 seconds
Started Aug 25 07:35:14 AM UTC 24
Finished Aug 25 07:36:21 AM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094712405 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2094712405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.3962488920
Short name T662
Test name
Test status
Simulation time 58672236 ps
CPU time 4.16 seconds
Started Aug 25 07:35:16 AM UTC 24
Finished Aug 25 07:35:21 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962488920 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3962488920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.1740686777
Short name T669
Test name
Test status
Simulation time 210506138 ps
CPU time 6.08 seconds
Started Aug 25 07:35:20 AM UTC 24
Finished Aug 25 07:35:28 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740686777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1740686777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.2081183905
Short name T668
Test name
Test status
Simulation time 2384843467 ps
CPU time 8.29 seconds
Started Aug 25 07:35:14 AM UTC 24
Finished Aug 25 07:35:24 AM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081183905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2081183905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1856152959
Short name T671
Test name
Test status
Simulation time 1241923820 ps
CPU time 11.67 seconds
Started Aug 25 07:35:17 AM UTC 24
Finished Aug 25 07:35:30 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856152959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1856152959
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.1921953371
Short name T175
Test name
Test status
Simulation time 105041620 ps
CPU time 5.51 seconds
Started Aug 25 07:35:20 AM UTC 24
Finished Aug 25 07:35:27 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921953371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1921953371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.848621326
Short name T677
Test name
Test status
Simulation time 66369268 ps
CPU time 1.18 seconds
Started Aug 25 07:35:30 AM UTC 24
Finished Aug 25 07:35:32 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848621326 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.848621326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.1133317997
Short name T439
Test name
Test status
Simulation time 39603117 ps
CPU time 3.9 seconds
Started Aug 25 07:35:25 AM UTC 24
Finished Aug 25 07:35:30 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133317997 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1133317997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.2471116625
Short name T39
Test name
Test status
Simulation time 461425640 ps
CPU time 11.49 seconds
Started Aug 25 07:35:28 AM UTC 24
Finished Aug 25 07:35:41 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471116625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2471116625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.2854195286
Short name T682
Test name
Test status
Simulation time 389771461 ps
CPU time 6.66 seconds
Started Aug 25 07:35:27 AM UTC 24
Finished Aug 25 07:35:35 AM UTC 24
Peak memory 231292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854195286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2854195286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.2738918851
Short name T681
Test name
Test status
Simulation time 242244232 ps
CPU time 3.55 seconds
Started Aug 25 07:35:28 AM UTC 24
Finished Aug 25 07:35:33 AM UTC 24
Peak memory 230504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738918851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2738918851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.3070668043
Short name T679
Test name
Test status
Simulation time 125764229 ps
CPU time 5.89 seconds
Started Aug 25 07:35:25 AM UTC 24
Finished Aug 25 07:35:32 AM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070668043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3070668043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_random.1603544466
Short name T676
Test name
Test status
Simulation time 154360057 ps
CPU time 5.5 seconds
Started Aug 25 07:35:25 AM UTC 24
Finished Aug 25 07:35:32 AM UTC 24
Peak memory 228492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603544466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1603544466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.643284425
Short name T335
Test name
Test status
Simulation time 216818028 ps
CPU time 4.37 seconds
Started Aug 25 07:35:24 AM UTC 24
Finished Aug 25 07:35:29 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643284425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.643284425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.2000960191
Short name T700
Test name
Test status
Simulation time 416482163 ps
CPU time 17.56 seconds
Started Aug 25 07:35:25 AM UTC 24
Finished Aug 25 07:35:44 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000960191 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2000960191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.39980876
Short name T673
Test name
Test status
Simulation time 313602591 ps
CPU time 4.16 seconds
Started Aug 25 07:35:25 AM UTC 24
Finished Aug 25 07:35:30 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39980876 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.39980876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.1224416916
Short name T672
Test name
Test status
Simulation time 199602876 ps
CPU time 3.91 seconds
Started Aug 25 07:35:25 AM UTC 24
Finished Aug 25 07:35:30 AM UTC 24
Peak memory 218308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224416916 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1224416916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.2025656528
Short name T678
Test name
Test status
Simulation time 36474826 ps
CPU time 2.47 seconds
Started Aug 25 07:35:28 AM UTC 24
Finished Aug 25 07:35:32 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025656528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2025656528
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.802795514
Short name T670
Test name
Test status
Simulation time 858672717 ps
CPU time 5.51 seconds
Started Aug 25 07:35:23 AM UTC 24
Finished Aug 25 07:35:29 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802795514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.802795514
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.4256843708
Short name T697
Test name
Test status
Simulation time 234597258 ps
CPU time 12.47 seconds
Started Aug 25 07:35:30 AM UTC 24
Finished Aug 25 07:35:44 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256843708 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4256843708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.317544128
Short name T394
Test name
Test status
Simulation time 1461852433 ps
CPU time 9.34 seconds
Started Aug 25 07:35:26 AM UTC 24
Finished Aug 25 07:35:37 AM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317544128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.317544128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.2649584091
Short name T680
Test name
Test status
Simulation time 65620269 ps
CPU time 2.99 seconds
Started Aug 25 07:35:29 AM UTC 24
Finished Aug 25 07:35:33 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649584091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2649584091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.2917013544
Short name T690
Test name
Test status
Simulation time 63615558 ps
CPU time 1.39 seconds
Started Aug 25 07:35:36 AM UTC 24
Finished Aug 25 07:35:39 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917013544 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2917013544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.807633173
Short name T702
Test name
Test status
Simulation time 763593403 ps
CPU time 10.96 seconds
Started Aug 25 07:35:34 AM UTC 24
Finished Aug 25 07:35:46 AM UTC 24
Peak memory 230956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807633173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.807633173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.2519711810
Short name T151
Test name
Test status
Simulation time 389930958 ps
CPU time 4.04 seconds
Started Aug 25 07:35:32 AM UTC 24
Finished Aug 25 07:35:38 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519711810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2519711810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.2361175714
Short name T693
Test name
Test status
Simulation time 337989922 ps
CPU time 5.29 seconds
Started Aug 25 07:35:33 AM UTC 24
Finished Aug 25 07:35:39 AM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361175714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2361175714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.2042371953
Short name T388
Test name
Test status
Simulation time 64159932 ps
CPU time 4.67 seconds
Started Aug 25 07:35:34 AM UTC 24
Finished Aug 25 07:35:40 AM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042371953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2042371953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.3601059324
Short name T692
Test name
Test status
Simulation time 60603673 ps
CPU time 5.38 seconds
Started Aug 25 07:35:32 AM UTC 24
Finished Aug 25 07:35:39 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601059324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3601059324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_random.4145851996
Short name T713
Test name
Test status
Simulation time 4942300311 ps
CPU time 19.76 seconds
Started Aug 25 07:35:31 AM UTC 24
Finished Aug 25 07:35:52 AM UTC 24
Peak memory 215976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145851996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4145851996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.2209351194
Short name T687
Test name
Test status
Simulation time 117232618 ps
CPU time 4.73 seconds
Started Aug 25 07:35:31 AM UTC 24
Finished Aug 25 07:35:37 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209351194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2209351194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.3168570446
Short name T694
Test name
Test status
Simulation time 138749168 ps
CPU time 7.26 seconds
Started Aug 25 07:35:31 AM UTC 24
Finished Aug 25 07:35:40 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168570446 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3168570446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.2106200648
Short name T686
Test name
Test status
Simulation time 58288805 ps
CPU time 4.51 seconds
Started Aug 25 07:35:31 AM UTC 24
Finished Aug 25 07:35:37 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106200648 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2106200648
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.2730548370
Short name T683
Test name
Test status
Simulation time 24523784 ps
CPU time 2.74 seconds
Started Aug 25 07:35:31 AM UTC 24
Finished Aug 25 07:35:35 AM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730548370 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2730548370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.2036165991
Short name T689
Test name
Test status
Simulation time 165012400 ps
CPU time 3.2 seconds
Started Aug 25 07:35:34 AM UTC 24
Finished Aug 25 07:35:38 AM UTC 24
Peak memory 218088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036165991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2036165991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.2075726128
Short name T688
Test name
Test status
Simulation time 758429473 ps
CPU time 4.85 seconds
Started Aug 25 07:35:31 AM UTC 24
Finished Aug 25 07:35:37 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075726128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2075726128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.603758905
Short name T695
Test name
Test status
Simulation time 93809395 ps
CPU time 6.07 seconds
Started Aug 25 07:35:33 AM UTC 24
Finished Aug 25 07:35:40 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603758905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.603758905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.4210525079
Short name T691
Test name
Test status
Simulation time 201644031 ps
CPU time 3.88 seconds
Started Aug 25 07:35:34 AM UTC 24
Finished Aug 25 07:35:39 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210525079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4210525079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.1166714603
Short name T704
Test name
Test status
Simulation time 72448147 ps
CPU time 1.42 seconds
Started Aug 25 07:35:44 AM UTC 24
Finished Aug 25 07:35:47 AM UTC 24
Peak memory 213624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166714603 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1166714603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.3638098539
Short name T699
Test name
Test status
Simulation time 31364896 ps
CPU time 2.91 seconds
Started Aug 25 07:35:40 AM UTC 24
Finished Aug 25 07:35:44 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638098539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3638098539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.2436027848
Short name T707
Test name
Test status
Simulation time 180640056 ps
CPU time 6.26 seconds
Started Aug 25 07:35:40 AM UTC 24
Finished Aug 25 07:35:47 AM UTC 24
Peak memory 232216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436027848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2436027848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.1521342246
Short name T141
Test name
Test status
Simulation time 301759196 ps
CPU time 3.47 seconds
Started Aug 25 07:35:40 AM UTC 24
Finished Aug 25 07:35:44 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521342246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1521342246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_random.3555362596
Short name T705
Test name
Test status
Simulation time 674482869 ps
CPU time 7.03 seconds
Started Aug 25 07:35:38 AM UTC 24
Finished Aug 25 07:35:47 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555362596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3555362596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.2813813217
Short name T696
Test name
Test status
Simulation time 283075885 ps
CPU time 3.58 seconds
Started Aug 25 07:35:37 AM UTC 24
Finished Aug 25 07:35:42 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813813217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2813813217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.3244674618
Short name T724
Test name
Test status
Simulation time 5649288221 ps
CPU time 18.3 seconds
Started Aug 25 07:35:37 AM UTC 24
Finished Aug 25 07:35:57 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244674618 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3244674618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.2362133254
Short name T714
Test name
Test status
Simulation time 2022893522 ps
CPU time 13.91 seconds
Started Aug 25 07:35:37 AM UTC 24
Finished Aug 25 07:35:52 AM UTC 24
Peak memory 217900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362133254 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2362133254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.2447585146
Short name T823
Test name
Test status
Simulation time 17658886019 ps
CPU time 80.2 seconds
Started Aug 25 07:35:38 AM UTC 24
Finished Aug 25 07:37:01 AM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447585146 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2447585146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.1177872913
Short name T701
Test name
Test status
Simulation time 142034221 ps
CPU time 2.74 seconds
Started Aug 25 07:35:41 AM UTC 24
Finished Aug 25 07:35:45 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177872913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1177872913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.3393277326
Short name T698
Test name
Test status
Simulation time 157816878 ps
CPU time 6.43 seconds
Started Aug 25 07:35:36 AM UTC 24
Finished Aug 25 07:35:44 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393277326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3393277326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.3117912262
Short name T706
Test name
Test status
Simulation time 492005927 ps
CPU time 6.31 seconds
Started Aug 25 07:35:40 AM UTC 24
Finished Aug 25 07:35:47 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117912262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3117912262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.3920150249
Short name T709
Test name
Test status
Simulation time 890920115 ps
CPU time 6.67 seconds
Started Aug 25 07:35:41 AM UTC 24
Finished Aug 25 07:35:49 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920150249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3920150249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2503049884
Short name T719
Test name
Test status
Simulation time 29975965 ps
CPU time 1.02 seconds
Started Aug 25 07:35:51 AM UTC 24
Finished Aug 25 07:35:54 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503049884 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2503049884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.2780934678
Short name T428
Test name
Test status
Simulation time 320753750 ps
CPU time 20.69 seconds
Started Aug 25 07:35:47 AM UTC 24
Finished Aug 25 07:36:09 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780934678 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2780934678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.432658416
Short name T725
Test name
Test status
Simulation time 349488526 ps
CPU time 10.43 seconds
Started Aug 25 07:35:47 AM UTC 24
Finished Aug 25 07:35:58 AM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432658416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.432658416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.2192002936
Short name T341
Test name
Test status
Simulation time 352930920 ps
CPU time 5.97 seconds
Started Aug 25 07:35:48 AM UTC 24
Finished Aug 25 07:35:55 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192002936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2192002936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.1666020799
Short name T405
Test name
Test status
Simulation time 289347521 ps
CPU time 4.69 seconds
Started Aug 25 07:35:48 AM UTC 24
Finished Aug 25 07:35:54 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666020799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1666020799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.1326742163
Short name T715
Test name
Test status
Simulation time 87912908 ps
CPU time 3.93 seconds
Started Aug 25 07:35:48 AM UTC 24
Finished Aug 25 07:35:53 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326742163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1326742163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_random.373125492
Short name T718
Test name
Test status
Simulation time 1548653205 ps
CPU time 5.57 seconds
Started Aug 25 07:35:47 AM UTC 24
Finished Aug 25 07:35:53 AM UTC 24
Peak memory 226028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373125492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.373125492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.4270851820
Short name T711
Test name
Test status
Simulation time 299488507 ps
CPU time 4.75 seconds
Started Aug 25 07:35:44 AM UTC 24
Finished Aug 25 07:35:50 AM UTC 24
Peak memory 218248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270851820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4270851820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.2472367629
Short name T717
Test name
Test status
Simulation time 584466305 ps
CPU time 6.61 seconds
Started Aug 25 07:35:46 AM UTC 24
Finished Aug 25 07:35:53 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472367629 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2472367629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.743321946
Short name T710
Test name
Test status
Simulation time 62273043 ps
CPU time 3.34 seconds
Started Aug 25 07:35:44 AM UTC 24
Finished Aug 25 07:35:49 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743321946 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.743321946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.1388346289
Short name T712
Test name
Test status
Simulation time 286848177 ps
CPU time 3.88 seconds
Started Aug 25 07:35:46 AM UTC 24
Finished Aug 25 07:35:51 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388346289 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1388346289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.2988118015
Short name T722
Test name
Test status
Simulation time 80618128 ps
CPU time 4.99 seconds
Started Aug 25 07:35:49 AM UTC 24
Finished Aug 25 07:35:55 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988118015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2988118015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.1494086705
Short name T708
Test name
Test status
Simulation time 133898290 ps
CPU time 2.79 seconds
Started Aug 25 07:35:44 AM UTC 24
Finished Aug 25 07:35:48 AM UTC 24
Peak memory 215992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494086705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1494086705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.2261020851
Short name T780
Test name
Test status
Simulation time 1323970341 ps
CPU time 46.13 seconds
Started Aug 25 07:35:50 AM UTC 24
Finished Aug 25 07:36:38 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261020851 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2261020851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.3737554483
Short name T720
Test name
Test status
Simulation time 347704309 ps
CPU time 5.55 seconds
Started Aug 25 07:35:48 AM UTC 24
Finished Aug 25 07:35:55 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737554483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3737554483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.309058110
Short name T716
Test name
Test status
Simulation time 90257766 ps
CPU time 2.77 seconds
Started Aug 25 07:35:49 AM UTC 24
Finished Aug 25 07:35:53 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309058110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.309058110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.365032233
Short name T685
Test name
Test status
Simulation time 48595429 ps
CPU time 1.12 seconds
Started Aug 25 07:36:00 AM UTC 24
Finished Aug 25 07:36:02 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365032233 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.365032233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.1119498566
Short name T426
Test name
Test status
Simulation time 112714778 ps
CPU time 8.85 seconds
Started Aug 25 07:35:55 AM UTC 24
Finished Aug 25 07:36:05 AM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119498566 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1119498566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.1880222675
Short name T729
Test name
Test status
Simulation time 159106642 ps
CPU time 4.68 seconds
Started Aug 25 07:35:56 AM UTC 24
Finished Aug 25 07:36:02 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880222675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1880222675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.2837296104
Short name T728
Test name
Test status
Simulation time 87210462 ps
CPU time 4.11 seconds
Started Aug 25 07:35:55 AM UTC 24
Finished Aug 25 07:36:00 AM UTC 24
Peak memory 230500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837296104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2837296104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.3881144118
Short name T55
Test name
Test status
Simulation time 354839485 ps
CPU time 5.44 seconds
Started Aug 25 07:35:56 AM UTC 24
Finished Aug 25 07:36:03 AM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881144118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3881144118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.4009926582
Short name T731
Test name
Test status
Simulation time 109851406 ps
CPU time 6.12 seconds
Started Aug 25 07:35:56 AM UTC 24
Finished Aug 25 07:36:03 AM UTC 24
Peak memory 232420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009926582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4009926582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.2985578534
Short name T723
Test name
Test status
Simulation time 151940087 ps
CPU time 5.66 seconds
Started Aug 25 07:35:55 AM UTC 24
Finished Aug 25 07:36:02 AM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985578534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2985578534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_random.2014918256
Short name T732
Test name
Test status
Simulation time 162262726 ps
CPU time 9.32 seconds
Started Aug 25 07:35:54 AM UTC 24
Finished Aug 25 07:36:04 AM UTC 24
Peak memory 218252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014918256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2014918256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.788425183
Short name T775
Test name
Test status
Simulation time 2159412706 ps
CPU time 39.99 seconds
Started Aug 25 07:35:54 AM UTC 24
Finished Aug 25 07:36:35 AM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788425183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.788425183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.1932088214
Short name T703
Test name
Test status
Simulation time 987917712 ps
CPU time 7.05 seconds
Started Aug 25 07:35:54 AM UTC 24
Finished Aug 25 07:36:02 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932088214 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1932088214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.1903484279
Short name T727
Test name
Test status
Simulation time 103976694 ps
CPU time 4.19 seconds
Started Aug 25 07:35:54 AM UTC 24
Finished Aug 25 07:35:59 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903484279 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1903484279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.533809346
Short name T758
Test name
Test status
Simulation time 802063519 ps
CPU time 28.7 seconds
Started Aug 25 07:35:54 AM UTC 24
Finished Aug 25 07:36:24 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533809346 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.533809346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1492153516
Short name T730
Test name
Test status
Simulation time 428683346 ps
CPU time 5.07 seconds
Started Aug 25 07:35:56 AM UTC 24
Finished Aug 25 07:36:03 AM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492153516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1492153516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.410723478
Short name T721
Test name
Test status
Simulation time 59263146 ps
CPU time 2.57 seconds
Started Aug 25 07:35:51 AM UTC 24
Finished Aug 25 07:35:55 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410723478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.410723478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.2810392938
Short name T785
Test name
Test status
Simulation time 1137620450 ps
CPU time 40.12 seconds
Started Aug 25 07:35:57 AM UTC 24
Finished Aug 25 07:36:39 AM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810392938 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2810392938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.1119921459
Short name T272
Test name
Test status
Simulation time 5694474337 ps
CPU time 36.02 seconds
Started Aug 25 07:35:58 AM UTC 24
Finished Aug 25 07:36:35 AM UTC 24
Peak memory 232700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1119921459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg
r_stress_all_with_rand_reset.1119921459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.2908276599
Short name T674
Test name
Test status
Simulation time 230499988 ps
CPU time 4.71 seconds
Started Aug 25 07:35:55 AM UTC 24
Finished Aug 25 07:36:01 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908276599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2908276599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.2470968429
Short name T409
Test name
Test status
Simulation time 131407829 ps
CPU time 2.81 seconds
Started Aug 25 07:35:56 AM UTC 24
Finished Aug 25 07:36:00 AM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470968429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2470968429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.1056803103
Short name T741
Test name
Test status
Simulation time 10983108 ps
CPU time 1.06 seconds
Started Aug 25 07:36:09 AM UTC 24
Finished Aug 25 07:36:11 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056803103 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1056803103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.551479207
Short name T443
Test name
Test status
Simulation time 50194390 ps
CPU time 5.22 seconds
Started Aug 25 07:36:03 AM UTC 24
Finished Aug 25 07:36:09 AM UTC 24
Peak memory 224024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551479207 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.551479207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.1437496192
Short name T764
Test name
Test status
Simulation time 1877835115 ps
CPU time 20.68 seconds
Started Aug 25 07:36:05 AM UTC 24
Finished Aug 25 07:36:28 AM UTC 24
Peak memory 232596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437496192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1437496192
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.608909801
Short name T738
Test name
Test status
Simulation time 290866171 ps
CPU time 3.53 seconds
Started Aug 25 07:36:03 AM UTC 24
Finished Aug 25 07:36:08 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608909801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.608909801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.718555801
Short name T743
Test name
Test status
Simulation time 345553043 ps
CPU time 6.36 seconds
Started Aug 25 07:36:04 AM UTC 24
Finished Aug 25 07:36:12 AM UTC 24
Peak memory 230672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718555801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.718555801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.1685860997
Short name T306
Test name
Test status
Simulation time 82690346 ps
CPU time 2.44 seconds
Started Aug 25 07:36:04 AM UTC 24
Finished Aug 25 07:36:08 AM UTC 24
Peak memory 224152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685860997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1685860997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.1662930034
Short name T229
Test name
Test status
Simulation time 329231859 ps
CPU time 5.66 seconds
Started Aug 25 07:36:03 AM UTC 24
Finished Aug 25 07:36:10 AM UTC 24
Peak memory 230492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662930034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1662930034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_random.1852874353
Short name T745
Test name
Test status
Simulation time 900603170 ps
CPU time 10.01 seconds
Started Aug 25 07:36:03 AM UTC 24
Finished Aug 25 07:36:14 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852874353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1852874353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.3273841953
Short name T733
Test name
Test status
Simulation time 182334527 ps
CPU time 3.67 seconds
Started Aug 25 07:36:00 AM UTC 24
Finished Aug 25 07:36:05 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273841953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3273841953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.3872606735
Short name T742
Test name
Test status
Simulation time 197737765 ps
CPU time 9.29 seconds
Started Aug 25 07:36:01 AM UTC 24
Finished Aug 25 07:36:11 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872606735 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3872606735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.2213609039
Short name T734
Test name
Test status
Simulation time 54520412 ps
CPU time 3.35 seconds
Started Aug 25 07:36:01 AM UTC 24
Finished Aug 25 07:36:05 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213609039 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2213609039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.2524360909
Short name T735
Test name
Test status
Simulation time 99010280 ps
CPU time 3.72 seconds
Started Aug 25 07:36:02 AM UTC 24
Finished Aug 25 07:36:07 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524360909 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2524360909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.3876968735
Short name T740
Test name
Test status
Simulation time 59370670 ps
CPU time 4.25 seconds
Started Aug 25 07:36:06 AM UTC 24
Finished Aug 25 07:36:11 AM UTC 24
Peak memory 218236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876968735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3876968735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.1256856036
Short name T736
Test name
Test status
Simulation time 332877237 ps
CPU time 6.73 seconds
Started Aug 25 07:36:00 AM UTC 24
Finished Aug 25 07:36:08 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256856036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1256856036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.668806069
Short name T188
Test name
Test status
Simulation time 2162644105 ps
CPU time 30.17 seconds
Started Aug 25 07:36:08 AM UTC 24
Finished Aug 25 07:36:40 AM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=668806069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr
_stress_all_with_rand_reset.668806069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.3311873254
Short name T784
Test name
Test status
Simulation time 905592605 ps
CPU time 34.4 seconds
Started Aug 25 07:36:03 AM UTC 24
Finished Aug 25 07:36:39 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311873254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3311873254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.1918639156
Short name T739
Test name
Test status
Simulation time 209307279 ps
CPU time 3.3 seconds
Started Aug 25 07:36:06 AM UTC 24
Finished Aug 25 07:36:10 AM UTC 24
Peak memory 218180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918639156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1918639156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.1935500676
Short name T757
Test name
Test status
Simulation time 18763713 ps
CPU time 1.22 seconds
Started Aug 25 07:36:19 AM UTC 24
Finished Aug 25 07:36:22 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935500676 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1935500676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.4041283489
Short name T425
Test name
Test status
Simulation time 62938078 ps
CPU time 6.37 seconds
Started Aug 25 07:36:11 AM UTC 24
Finished Aug 25 07:36:19 AM UTC 24
Peak memory 232288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041283489 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4041283489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.2237844914
Short name T128
Test name
Test status
Simulation time 103026748 ps
CPU time 3.66 seconds
Started Aug 25 07:36:15 AM UTC 24
Finished Aug 25 07:36:20 AM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237844914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2237844914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.226742417
Short name T752
Test name
Test status
Simulation time 647438439 ps
CPU time 5.87 seconds
Started Aug 25 07:36:12 AM UTC 24
Finished Aug 25 07:36:20 AM UTC 24
Peak memory 218192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226742417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.226742417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.4135161519
Short name T747
Test name
Test status
Simulation time 50942351 ps
CPU time 4.67 seconds
Started Aug 25 07:36:13 AM UTC 24
Finished Aug 25 07:36:18 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135161519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4135161519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.3439699743
Short name T746
Test name
Test status
Simulation time 377689260 ps
CPU time 3.04 seconds
Started Aug 25 07:36:14 AM UTC 24
Finished Aug 25 07:36:18 AM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439699743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3439699743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.3471782279
Short name T749
Test name
Test status
Simulation time 85882454 ps
CPU time 5.24 seconds
Started Aug 25 07:36:12 AM UTC 24
Finished Aug 25 07:36:19 AM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471782279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3471782279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_random.4130823886
Short name T751
Test name
Test status
Simulation time 105944108 ps
CPU time 6.72 seconds
Started Aug 25 07:36:11 AM UTC 24
Finished Aug 25 07:36:19 AM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130823886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4130823886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.2999929656
Short name T754
Test name
Test status
Simulation time 1036645263 ps
CPU time 9.31 seconds
Started Aug 25 07:36:09 AM UTC 24
Finished Aug 25 07:36:20 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999929656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2999929656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.1308905314
Short name T748
Test name
Test status
Simulation time 256697694 ps
CPU time 7.22 seconds
Started Aug 25 07:36:10 AM UTC 24
Finished Aug 25 07:36:19 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308905314 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1308905314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.3193946719
Short name T841
Test name
Test status
Simulation time 10170500828 ps
CPU time 61.19 seconds
Started Aug 25 07:36:09 AM UTC 24
Finished Aug 25 07:37:13 AM UTC 24
Peak memory 218080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193946719 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3193946719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.4033615488
Short name T750
Test name
Test status
Simulation time 186211918 ps
CPU time 7.62 seconds
Started Aug 25 07:36:10 AM UTC 24
Finished Aug 25 07:36:19 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033615488 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4033615488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.4125498384
Short name T774
Test name
Test status
Simulation time 566370941 ps
CPU time 17.16 seconds
Started Aug 25 07:36:15 AM UTC 24
Finished Aug 25 07:36:33 AM UTC 24
Peak memory 218344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125498384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4125498384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.3128401870
Short name T744
Test name
Test status
Simulation time 250132100 ps
CPU time 3.55 seconds
Started Aug 25 07:36:09 AM UTC 24
Finished Aug 25 07:36:14 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128401870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3128401870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.3522443809
Short name T873
Test name
Test status
Simulation time 14051324327 ps
CPU time 69.84 seconds
Started Aug 25 07:36:19 AM UTC 24
Finished Aug 25 07:37:31 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522443809 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3522443809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.966539124
Short name T153
Test name
Test status
Simulation time 78628212 ps
CPU time 7.43 seconds
Started Aug 25 07:36:19 AM UTC 24
Finished Aug 25 07:36:28 AM UTC 24
Peak memory 230388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=966539124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr
_stress_all_with_rand_reset.966539124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.3383885475
Short name T756
Test name
Test status
Simulation time 362600405 ps
CPU time 7.48 seconds
Started Aug 25 07:36:12 AM UTC 24
Finished Aug 25 07:36:21 AM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383885475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3383885475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.342849921
Short name T753
Test name
Test status
Simulation time 125381450 ps
CPU time 3.39 seconds
Started Aug 25 07:36:15 AM UTC 24
Finished Aug 25 07:36:20 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342849921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.342849921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.1516046045
Short name T448
Test name
Test status
Simulation time 50420095 ps
CPU time 1.09 seconds
Started Aug 25 07:30:09 AM UTC 24
Finished Aug 25 07:30:11 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516046045 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1516046045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.4287933887
Short name T122
Test name
Test status
Simulation time 112779365 ps
CPU time 6.25 seconds
Started Aug 25 07:30:02 AM UTC 24
Finished Aug 25 07:30:09 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287933887 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4287933887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.3316937040
Short name T132
Test name
Test status
Simulation time 46252347 ps
CPU time 3.07 seconds
Started Aug 25 07:30:02 AM UTC 24
Finished Aug 25 07:30:06 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316937040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3316937040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.3088666595
Short name T280
Test name
Test status
Simulation time 175084891 ps
CPU time 4.45 seconds
Started Aug 25 07:30:02 AM UTC 24
Finished Aug 25 07:30:08 AM UTC 24
Peak memory 216188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088666595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3088666595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.3545742777
Short name T106
Test name
Test status
Simulation time 139531024 ps
CPU time 6.89 seconds
Started Aug 25 07:30:02 AM UTC 24
Finished Aug 25 07:30:10 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545742777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3545742777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_random.1226970630
Short name T304
Test name
Test status
Simulation time 220909101 ps
CPU time 5.97 seconds
Started Aug 25 07:29:59 AM UTC 24
Finished Aug 25 07:30:06 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226970630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1226970630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.1011137628
Short name T71
Test name
Test status
Simulation time 1169840148 ps
CPU time 13.65 seconds
Started Aug 25 07:30:09 AM UTC 24
Finished Aug 25 07:30:24 AM UTC 24
Peak memory 252240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011137628 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1011137628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.2501059467
Short name T246
Test name
Test status
Simulation time 438206260 ps
CPU time 3.85 seconds
Started Aug 25 07:29:56 AM UTC 24
Finished Aug 25 07:30:01 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501059467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2501059467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.3308361460
Short name T282
Test name
Test status
Simulation time 443175478 ps
CPU time 8.17 seconds
Started Aug 25 07:29:58 AM UTC 24
Finished Aug 25 07:30:07 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308361460 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3308361460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.3594890727
Short name T326
Test name
Test status
Simulation time 816659086 ps
CPU time 29.44 seconds
Started Aug 25 07:29:58 AM UTC 24
Finished Aug 25 07:30:29 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594890727 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3594890727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.3775017513
Short name T267
Test name
Test status
Simulation time 132839856 ps
CPU time 5.18 seconds
Started Aug 25 07:29:58 AM UTC 24
Finished Aug 25 07:30:04 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775017513 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3775017513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.3326234836
Short name T435
Test name
Test status
Simulation time 158684605 ps
CPU time 4.21 seconds
Started Aug 25 07:30:06 AM UTC 24
Finished Aug 25 07:30:11 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326234836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3326234836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.2473512024
Short name T447
Test name
Test status
Simulation time 133687196 ps
CPU time 5.44 seconds
Started Aug 25 07:29:56 AM UTC 24
Finished Aug 25 07:30:02 AM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473512024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2473512024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.3574697004
Short name T265
Test name
Test status
Simulation time 81156015 ps
CPU time 5.45 seconds
Started Aug 25 07:30:02 AM UTC 24
Finished Aug 25 07:30:09 AM UTC 24
Peak memory 215856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574697004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3574697004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.1773663849
Short name T41
Test name
Test status
Simulation time 200569103 ps
CPU time 2.77 seconds
Started Aug 25 07:30:07 AM UTC 24
Finished Aug 25 07:30:11 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773663849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1773663849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.4228483039
Short name T769
Test name
Test status
Simulation time 73312663 ps
CPU time 1.53 seconds
Started Aug 25 07:36:27 AM UTC 24
Finished Aug 25 07:36:31 AM UTC 24
Peak memory 213724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228483039 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4228483039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.2757485499
Short name T444
Test name
Test status
Simulation time 717821474 ps
CPU time 14.32 seconds
Started Aug 25 07:36:21 AM UTC 24
Finished Aug 25 07:36:37 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757485499 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2757485499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.1520480860
Short name T842
Test name
Test status
Simulation time 2281987328 ps
CPU time 45.47 seconds
Started Aug 25 07:36:25 AM UTC 24
Finished Aug 25 07:37:13 AM UTC 24
Peak memory 224168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520480860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1520480860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.2989134359
Short name T777
Test name
Test status
Simulation time 363359830 ps
CPU time 13.99 seconds
Started Aug 25 07:36:21 AM UTC 24
Finished Aug 25 07:36:36 AM UTC 24
Peak memory 228268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989134359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2989134359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.1868058557
Short name T368
Test name
Test status
Simulation time 146307470 ps
CPU time 2.31 seconds
Started Aug 25 07:36:22 AM UTC 24
Finished Aug 25 07:36:25 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868058557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1868058557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.141018215
Short name T345
Test name
Test status
Simulation time 153178773 ps
CPU time 5.59 seconds
Started Aug 25 07:36:23 AM UTC 24
Finished Aug 25 07:36:30 AM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141018215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.141018215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.3856107636
Short name T765
Test name
Test status
Simulation time 105320828 ps
CPU time 6.73 seconds
Started Aug 25 07:36:21 AM UTC 24
Finished Aug 25 07:36:29 AM UTC 24
Peak memory 220380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856107636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3856107636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_random.421577126
Short name T759
Test name
Test status
Simulation time 36271706 ps
CPU time 3.75 seconds
Started Aug 25 07:36:21 AM UTC 24
Finished Aug 25 07:36:26 AM UTC 24
Peak memory 218252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421577126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.421577126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.1348211074
Short name T760
Test name
Test status
Simulation time 353444849 ps
CPU time 4.06 seconds
Started Aug 25 07:36:20 AM UTC 24
Finished Aug 25 07:36:26 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348211074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1348211074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.3811264158
Short name T763
Test name
Test status
Simulation time 118602036 ps
CPU time 4.86 seconds
Started Aug 25 07:36:21 AM UTC 24
Finished Aug 25 07:36:27 AM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811264158 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3811264158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.4109079608
Short name T761
Test name
Test status
Simulation time 39864493 ps
CPU time 4.24 seconds
Started Aug 25 07:36:20 AM UTC 24
Finished Aug 25 07:36:26 AM UTC 24
Peak memory 218304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109079608 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4109079608
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.1979328720
Short name T762
Test name
Test status
Simulation time 214447579 ps
CPU time 4.04 seconds
Started Aug 25 07:36:21 AM UTC 24
Finished Aug 25 07:36:26 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979328720 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1979328720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.3708943784
Short name T767
Test name
Test status
Simulation time 18320347 ps
CPU time 2.27 seconds
Started Aug 25 07:36:26 AM UTC 24
Finished Aug 25 07:36:30 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708943784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3708943784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.3825036211
Short name T770
Test name
Test status
Simulation time 1013305069 ps
CPU time 9.43 seconds
Started Aug 25 07:36:20 AM UTC 24
Finished Aug 25 07:36:31 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825036211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3825036211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.2429400182
Short name T357
Test name
Test status
Simulation time 2062012725 ps
CPU time 53.35 seconds
Started Aug 25 07:36:27 AM UTC 24
Finished Aug 25 07:37:23 AM UTC 24
Peak memory 230700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429400182 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2429400182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.2720280934
Short name T800
Test name
Test status
Simulation time 468889853 ps
CPU time 20.41 seconds
Started Aug 25 07:36:27 AM UTC 24
Finished Aug 25 07:36:50 AM UTC 24
Peak memory 232416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2720280934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg
r_stress_all_with_rand_reset.2720280934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.2233200746
Short name T771
Test name
Test status
Simulation time 491097590 ps
CPU time 10.24 seconds
Started Aug 25 07:36:22 AM UTC 24
Finished Aug 25 07:36:33 AM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233200746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2233200746
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.1900711984
Short name T768
Test name
Test status
Simulation time 30020078 ps
CPU time 2.55 seconds
Started Aug 25 07:36:26 AM UTC 24
Finished Aug 25 07:36:30 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900711984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1900711984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.4191818532
Short name T791
Test name
Test status
Simulation time 17205013 ps
CPU time 1.28 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:45 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191818532 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4191818532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.1381935755
Short name T437
Test name
Test status
Simulation time 1018765579 ps
CPU time 35.41 seconds
Started Aug 25 07:36:31 AM UTC 24
Finished Aug 25 07:37:08 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381935755 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1381935755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.127013423
Short name T787
Test name
Test status
Simulation time 436893513 ps
CPU time 4.28 seconds
Started Aug 25 07:36:34 AM UTC 24
Finished Aug 25 07:36:40 AM UTC 24
Peak memory 218036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127013423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.127013423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.979201414
Short name T778
Test name
Test status
Simulation time 82909990 ps
CPU time 4.07 seconds
Started Aug 25 07:36:31 AM UTC 24
Finished Aug 25 07:36:37 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979201414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.979201414
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.1319852544
Short name T783
Test name
Test status
Simulation time 172883098 ps
CPU time 3.41 seconds
Started Aug 25 07:36:34 AM UTC 24
Finished Aug 25 07:36:39 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319852544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1319852544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.3251500070
Short name T788
Test name
Test status
Simulation time 312266962 ps
CPU time 4.67 seconds
Started Aug 25 07:36:34 AM UTC 24
Finished Aug 25 07:36:41 AM UTC 24
Peak memory 230956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251500070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3251500070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.15498966
Short name T781
Test name
Test status
Simulation time 277454670 ps
CPU time 4.67 seconds
Started Aug 25 07:36:32 AM UTC 24
Finished Aug 25 07:36:38 AM UTC 24
Peak memory 230252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15498966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.15498966
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_random.780198845
Short name T779
Test name
Test status
Simulation time 61984983 ps
CPU time 4.3 seconds
Started Aug 25 07:36:31 AM UTC 24
Finished Aug 25 07:36:37 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780198845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.780198845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.1371892190
Short name T776
Test name
Test status
Simulation time 424510293 ps
CPU time 6.03 seconds
Started Aug 25 07:36:29 AM UTC 24
Finished Aug 25 07:36:36 AM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371892190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1371892190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.1765084829
Short name T773
Test name
Test status
Simulation time 42041684 ps
CPU time 2.54 seconds
Started Aug 25 07:36:30 AM UTC 24
Finished Aug 25 07:36:33 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765084829 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1765084829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.1680029054
Short name T772
Test name
Test status
Simulation time 182986756 ps
CPU time 3.37 seconds
Started Aug 25 07:36:29 AM UTC 24
Finished Aug 25 07:36:33 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680029054 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1680029054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.3066079233
Short name T789
Test name
Test status
Simulation time 1112263019 ps
CPU time 8.28 seconds
Started Aug 25 07:36:31 AM UTC 24
Finished Aug 25 07:36:41 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066079233 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3066079233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.1070878540
Short name T786
Test name
Test status
Simulation time 136061449 ps
CPU time 4.02 seconds
Started Aug 25 07:36:34 AM UTC 24
Finished Aug 25 07:36:40 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070878540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1070878540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.3749443172
Short name T782
Test name
Test status
Simulation time 249293921 ps
CPU time 8.09 seconds
Started Aug 25 07:36:28 AM UTC 24
Finished Aug 25 07:36:38 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749443172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3749443172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.1181340932
Short name T870
Test name
Test status
Simulation time 1147345103 ps
CPU time 47.72 seconds
Started Aug 25 07:36:41 AM UTC 24
Finished Aug 25 07:37:30 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181340932 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1181340932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.2753835325
Short name T790
Test name
Test status
Simulation time 126689743 ps
CPU time 7.9 seconds
Started Aug 25 07:36:32 AM UTC 24
Finished Aug 25 07:36:42 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753835325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2753835325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.3568474173
Short name T792
Test name
Test status
Simulation time 243887721 ps
CPU time 4.07 seconds
Started Aug 25 07:36:41 AM UTC 24
Finished Aug 25 07:36:46 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568474173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3568474173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.3274217678
Short name T802
Test name
Test status
Simulation time 11775888 ps
CPU time 1.26 seconds
Started Aug 25 07:36:47 AM UTC 24
Finished Aug 25 07:36:50 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274217678 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3274217678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.1971288495
Short name T445
Test name
Test status
Simulation time 271985839 ps
CPU time 9.55 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:54 AM UTC 24
Peak memory 225996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971288495 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1971288495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.764459493
Short name T798
Test name
Test status
Simulation time 474165821 ps
CPU time 4.82 seconds
Started Aug 25 07:36:43 AM UTC 24
Finished Aug 25 07:36:49 AM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764459493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.764459493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.2684500338
Short name T793
Test name
Test status
Simulation time 200834448 ps
CPU time 3.37 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:47 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684500338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2684500338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.3994257133
Short name T404
Test name
Test status
Simulation time 56838910 ps
CPU time 2.81 seconds
Started Aug 25 07:36:43 AM UTC 24
Finished Aug 25 07:36:47 AM UTC 24
Peak memory 224296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994257133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3994257133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.365094271
Short name T795
Test name
Test status
Simulation time 97696080 ps
CPU time 4 seconds
Started Aug 25 07:36:43 AM UTC 24
Finished Aug 25 07:36:48 AM UTC 24
Peak memory 230780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365094271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.365094271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.1394381678
Short name T801
Test name
Test status
Simulation time 117633088 ps
CPU time 5.78 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:50 AM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394381678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1394381678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_random.1370946942
Short name T803
Test name
Test status
Simulation time 271516235 ps
CPU time 8.29 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:52 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370946942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1370946942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.3196588239
Short name T737
Test name
Test status
Simulation time 96023528 ps
CPU time 3.18 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:47 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196588239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3196588239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.355822289
Short name T799
Test name
Test status
Simulation time 195090756 ps
CPU time 5.68 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:49 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355822289 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.355822289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.322957519
Short name T797
Test name
Test status
Simulation time 411040992 ps
CPU time 5.16 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:49 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322957519 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.322957519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.2366499158
Short name T808
Test name
Test status
Simulation time 247377964 ps
CPU time 10.57 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:54 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366499158 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2366499158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.977619276
Short name T794
Test name
Test status
Simulation time 389994371 ps
CPU time 3.86 seconds
Started Aug 25 07:36:42 AM UTC 24
Finished Aug 25 07:36:47 AM UTC 24
Peak memory 216072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977619276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.977619276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.3381027861
Short name T810
Test name
Test status
Simulation time 1719807677 ps
CPU time 11.04 seconds
Started Aug 25 07:36:43 AM UTC 24
Finished Aug 25 07:36:55 AM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381027861 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3381027861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.406429076
Short name T796
Test name
Test status
Simulation time 147918116 ps
CPU time 4.27 seconds
Started Aug 25 07:36:43 AM UTC 24
Finished Aug 25 07:36:48 AM UTC 24
Peak memory 230596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406429076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.406429076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.3041443495
Short name T811
Test name
Test status
Simulation time 439426475 ps
CPU time 11.14 seconds
Started Aug 25 07:36:43 AM UTC 24
Finished Aug 25 07:36:56 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041443495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3041443495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.908144025
Short name T818
Test name
Test status
Simulation time 12907967 ps
CPU time 1.42 seconds
Started Aug 25 07:36:55 AM UTC 24
Finished Aug 25 07:36:58 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908144025 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.908144025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.291878115
Short name T350
Test name
Test status
Simulation time 194311056 ps
CPU time 12.98 seconds
Started Aug 25 07:36:49 AM UTC 24
Finished Aug 25 07:37:05 AM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291878115 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.291878115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.3605493298
Short name T813
Test name
Test status
Simulation time 97733316 ps
CPU time 3.68 seconds
Started Aug 25 07:36:51 AM UTC 24
Finished Aug 25 07:36:56 AM UTC 24
Peak memory 218288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605493298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3605493298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.975628697
Short name T816
Test name
Test status
Simulation time 299850845 ps
CPU time 4.66 seconds
Started Aug 25 07:36:51 AM UTC 24
Finished Aug 25 07:36:57 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975628697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.975628697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.871558224
Short name T814
Test name
Test status
Simulation time 849454463 ps
CPU time 4.21 seconds
Started Aug 25 07:36:51 AM UTC 24
Finished Aug 25 07:36:57 AM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871558224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.871558224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1375278107
Short name T815
Test name
Test status
Simulation time 487506771 ps
CPU time 4.18 seconds
Started Aug 25 07:36:51 AM UTC 24
Finished Aug 25 07:36:57 AM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375278107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1375278107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.3254269906
Short name T376
Test name
Test status
Simulation time 205720063 ps
CPU time 5.37 seconds
Started Aug 25 07:36:51 AM UTC 24
Finished Aug 25 07:36:58 AM UTC 24
Peak memory 228132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254269906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3254269906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_random.4020841025
Short name T812
Test name
Test status
Simulation time 208502287 ps
CPU time 4.87 seconds
Started Aug 25 07:36:49 AM UTC 24
Finished Aug 25 07:36:56 AM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020841025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4020841025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.4136815813
Short name T806
Test name
Test status
Simulation time 81119405 ps
CPU time 3.68 seconds
Started Aug 25 07:36:48 AM UTC 24
Finished Aug 25 07:36:54 AM UTC 24
Peak memory 215600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136815813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4136815813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.1904936367
Short name T805
Test name
Test status
Simulation time 189226697 ps
CPU time 3.04 seconds
Started Aug 25 07:36:48 AM UTC 24
Finished Aug 25 07:36:53 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904936367 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1904936367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.3470098563
Short name T819
Test name
Test status
Simulation time 225056544 ps
CPU time 9.32 seconds
Started Aug 25 07:36:48 AM UTC 24
Finished Aug 25 07:37:00 AM UTC 24
Peak memory 216096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470098563 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3470098563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.995619980
Short name T826
Test name
Test status
Simulation time 718747698 ps
CPU time 11.28 seconds
Started Aug 25 07:36:49 AM UTC 24
Finished Aug 25 07:37:03 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995619980 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.995619980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.3912898889
Short name T817
Test name
Test status
Simulation time 49153135 ps
CPU time 2.87 seconds
Started Aug 25 07:36:53 AM UTC 24
Finished Aug 25 07:36:57 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912898889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3912898889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.3682489866
Short name T807
Test name
Test status
Simulation time 213012646 ps
CPU time 3.89 seconds
Started Aug 25 07:36:48 AM UTC 24
Finished Aug 25 07:36:54 AM UTC 24
Peak memory 215600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682489866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3682489866
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.1074945435
Short name T236
Test name
Test status
Simulation time 242091539 ps
CPU time 13.95 seconds
Started Aug 25 07:36:54 AM UTC 24
Finished Aug 25 07:37:09 AM UTC 24
Peak memory 230960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074945435 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1074945435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.1963060257
Short name T835
Test name
Test status
Simulation time 553948363 ps
CPU time 12.69 seconds
Started Aug 25 07:36:54 AM UTC 24
Finished Aug 25 07:37:08 AM UTC 24
Peak memory 232352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1963060257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymg
r_stress_all_with_rand_reset.1963060257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.3891905314
Short name T824
Test name
Test status
Simulation time 259768070 ps
CPU time 6.79 seconds
Started Aug 25 07:36:54 AM UTC 24
Finished Aug 25 07:37:02 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891905314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3891905314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.3550087508
Short name T830
Test name
Test status
Simulation time 38256071 ps
CPU time 1.37 seconds
Started Aug 25 07:37:02 AM UTC 24
Finished Aug 25 07:37:05 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550087508 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3550087508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.2361846967
Short name T429
Test name
Test status
Simulation time 175847401 ps
CPU time 14.52 seconds
Started Aug 25 07:36:58 AM UTC 24
Finished Aug 25 07:37:14 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361846967 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2361846967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.2894557652
Short name T184
Test name
Test status
Simulation time 310129156 ps
CPU time 4.39 seconds
Started Aug 25 07:36:59 AM UTC 24
Finished Aug 25 07:37:05 AM UTC 24
Peak memory 218244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894557652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2894557652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.3008648867
Short name T832
Test name
Test status
Simulation time 544086882 ps
CPU time 7.83 seconds
Started Aug 25 07:36:58 AM UTC 24
Finished Aug 25 07:37:07 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008648867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3008648867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.1512082546
Short name T828
Test name
Test status
Simulation time 179497229 ps
CPU time 5.32 seconds
Started Aug 25 07:36:58 AM UTC 24
Finished Aug 25 07:37:04 AM UTC 24
Peak memory 224180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512082546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1512082546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.378012040
Short name T831
Test name
Test status
Simulation time 177062102 ps
CPU time 5.06 seconds
Started Aug 25 07:36:59 AM UTC 24
Finished Aug 25 07:37:05 AM UTC 24
Peak memory 232200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378012040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.378012040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.895191979
Short name T827
Test name
Test status
Simulation time 305152748 ps
CPU time 5.29 seconds
Started Aug 25 07:36:58 AM UTC 24
Finished Aug 25 07:37:04 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895191979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.895191979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_random.1723460795
Short name T825
Test name
Test status
Simulation time 55039043 ps
CPU time 4.38 seconds
Started Aug 25 07:36:57 AM UTC 24
Finished Aug 25 07:37:02 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723460795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1723460795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.3133443972
Short name T820
Test name
Test status
Simulation time 60746332 ps
CPU time 3.44 seconds
Started Aug 25 07:36:55 AM UTC 24
Finished Aug 25 07:37:00 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133443972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3133443972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.3913357775
Short name T822
Test name
Test status
Simulation time 20628923 ps
CPU time 2.71 seconds
Started Aug 25 07:36:57 AM UTC 24
Finished Aug 25 07:37:00 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913357775 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3913357775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.162371209
Short name T836
Test name
Test status
Simulation time 973158939 ps
CPU time 11.86 seconds
Started Aug 25 07:36:56 AM UTC 24
Finished Aug 25 07:37:10 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162371209 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.162371209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.2970599227
Short name T892
Test name
Test status
Simulation time 3464499529 ps
CPU time 44.89 seconds
Started Aug 25 07:36:57 AM UTC 24
Finished Aug 25 07:37:43 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970599227 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2970599227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.524348683
Short name T829
Test name
Test status
Simulation time 109637554 ps
CPU time 3.49 seconds
Started Aug 25 07:37:00 AM UTC 24
Finished Aug 25 07:37:05 AM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524348683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.524348683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.2715999451
Short name T821
Test name
Test status
Simulation time 56380401 ps
CPU time 3.87 seconds
Started Aug 25 07:36:55 AM UTC 24
Finished Aug 25 07:37:00 AM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715999451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2715999451
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.3893578993
Short name T909
Test name
Test status
Simulation time 9869213051 ps
CPU time 230.22 seconds
Started Aug 25 07:37:01 AM UTC 24
Finished Aug 25 07:40:56 AM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893578993 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3893578993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.1857197010
Short name T857
Test name
Test status
Simulation time 656309079 ps
CPU time 22.3 seconds
Started Aug 25 07:36:58 AM UTC 24
Finished Aug 25 07:37:22 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857197010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1857197010
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.4220655774
Short name T206
Test name
Test status
Simulation time 2160389236 ps
CPU time 16.75 seconds
Started Aug 25 07:37:01 AM UTC 24
Finished Aug 25 07:37:19 AM UTC 24
Peak memory 220072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220655774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4220655774
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.2377195526
Short name T845
Test name
Test status
Simulation time 82192923 ps
CPU time 1.51 seconds
Started Aug 25 07:37:11 AM UTC 24
Finished Aug 25 07:37:13 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377195526 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2377195526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.955020891
Short name T837
Test name
Test status
Simulation time 147227347 ps
CPU time 2.88 seconds
Started Aug 25 07:37:06 AM UTC 24
Finished Aug 25 07:37:10 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955020891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.955020891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.4055470185
Short name T843
Test name
Test status
Simulation time 177386325 ps
CPU time 3.54 seconds
Started Aug 25 07:37:08 AM UTC 24
Finished Aug 25 07:37:13 AM UTC 24
Peak memory 228392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055470185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.4055470185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_random.1680662668
Short name T844
Test name
Test status
Simulation time 381530805 ps
CPU time 6.32 seconds
Started Aug 25 07:37:06 AM UTC 24
Finished Aug 25 07:37:13 AM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680662668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1680662668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.2800696246
Short name T833
Test name
Test status
Simulation time 22716442 ps
CPU time 2.24 seconds
Started Aug 25 07:37:04 AM UTC 24
Finished Aug 25 07:37:07 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800696246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2800696246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.1540540314
Short name T840
Test name
Test status
Simulation time 114489247 ps
CPU time 4.52 seconds
Started Aug 25 07:37:06 AM UTC 24
Finished Aug 25 07:37:11 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540540314 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1540540314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.1722068714
Short name T834
Test name
Test status
Simulation time 27046858 ps
CPU time 2.85 seconds
Started Aug 25 07:37:04 AM UTC 24
Finished Aug 25 07:37:08 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722068714 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1722068714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.88697852
Short name T838
Test name
Test status
Simulation time 183054243 ps
CPU time 3.32 seconds
Started Aug 25 07:37:06 AM UTC 24
Finished Aug 25 07:37:10 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88697852 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.88697852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.3513117346
Short name T846
Test name
Test status
Simulation time 38413352 ps
CPU time 2.91 seconds
Started Aug 25 07:37:09 AM UTC 24
Finished Aug 25 07:37:14 AM UTC 24
Peak memory 218120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513117346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3513117346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.2851402046
Short name T839
Test name
Test status
Simulation time 155508393 ps
CPU time 5.66 seconds
Started Aug 25 07:37:03 AM UTC 24
Finished Aug 25 07:37:10 AM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851402046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2851402046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.405503672
Short name T232
Test name
Test status
Simulation time 435289753 ps
CPU time 22.82 seconds
Started Aug 25 07:37:09 AM UTC 24
Finished Aug 25 07:37:34 AM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405503672 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.405503672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all_with_rand_reset.1321754967
Short name T285
Test name
Test status
Simulation time 297280803 ps
CPU time 26.27 seconds
Started Aug 25 07:37:11 AM UTC 24
Finished Aug 25 07:37:38 AM UTC 24
Peak memory 231168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1321754967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymg
r_stress_all_with_rand_reset.1321754967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.3427764275
Short name T859
Test name
Test status
Simulation time 1052322186 ps
CPU time 15.82 seconds
Started Aug 25 07:37:06 AM UTC 24
Finished Aug 25 07:37:23 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427764275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3427764275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.919443946
Short name T809
Test name
Test status
Simulation time 320990634 ps
CPU time 11.22 seconds
Started Aug 25 07:37:09 AM UTC 24
Finished Aug 25 07:37:22 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919443946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.919443946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.2287836737
Short name T852
Test name
Test status
Simulation time 54991743 ps
CPU time 1.19 seconds
Started Aug 25 07:37:17 AM UTC 24
Finished Aug 25 07:37:20 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287836737 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2287836737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.4279960114
Short name T860
Test name
Test status
Simulation time 135617443 ps
CPU time 10.44 seconds
Started Aug 25 07:37:14 AM UTC 24
Finished Aug 25 07:37:26 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279960114 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4279960114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.1457456881
Short name T851
Test name
Test status
Simulation time 83642089 ps
CPU time 2.7 seconds
Started Aug 25 07:37:14 AM UTC 24
Finished Aug 25 07:37:18 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457456881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1457456881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.2046072488
Short name T850
Test name
Test status
Simulation time 48146279 ps
CPU time 2.32 seconds
Started Aug 25 07:37:14 AM UTC 24
Finished Aug 25 07:37:18 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046072488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2046072488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.3611152269
Short name T856
Test name
Test status
Simulation time 171977611 ps
CPU time 5.25 seconds
Started Aug 25 07:37:14 AM UTC 24
Finished Aug 25 07:37:21 AM UTC 24
Peak memory 232116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611152269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3611152269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.665764498
Short name T854
Test name
Test status
Simulation time 136481875 ps
CPU time 5.03 seconds
Started Aug 25 07:37:14 AM UTC 24
Finished Aug 25 07:37:21 AM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665764498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.665764498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_random.475567494
Short name T853
Test name
Test status
Simulation time 113361684 ps
CPU time 4.45 seconds
Started Aug 25 07:37:14 AM UTC 24
Finished Aug 25 07:37:20 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475567494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.475567494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.2991747392
Short name T848
Test name
Test status
Simulation time 64057887 ps
CPU time 4.78 seconds
Started Aug 25 07:37:11 AM UTC 24
Finished Aug 25 07:37:17 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991747392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2991747392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.2712274836
Short name T849
Test name
Test status
Simulation time 198948012 ps
CPU time 3.79 seconds
Started Aug 25 07:37:12 AM UTC 24
Finished Aug 25 07:37:17 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712274836 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2712274836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.2083533983
Short name T858
Test name
Test status
Simulation time 188845234 ps
CPU time 9.67 seconds
Started Aug 25 07:37:12 AM UTC 24
Finished Aug 25 07:37:23 AM UTC 24
Peak memory 217972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083533983 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2083533983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.1825410915
Short name T804
Test name
Test status
Simulation time 408563926 ps
CPU time 7.77 seconds
Started Aug 25 07:37:13 AM UTC 24
Finished Aug 25 07:37:22 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825410915 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1825410915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.1479110932
Short name T325
Test name
Test status
Simulation time 460296886 ps
CPU time 7.07 seconds
Started Aug 25 07:37:17 AM UTC 24
Finished Aug 25 07:37:25 AM UTC 24
Peak memory 220000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479110932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1479110932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.935994020
Short name T847
Test name
Test status
Simulation time 113752889 ps
CPU time 3.86 seconds
Started Aug 25 07:37:11 AM UTC 24
Finished Aug 25 07:37:16 AM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935994020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.935994020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.2104144791
Short name T907
Test name
Test status
Simulation time 3762003985 ps
CPU time 87.02 seconds
Started Aug 25 07:37:17 AM UTC 24
Finished Aug 25 07:38:47 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104144791 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2104144791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all_with_rand_reset.2754103351
Short name T871
Test name
Test status
Simulation time 132497360 ps
CPU time 11.91 seconds
Started Aug 25 07:37:17 AM UTC 24
Finished Aug 25 07:37:31 AM UTC 24
Peak memory 232296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2754103351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymg
r_stress_all_with_rand_reset.2754103351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.2866610753
Short name T855
Test name
Test status
Simulation time 319441491 ps
CPU time 5.21 seconds
Started Aug 25 07:37:14 AM UTC 24
Finished Aug 25 07:37:21 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866610753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2866610753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.3498068013
Short name T410
Test name
Test status
Simulation time 764658409 ps
CPU time 4.97 seconds
Started Aug 25 07:37:17 AM UTC 24
Finished Aug 25 07:37:23 AM UTC 24
Peak memory 220108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498068013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3498068013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.2151617154
Short name T861
Test name
Test status
Simulation time 31902120 ps
CPU time 1.16 seconds
Started Aug 25 07:37:26 AM UTC 24
Finished Aug 25 07:37:28 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151617154 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2151617154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.2620749458
Short name T291
Test name
Test status
Simulation time 104428057 ps
CPU time 7.96 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:33 AM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620749458 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2620749458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.194342958
Short name T866
Test name
Test status
Simulation time 149168204 ps
CPU time 3.05 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:29 AM UTC 24
Peak memory 218560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194342958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.194342958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.1619061794
Short name T869
Test name
Test status
Simulation time 65687740 ps
CPU time 4.49 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:30 AM UTC 24
Peak memory 218116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619061794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1619061794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.3910181534
Short name T868
Test name
Test status
Simulation time 73556144 ps
CPU time 3.28 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:29 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910181534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3910181534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.1598395194
Short name T360
Test name
Test status
Simulation time 594347941 ps
CPU time 39.12 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:38:05 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598395194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1598395194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_random.679121957
Short name T877
Test name
Test status
Simulation time 265885296 ps
CPU time 7.41 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:33 AM UTC 24
Peak memory 230288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679121957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.679121957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.1731246607
Short name T865
Test name
Test status
Simulation time 44073002 ps
CPU time 3.67 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:29 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731246607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1731246607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.1787092505
Short name T875
Test name
Test status
Simulation time 273305303 ps
CPU time 6.84 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:32 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787092505 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1787092505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.3276388409
Short name T876
Test name
Test status
Simulation time 187312235 ps
CPU time 7.56 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:33 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276388409 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3276388409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.3030979316
Short name T864
Test name
Test status
Simulation time 36572470 ps
CPU time 3.43 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:29 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030979316 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3030979316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.2744977091
Short name T863
Test name
Test status
Simulation time 114883391 ps
CPU time 2.64 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:28 AM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744977091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2744977091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.204707028
Short name T862
Test name
Test status
Simulation time 90394847 ps
CPU time 3.03 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:28 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204707028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.204707028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.2785624905
Short name T906
Test name
Test status
Simulation time 1820215329 ps
CPU time 61.15 seconds
Started Aug 25 07:37:25 AM UTC 24
Finished Aug 25 07:38:29 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785624905 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2785624905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.795572259
Short name T902
Test name
Test status
Simulation time 1540701214 ps
CPU time 27.32 seconds
Started Aug 25 07:37:26 AM UTC 24
Finished Aug 25 07:37:54 AM UTC 24
Peak memory 232456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=795572259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr
_stress_all_with_rand_reset.795572259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.4160487744
Short name T872
Test name
Test status
Simulation time 140019802 ps
CPU time 5.13 seconds
Started Aug 25 07:37:24 AM UTC 24
Finished Aug 25 07:37:31 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160487744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4160487744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2092038519
Short name T882
Test name
Test status
Simulation time 33578112 ps
CPU time 1.1 seconds
Started Aug 25 07:37:33 AM UTC 24
Finished Aug 25 07:37:35 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092038519 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2092038519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.1937036366
Short name T333
Test name
Test status
Simulation time 36089959 ps
CPU time 4.32 seconds
Started Aug 25 07:37:30 AM UTC 24
Finished Aug 25 07:37:36 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937036366 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1937036366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.2506164291
Short name T888
Test name
Test status
Simulation time 302790407 ps
CPU time 8.76 seconds
Started Aug 25 07:37:32 AM UTC 24
Finished Aug 25 07:37:42 AM UTC 24
Peak memory 220368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506164291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2506164291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.2882517080
Short name T881
Test name
Test status
Simulation time 78201629 ps
CPU time 3.37 seconds
Started Aug 25 07:37:30 AM UTC 24
Finished Aug 25 07:37:35 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882517080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2882517080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.1092114855
Short name T880
Test name
Test status
Simulation time 140426923 ps
CPU time 3.04 seconds
Started Aug 25 07:37:30 AM UTC 24
Finished Aug 25 07:37:35 AM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092114855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1092114855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.61971368
Short name T385
Test name
Test status
Simulation time 169859788 ps
CPU time 3.67 seconds
Started Aug 25 07:37:31 AM UTC 24
Finished Aug 25 07:37:36 AM UTC 24
Peak memory 230204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61971368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.61971368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.915688095
Short name T883
Test name
Test status
Simulation time 183978291 ps
CPU time 4.79 seconds
Started Aug 25 07:37:30 AM UTC 24
Finished Aug 25 07:37:36 AM UTC 24
Peak memory 217796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915688095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.915688095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_random.3289363015
Short name T899
Test name
Test status
Simulation time 500598206 ps
CPU time 13.04 seconds
Started Aug 25 07:37:30 AM UTC 24
Finished Aug 25 07:37:45 AM UTC 24
Peak memory 219972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289363015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3289363015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.710399629
Short name T874
Test name
Test status
Simulation time 211444881 ps
CPU time 3.71 seconds
Started Aug 25 07:37:27 AM UTC 24
Finished Aug 25 07:37:32 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710399629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.710399629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.3010692670
Short name T879
Test name
Test status
Simulation time 62693181 ps
CPU time 4.58 seconds
Started Aug 25 07:37:29 AM UTC 24
Finished Aug 25 07:37:35 AM UTC 24
Peak memory 218184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010692670 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3010692670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.2776847972
Short name T908
Test name
Test status
Simulation time 9598719727 ps
CPU time 110.56 seconds
Started Aug 25 07:37:29 AM UTC 24
Finished Aug 25 07:39:22 AM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776847972 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2776847972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.1302891964
Short name T884
Test name
Test status
Simulation time 313679015 ps
CPU time 7.86 seconds
Started Aug 25 07:37:29 AM UTC 24
Finished Aug 25 07:37:38 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302891964 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1302891964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.2106178704
Short name T885
Test name
Test status
Simulation time 91603321 ps
CPU time 5.69 seconds
Started Aug 25 07:37:32 AM UTC 24
Finished Aug 25 07:37:39 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106178704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2106178704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.3551369380
Short name T878
Test name
Test status
Simulation time 162719524 ps
CPU time 6.24 seconds
Started Aug 25 07:37:27 AM UTC 24
Finished Aug 25 07:37:34 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551369380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3551369380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1459423231
Short name T234
Test name
Test status
Simulation time 2431672964 ps
CPU time 57.08 seconds
Started Aug 25 07:37:33 AM UTC 24
Finished Aug 25 07:38:32 AM UTC 24
Peak memory 232312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459423231 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1459423231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.2689044060
Short name T897
Test name
Test status
Simulation time 627128041 ps
CPU time 12.4 seconds
Started Aug 25 07:37:30 AM UTC 24
Finished Aug 25 07:37:44 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689044060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2689044060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.3278010109
Short name T168
Test name
Test status
Simulation time 103390957 ps
CPU time 3.02 seconds
Started Aug 25 07:37:32 AM UTC 24
Finished Aug 25 07:37:36 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278010109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3278010109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.1733834018
Short name T894
Test name
Test status
Simulation time 10392577 ps
CPU time 1.26 seconds
Started Aug 25 07:37:41 AM UTC 24
Finished Aug 25 07:37:44 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733834018 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1733834018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3525657855
Short name T901
Test name
Test status
Simulation time 585628502 ps
CPU time 16.84 seconds
Started Aug 25 07:37:35 AM UTC 24
Finished Aug 25 07:37:54 AM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525657855 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3525657855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.2006500672
Short name T311
Test name
Test status
Simulation time 46747149 ps
CPU time 3.89 seconds
Started Aug 25 07:37:38 AM UTC 24
Finished Aug 25 07:37:43 AM UTC 24
Peak memory 224476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006500672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2006500672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.779651597
Short name T895
Test name
Test status
Simulation time 207254622 ps
CPU time 6.84 seconds
Started Aug 25 07:37:35 AM UTC 24
Finished Aug 25 07:37:44 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779651597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.779651597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.2963353515
Short name T887
Test name
Test status
Simulation time 41675374 ps
CPU time 3.5 seconds
Started Aug 25 07:37:37 AM UTC 24
Finished Aug 25 07:37:42 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963353515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2963353515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.1381647587
Short name T890
Test name
Test status
Simulation time 67357507 ps
CPU time 4.62 seconds
Started Aug 25 07:37:37 AM UTC 24
Finished Aug 25 07:37:43 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381647587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1381647587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_random.4119278950
Short name T903
Test name
Test status
Simulation time 612736195 ps
CPU time 18.09 seconds
Started Aug 25 07:37:35 AM UTC 24
Finished Aug 25 07:37:55 AM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119278950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4119278950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.2504633817
Short name T900
Test name
Test status
Simulation time 641179442 ps
CPU time 9.83 seconds
Started Aug 25 07:37:34 AM UTC 24
Finished Aug 25 07:37:45 AM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504633817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2504633817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.4169099336
Short name T896
Test name
Test status
Simulation time 223844013 ps
CPU time 8.53 seconds
Started Aug 25 07:37:34 AM UTC 24
Finished Aug 25 07:37:44 AM UTC 24
Peak memory 215880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169099336 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4169099336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.3143718636
Short name T898
Test name
Test status
Simulation time 614393125 ps
CPU time 8.99 seconds
Started Aug 25 07:37:34 AM UTC 24
Finished Aug 25 07:37:45 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143718636 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3143718636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.2959968901
Short name T886
Test name
Test status
Simulation time 51139849 ps
CPU time 4.06 seconds
Started Aug 25 07:37:35 AM UTC 24
Finished Aug 25 07:37:41 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959968901 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2959968901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.3105690035
Short name T889
Test name
Test status
Simulation time 76169506 ps
CPU time 2.84 seconds
Started Aug 25 07:37:38 AM UTC 24
Finished Aug 25 07:37:42 AM UTC 24
Peak memory 215996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105690035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3105690035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.1289389251
Short name T904
Test name
Test status
Simulation time 2823049510 ps
CPU time 30.87 seconds
Started Aug 25 07:37:34 AM UTC 24
Finished Aug 25 07:38:07 AM UTC 24
Peak memory 217900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289389251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1289389251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.231971186
Short name T905
Test name
Test status
Simulation time 458419522 ps
CPU time 34.11 seconds
Started Aug 25 07:37:40 AM UTC 24
Finished Aug 25 07:38:16 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231971186 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.231971186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.1689914997
Short name T317
Test name
Test status
Simulation time 118904133 ps
CPU time 4.52 seconds
Started Aug 25 07:37:37 AM UTC 24
Finished Aug 25 07:37:43 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689914997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1689914997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.2276847217
Short name T893
Test name
Test status
Simulation time 158861846 ps
CPU time 3.44 seconds
Started Aug 25 07:37:39 AM UTC 24
Finished Aug 25 07:37:44 AM UTC 24
Peak memory 220048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276847217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2276847217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.1718331139
Short name T450
Test name
Test status
Simulation time 43095189 ps
CPU time 1.17 seconds
Started Aug 25 07:30:18 AM UTC 24
Finished Aug 25 07:30:21 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718331139 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1718331139
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.4019802965
Short name T107
Test name
Test status
Simulation time 47191242 ps
CPU time 5.11 seconds
Started Aug 25 07:30:11 AM UTC 24
Finished Aug 25 07:30:18 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019802965 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4019802965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.1293308534
Short name T31
Test name
Test status
Simulation time 42760313 ps
CPU time 3.7 seconds
Started Aug 25 07:30:16 AM UTC 24
Finished Aug 25 07:30:21 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293308534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1293308534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.3966480317
Short name T422
Test name
Test status
Simulation time 75951093 ps
CPU time 1.97 seconds
Started Aug 25 07:30:11 AM UTC 24
Finished Aug 25 07:30:15 AM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966480317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3966480317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.3728922036
Short name T45
Test name
Test status
Simulation time 338455624 ps
CPU time 4.28 seconds
Started Aug 25 07:30:15 AM UTC 24
Finished Aug 25 07:30:20 AM UTC 24
Peak memory 226112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728922036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3728922036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.1225943094
Short name T250
Test name
Test status
Simulation time 1678362926 ps
CPU time 8.59 seconds
Started Aug 25 07:30:16 AM UTC 24
Finished Aug 25 07:30:26 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225943094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1225943094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.1105454777
Short name T137
Test name
Test status
Simulation time 165101783 ps
CPU time 5.85 seconds
Started Aug 25 07:30:13 AM UTC 24
Finished Aug 25 07:30:19 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105454777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1105454777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_random.3754197999
Short name T378
Test name
Test status
Simulation time 102474147 ps
CPU time 4.7 seconds
Started Aug 25 07:30:11 AM UTC 24
Finished Aug 25 07:30:17 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754197999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3754197999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.46375287
Short name T300
Test name
Test status
Simulation time 46981101 ps
CPU time 2.81 seconds
Started Aug 25 07:30:10 AM UTC 24
Finished Aug 25 07:30:14 AM UTC 24
Peak memory 217908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46375287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.46375287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.2604555792
Short name T358
Test name
Test status
Simulation time 40905510 ps
CPU time 3.65 seconds
Started Aug 25 07:30:10 AM UTC 24
Finished Aug 25 07:30:15 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604555792 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2604555792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.2011678809
Short name T261
Test name
Test status
Simulation time 86020251 ps
CPU time 4.39 seconds
Started Aug 25 07:30:10 AM UTC 24
Finished Aug 25 07:30:16 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011678809 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2011678809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.2624968737
Short name T331
Test name
Test status
Simulation time 175679085 ps
CPU time 3.47 seconds
Started Aug 25 07:30:11 AM UTC 24
Finished Aug 25 07:30:16 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624968737 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2624968737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.2950250084
Short name T274
Test name
Test status
Simulation time 594439100 ps
CPU time 8.97 seconds
Started Aug 25 07:30:17 AM UTC 24
Finished Aug 25 07:30:27 AM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950250084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2950250084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.753139099
Short name T449
Test name
Test status
Simulation time 116109133 ps
CPU time 3.34 seconds
Started Aug 25 07:30:09 AM UTC 24
Finished Aug 25 07:30:14 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753139099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.753139099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.4042953481
Short name T215
Test name
Test status
Simulation time 314208647 ps
CPU time 7.89 seconds
Started Aug 25 07:30:15 AM UTC 24
Finished Aug 25 07:30:24 AM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042953481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4042953481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.2910403389
Short name T89
Test name
Test status
Simulation time 424457726 ps
CPU time 7.05 seconds
Started Aug 25 07:30:17 AM UTC 24
Finished Aug 25 07:30:25 AM UTC 24
Peak memory 220328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910403389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2910403389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.1624820445
Short name T451
Test name
Test status
Simulation time 19293392 ps
CPU time 1.17 seconds
Started Aug 25 07:30:33 AM UTC 24
Finished Aug 25 07:30:36 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624820445 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1624820445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.4042982886
Short name T68
Test name
Test status
Simulation time 124417515 ps
CPU time 4.41 seconds
Started Aug 25 07:30:26 AM UTC 24
Finished Aug 25 07:30:32 AM UTC 24
Peak memory 218256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042982886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4042982886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.2935971624
Short name T133
Test name
Test status
Simulation time 283956366 ps
CPU time 4.07 seconds
Started Aug 25 07:30:25 AM UTC 24
Finished Aug 25 07:30:30 AM UTC 24
Peak memory 226464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935971624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2935971624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.2990174490
Short name T251
Test name
Test status
Simulation time 1907895092 ps
CPU time 5.61 seconds
Started Aug 25 07:30:26 AM UTC 24
Finished Aug 25 07:30:33 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990174490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2990174490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.4242124937
Short name T307
Test name
Test status
Simulation time 45036216 ps
CPU time 4.56 seconds
Started Aug 25 07:30:26 AM UTC 24
Finished Aug 25 07:30:32 AM UTC 24
Peak memory 224312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242124937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4242124937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.184861707
Short name T7
Test name
Test status
Simulation time 32464460 ps
CPU time 2.33 seconds
Started Aug 25 07:30:25 AM UTC 24
Finished Aug 25 07:30:29 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184861707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.184861707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_random.3749288539
Short name T270
Test name
Test status
Simulation time 1803301333 ps
CPU time 18.94 seconds
Started Aug 25 07:30:22 AM UTC 24
Finished Aug 25 07:30:42 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749288539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3749288539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.3369115058
Short name T266
Test name
Test status
Simulation time 44628466 ps
CPU time 3.35 seconds
Started Aug 25 07:30:20 AM UTC 24
Finished Aug 25 07:30:25 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369115058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3369115058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.1284060648
Short name T377
Test name
Test status
Simulation time 771109515 ps
CPU time 25.24 seconds
Started Aug 25 07:30:22 AM UTC 24
Finished Aug 25 07:30:49 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284060648 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1284060648
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.2143485333
Short name T337
Test name
Test status
Simulation time 23794794 ps
CPU time 2.46 seconds
Started Aug 25 07:30:22 AM UTC 24
Finished Aug 25 07:30:25 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143485333 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2143485333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.2548003304
Short name T353
Test name
Test status
Simulation time 5819896254 ps
CPU time 55.23 seconds
Started Aug 25 07:30:22 AM UTC 24
Finished Aug 25 07:31:19 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548003304 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2548003304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.1740900177
Short name T292
Test name
Test status
Simulation time 1232218191 ps
CPU time 15.85 seconds
Started Aug 25 07:30:28 AM UTC 24
Finished Aug 25 07:30:45 AM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740900177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1740900177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.2929697714
Short name T453
Test name
Test status
Simulation time 595586424 ps
CPU time 17.78 seconds
Started Aug 25 07:30:18 AM UTC 24
Finished Aug 25 07:30:38 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929697714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2929697714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.3594413797
Short name T339
Test name
Test status
Simulation time 96308087 ps
CPU time 3.98 seconds
Started Aug 25 07:30:26 AM UTC 24
Finished Aug 25 07:30:31 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594413797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3594413797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.3979752497
Short name T455
Test name
Test status
Simulation time 47205564 ps
CPU time 1.25 seconds
Started Aug 25 07:30:49 AM UTC 24
Finished Aug 25 07:30:52 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979752497 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3979752497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.4144265802
Short name T255
Test name
Test status
Simulation time 190749337 ps
CPU time 4.56 seconds
Started Aug 25 07:30:38 AM UTC 24
Finished Aug 25 07:30:45 AM UTC 24
Peak memory 226224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144265802 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4144265802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.3472608420
Short name T28
Test name
Test status
Simulation time 83273332 ps
CPU time 3.03 seconds
Started Aug 25 07:30:45 AM UTC 24
Finished Aug 25 07:30:50 AM UTC 24
Peak memory 228532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472608420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3472608420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.3728701936
Short name T454
Test name
Test status
Simulation time 99096403 ps
CPU time 2.3 seconds
Started Aug 25 07:30:40 AM UTC 24
Finished Aug 25 07:30:44 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728701936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3728701936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.99884222
Short name T252
Test name
Test status
Simulation time 40769617 ps
CPU time 2.99 seconds
Started Aug 25 07:30:45 AM UTC 24
Finished Aug 25 07:30:50 AM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99884222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.99884222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.3454359628
Short name T434
Test name
Test status
Simulation time 1647228656 ps
CPU time 3.94 seconds
Started Aug 25 07:30:42 AM UTC 24
Finished Aug 25 07:30:48 AM UTC 24
Peak memory 215248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454359628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3454359628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_random.2678922686
Short name T321
Test name
Test status
Simulation time 223465678 ps
CPU time 11.26 seconds
Started Aug 25 07:30:38 AM UTC 24
Finished Aug 25 07:30:51 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678922686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2678922686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.360191452
Short name T423
Test name
Test status
Simulation time 7053506656 ps
CPU time 48.93 seconds
Started Aug 25 07:30:33 AM UTC 24
Finished Aug 25 07:31:24 AM UTC 24
Peak memory 218016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360191452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.360191452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.2359138431
Short name T362
Test name
Test status
Simulation time 2255243039 ps
CPU time 18.04 seconds
Started Aug 25 07:30:37 AM UTC 24
Finished Aug 25 07:30:57 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359138431 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2359138431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.3401594720
Short name T359
Test name
Test status
Simulation time 51146782 ps
CPU time 3.77 seconds
Started Aug 25 07:30:34 AM UTC 24
Finished Aug 25 07:30:39 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401594720 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3401594720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.3973006102
Short name T262
Test name
Test status
Simulation time 65072265 ps
CPU time 3.55 seconds
Started Aug 25 07:30:37 AM UTC 24
Finished Aug 25 07:30:42 AM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973006102 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3973006102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.516623072
Short name T456
Test name
Test status
Simulation time 113078371 ps
CPU time 5.9 seconds
Started Aug 25 07:30:46 AM UTC 24
Finished Aug 25 07:30:53 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516623072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.516623072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.2567895846
Short name T452
Test name
Test status
Simulation time 49164647 ps
CPU time 2.6 seconds
Started Aug 25 07:30:33 AM UTC 24
Finished Aug 25 07:30:37 AM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567895846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2567895846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.2228839549
Short name T224
Test name
Test status
Simulation time 11794289896 ps
CPU time 158.69 seconds
Started Aug 25 07:30:47 AM UTC 24
Finished Aug 25 07:33:29 AM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228839549 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2228839549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.3322127520
Short name T91
Test name
Test status
Simulation time 450328862 ps
CPU time 33.02 seconds
Started Aug 25 07:30:49 AM UTC 24
Finished Aug 25 07:31:24 AM UTC 24
Peak memory 232412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3322127520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr
_stress_all_with_rand_reset.3322127520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2434415727
Short name T220
Test name
Test status
Simulation time 518520052 ps
CPU time 9.19 seconds
Started Aug 25 07:30:42 AM UTC 24
Finished Aug 25 07:30:53 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434415727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2434415727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.3398803786
Short name T207
Test name
Test status
Simulation time 853856274 ps
CPU time 12.87 seconds
Started Aug 25 07:30:46 AM UTC 24
Finished Aug 25 07:31:00 AM UTC 24
Peak memory 220044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398803786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3398803786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.1413646586
Short name T213
Test name
Test status
Simulation time 48081349 ps
CPU time 1.14 seconds
Started Aug 25 07:31:04 AM UTC 24
Finished Aug 25 07:31:06 AM UTC 24
Peak memory 213460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413646586 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1413646586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.1428035606
Short name T208
Test name
Test status
Simulation time 62991550 ps
CPU time 6.1 seconds
Started Aug 25 07:30:55 AM UTC 24
Finished Aug 25 07:31:03 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428035606 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1428035606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.2667684680
Short name T134
Test name
Test status
Simulation time 211177168 ps
CPU time 3.53 seconds
Started Aug 25 07:30:55 AM UTC 24
Finished Aug 25 07:31:00 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667684680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2667684680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.1411938663
Short name T253
Test name
Test status
Simulation time 99512979 ps
CPU time 6.56 seconds
Started Aug 25 07:30:58 AM UTC 24
Finished Aug 25 07:31:06 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411938663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1411938663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.1137452723
Short name T212
Test name
Test status
Simulation time 86519572 ps
CPU time 5.55 seconds
Started Aug 25 07:30:58 AM UTC 24
Finished Aug 25 07:31:05 AM UTC 24
Peak memory 232452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137452723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1137452723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.3633342911
Short name T110
Test name
Test status
Simulation time 104280137 ps
CPU time 5.5 seconds
Started Aug 25 07:30:56 AM UTC 24
Finished Aug 25 07:31:03 AM UTC 24
Peak memory 218316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633342911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3633342911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_random.4138052354
Short name T436
Test name
Test status
Simulation time 27741073 ps
CPU time 2.9 seconds
Started Aug 25 07:30:53 AM UTC 24
Finished Aug 25 07:30:58 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138052354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4138052354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.4176231866
Short name T221
Test name
Test status
Simulation time 43713913 ps
CPU time 2.91 seconds
Started Aug 25 07:30:50 AM UTC 24
Finished Aug 25 07:30:55 AM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176231866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4176231866
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.1758068512
Short name T459
Test name
Test status
Simulation time 51593484 ps
CPU time 3.63 seconds
Started Aug 25 07:30:51 AM UTC 24
Finished Aug 25 07:30:58 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758068512 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1758068512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.3721014982
Short name T457
Test name
Test status
Simulation time 52934416 ps
CPU time 3.74 seconds
Started Aug 25 07:30:50 AM UTC 24
Finished Aug 25 07:30:56 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721014982 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3721014982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.916345389
Short name T209
Test name
Test status
Simulation time 189058035 ps
CPU time 8.61 seconds
Started Aug 25 07:30:52 AM UTC 24
Finished Aug 25 07:31:03 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916345389 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.916345389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3457239559
Short name T210
Test name
Test status
Simulation time 40114262 ps
CPU time 3.41 seconds
Started Aug 25 07:30:58 AM UTC 24
Finished Aug 25 07:31:03 AM UTC 24
Peak memory 226340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457239559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3457239559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.2747007920
Short name T458
Test name
Test status
Simulation time 377948454 ps
CPU time 6.33 seconds
Started Aug 25 07:30:49 AM UTC 24
Finished Aug 25 07:30:57 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747007920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2747007920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.772644960
Short name T219
Test name
Test status
Simulation time 251878464 ps
CPU time 10.28 seconds
Started Aug 25 07:31:00 AM UTC 24
Finished Aug 25 07:31:12 AM UTC 24
Peak memory 226520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772644960 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.772644960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.1708572664
Short name T211
Test name
Test status
Simulation time 104977175 ps
CPU time 5.19 seconds
Started Aug 25 07:30:57 AM UTC 24
Finished Aug 25 07:31:03 AM UTC 24
Peak memory 228192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708572664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1708572664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.3849939350
Short name T142
Test name
Test status
Simulation time 448026039 ps
CPU time 4.31 seconds
Started Aug 25 07:30:58 AM UTC 24
Finished Aug 25 07:31:04 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849939350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3849939350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2905682071
Short name T460
Test name
Test status
Simulation time 37592482 ps
CPU time 1.11 seconds
Started Aug 25 07:31:14 AM UTC 24
Finished Aug 25 07:31:17 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905682071 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2905682071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.3349754913
Short name T112
Test name
Test status
Simulation time 535813481 ps
CPU time 4.36 seconds
Started Aug 25 07:31:06 AM UTC 24
Finished Aug 25 07:31:12 AM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349754913 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3349754913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.3504197912
Short name T29
Test name
Test status
Simulation time 168373120 ps
CPU time 6.6 seconds
Started Aug 25 07:31:10 AM UTC 24
Finished Aug 25 07:31:19 AM UTC 24
Peak memory 232632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504197912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3504197912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.1160036798
Short name T414
Test name
Test status
Simulation time 278308926 ps
CPU time 10.67 seconds
Started Aug 25 07:31:07 AM UTC 24
Finished Aug 25 07:31:19 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160036798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1160036798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.1785616927
Short name T56
Test name
Test status
Simulation time 246995022 ps
CPU time 5.7 seconds
Started Aug 25 07:31:08 AM UTC 24
Finished Aug 25 07:31:15 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785616927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1785616927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.2992053088
Short name T26
Test name
Test status
Simulation time 87768914 ps
CPU time 5.55 seconds
Started Aug 25 07:31:09 AM UTC 24
Finished Aug 25 07:31:16 AM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992053088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2992053088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_random.198359366
Short name T314
Test name
Test status
Simulation time 401889284 ps
CPU time 5.42 seconds
Started Aug 25 07:31:06 AM UTC 24
Finished Aug 25 07:31:13 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198359366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.198359366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.667920233
Short name T319
Test name
Test status
Simulation time 19905802 ps
CPU time 2.61 seconds
Started Aug 25 07:31:04 AM UTC 24
Finished Aug 25 07:31:08 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667920233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.667920233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.2239948381
Short name T417
Test name
Test status
Simulation time 22340372 ps
CPU time 2.43 seconds
Started Aug 25 07:31:04 AM UTC 24
Finished Aug 25 07:31:07 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239948381 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2239948381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.1054401267
Short name T288
Test name
Test status
Simulation time 54528978 ps
CPU time 4.26 seconds
Started Aug 25 07:31:05 AM UTC 24
Finished Aug 25 07:31:10 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054401267 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1054401267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.2992124953
Short name T461
Test name
Test status
Simulation time 348339121 ps
CPU time 3.78 seconds
Started Aug 25 07:31:12 AM UTC 24
Finished Aug 25 07:31:17 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992124953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2992124953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.3755180664
Short name T415
Test name
Test status
Simulation time 35067819 ps
CPU time 3.55 seconds
Started Aug 25 07:31:04 AM UTC 24
Finished Aug 25 07:31:09 AM UTC 24
Peak memory 217900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755180664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3755180664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.2834653851
Short name T93
Test name
Test status
Simulation time 898627139 ps
CPU time 33.75 seconds
Started Aug 25 07:31:13 AM UTC 24
Finished Aug 25 07:31:49 AM UTC 24
Peak memory 232408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2834653851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr
_stress_all_with_rand_reset.2834653851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.2079836580
Short name T289
Test name
Test status
Simulation time 398785486 ps
CPU time 9.24 seconds
Started Aug 25 07:31:08 AM UTC 24
Finished Aug 25 07:31:19 AM UTC 24
Peak memory 219964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079836580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2079836580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest
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