Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	46	1			T127	1		T9	1		T8	1
auto[OpGenId]	11	1			T97	1		T39	1		T220	1
auto[OpGenSwOut]	17	1			T71	1		T133	1		T111	1
auto[OpGenHwOut]	18	1			T6	1		T7	1		T137	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1685	1			T66	2		T10	90		T11	180
auto[StInit]	89	1			T6	1		T127	1		T20	1
auto[StCreatorRootKey]	61	1			T19	1		T9	1		T70	1
auto[StOwnerIntKey]	35	1			T34	1		T132	1		T133	1
auto[StOwnerKey]	50	1			T17	1		T35	1		T40	1
auto[StDisabled]	471	1			T66	3		T136	1		T69	5
auto[StInvalid]	50	1			T15	1		T36	1		T68	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3420

1

T1

1

T2

1

T3

1

auto[1]

92

1

T6

1

T127

1

T71

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1682	1			T66	2		T10	90		T11	180
auto[StReset]	auto[1]	3	1			T83	1		T221	1		T138	1
auto[StInit]	auto[0]	39	1			T20	1		T108	1		T171	1
auto[StInit]	auto[1]	50	1			T6	1		T127	1		T7	1
auto[StCreatorRootKey]	auto[0]	41	1			T19	1		T70	1		T131	1
auto[StCreatorRootKey]	auto[1]	20	1			T9	1		T8	1		T111	1
auto[StOwnerIntKey]	auto[0]	28	1			T34	1		T132	1		T95	1
auto[StOwnerIntKey]	auto[1]	7	1			T133	1		T222	1		T223	1
auto[StOwnerKey]	auto[0]	41	1			T17	1		T35	1		T40	1
auto[StOwnerKey]	auto[1]	9	1			T71	1		T111	1		T224	1
auto[StDisabled]	auto[0]	468	1			T66	3		T136	1		T69	5
auto[StDisabled]	auto[1]	3	1			T38	1		T225	1		T226	1
auto[StInvalid]	auto[0]	50	1			T15	1		T36	1		T68	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T83	1		T221	1		T138	1
auto[StInit]	auto[OpAdvance]	24	1			T127	1		T94	1		T81	1
auto[StInit]	auto[OpGenId]	6	1			T97	1		T220	1		T227	1
auto[StInit]	auto[OpGenSwOut]	7	1			T228	1		T229	1		T230	1
auto[StInit]	auto[OpGenHwOut]	13	1			T6	1		T7	1		T137	1
auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T9	1		T8	1		T97	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T39	1		T231	1		T232	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T111	1		T233	1		T234	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T235	1		T236	1		T237	2
auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T222	1		T238	1		T239	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T240	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T133	1		T223	1		T241	1
auto[StOwnerKey]	auto[OpAdvance]	5	1			T224	1		T151	1		T233	1
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T71	1		T242	1		T243	1
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T111	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	1	1			T38	1		-	-		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T225	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	1	1			T226	1		-	-		-	-