Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4803

1

T2

4

T3

9

T4

9

auto[1]

546

1

T33

4

T26

4

T124

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4803

1

T2

4

T3

9

T4

9

auto[1]

546

1

T33

4

T26

4

T124

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4736

1

T2

4

T3

5

T4

9

auto[1]

613

1

T3

4

T5

1

T42

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4736

1

T2

4

T3

5

T4

9

auto[1]

613

1

T3

4

T5

1

T42

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T15	1		T16	2		T26	1
auto[OpGenId]	1094	1			T2	1		T5	2		T15	2
auto[OpGenSwOut]	1153	1			T2	3		T14	2		T15	1
auto[OpGenHwOut]	2584	1			T3	9		T4	9		T13	9
auto[OpDisable]	81	1			T126	1		T66	1		T69	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	437	1			T15	1		T16	2		T26	1
auto[OpGenId]	1094	1			T2	1		T5	2		T15	2
auto[OpGenSwOut]	1153	1			T2	3		T14	2		T15	1
auto[OpGenHwOut]	2584	1			T3	9		T4	9		T13	9
auto[OpDisable]	81	1			T126	1		T66	1		T69	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4829

1

T2

4

T3

9

T4

4

auto[1]

520

1

T4

5

T13

5

T16

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4829

1

T2

4

T3

9

T4

4

auto[1]

520

1

T4

5

T13

5

T16

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5078

1

T2

4

T3

9

T4

9

auto[1]

271

1

T42

7

T88

6

T106

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1873	1			T2	1		T3	4		T4	3
auto[1]	686	1			T3	2		T4	1		T5	1
auto[2]	683	1			T3	1		T4	2		T13	2
auto[3]	697	1			T2	2		T4	2		T13	1
auto[4]	341	1			T2	1		T3	1		T13	1
auto[5]	368	1			T124	1		T88	2		T103	1
auto[6]	353	1			T14	1		T33	1		T18	1
auto[7]	348	1			T3	1		T4	1		T13	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1410	1			T2	1		T3	2		T4	1
clear_one[1]	686	1			T3	2		T4	1		T5	1
clear_one[2]	683	1			T3	1		T4	2		T13	2
clear_one[3]	697	1			T2	2		T4	2		T13	1
clear_none	1873	1			T2	1		T3	4		T4	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	942	1			T3	1		T4	1		T13	1
auto[StInit]	677	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	572	1			T3	1		T4	1		T13	1
auto[StOwnerIntKey]	528	1			T3	1		T4	1		T13	1
auto[StOwnerKey]	467	1			T3	1		T4	1		T13	1
auto[StDisabled]	1871	1			T2	3		T3	4		T4	4
auto[StInvalid]	292	1			T14	4		T15	5		T100	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	942	1			T3	1		T4	1		T13	1
auto[StInit]	677	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	572	1			T3	1		T4	1		T13	1
auto[StOwnerIntKey]	528	1			T3	1		T4	1		T13	1
auto[StOwnerKey]	467	1			T3	1		T4	1		T13	1
auto[StDisabled]	1871	1			T2	3		T3	4		T4	4
auto[StInvalid]	292	1			T14	4		T15	5		T100	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T248	1		T249	1		T250	1
auto[0]	auto[StReset]	auto[OpGenId]	148	1			T5	1		T17	1		T88	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	147	1			T27	2		T70	1		T139	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	248	1			T3	1		T4	1		T13	1
auto[0]	auto[StInit]	auto[OpAdvance]	62	1			T9	1		T70	1		T187	1
auto[0]	auto[StInit]	auto[OpGenId]	92	1			T16	1		T106	1		T20	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	102	1			T2	1		T208	1		T251	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	194	1			T3	1		T26	1		T43	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	26	1			T42	1		T215	1		T252	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	50	1			T66	1		T70	1		T216	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	50	1			T66	1		T69	3		T71	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	75	1			T33	1		T42	1		T18	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T42	1		T69	1		T253	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	37	1			T106	1		T107	1		T108	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	28	1			T66	1		T70	1		T129	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T126	1		T88	2		T136	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T111	1		T149	1		T151	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T42	1		T212	1		T254	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T66	1		T27	1		T94	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T4	1		T33	1		T101	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	35	1			T88	1		T110	4		T255	2
auto[0]	auto[StDisabled]	auto[OpGenId]	50	1			T88	1		T106	1		T197	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	77	1			T26	1		T18	1		T106	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	174	1			T3	2		T4	1		T13	3
auto[0]	auto[StDisabled]	auto[OpDisable]	23	1			T66	1		T76	1		T97	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	8	1			T15	1		T48	1		T203	1
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T15	2		T103	1		T44	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	30	1			T15	1		T100	2		T36	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	24	1			T14	1		T68	1		T139	1
auto[1]	auto[StReset]	auto[OpGenId]	18	1			T110	1		T256	1		T113	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T257	1		T140	1		T142	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	40	1			T33	1		T17	1		T102	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T222	1		T258	2		T259	1
auto[1]	auto[StInit]	auto[OpGenId]	4	1			T111	1		T143	1		T260	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T70	1		T23	1		T261	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T262	1		T263	1		T93	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T200	1		T264	1		T265	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	20	1			T219	1		T148	1		T114	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T71	1		T70	1		T266	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T125	1		T79	1		T267	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T187	1		T268	1		T269	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T255	1		T98	1		T270	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T255	1		T199	1		T99	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T101	1		T105	1		T271	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T42	1		T110	1		T272	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T213	1		T145	1		T273	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T18	1		T268	1		T274	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T75	1		T275	1		T108	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	13	1			T88	1		T107	1		T112	1
auto[1]	auto[StDisabled]	auto[OpGenId]	46	1			T5	1		T66	1		T75	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T16	1		T102	1		T23	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T3	2		T4	1		T33	2
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T74	1		T146	1		T199	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T139	1		T189	1		T218	1
auto[1]	auto[StInvalid]	auto[OpGenId]	14	1			T203	1		T276	1		T277	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T189	1		T278	2		T279	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T14	1		T203	1		T192	1
auto[2]	auto[StReset]	auto[OpGenId]	15	1			T148	1		T149	1		T280	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	23	1			T74	1		T203	1		T281	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	53	1			T33	1		T36	1		T46	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T282	1		T283	1		T258	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T102	1		T199	1		T224	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T128	1		T197	1		T24	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	24	1			T5	1		T105	1		T284	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T285	1		T149	1		T286	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T106	1		T75	1		T208	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T43	1		T129	1		T110	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T13	1		T217	1		T101	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T285	1		T287	1		T143	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T102	1		T191	1		T198	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T70	1		T285	1		T288	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T4	1		T33	1		T204	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T16	1		T128	1		T289	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T69	1		T290	1		T37	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T136	1		T70	1		T198	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T3	1		T73	1		T291	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	20	1			T16	1		T108	2		T114	1
auto[2]	auto[StDisabled]	auto[OpGenId]	57	1			T26	1		T66	1		T23	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T26	1		T219	1		T71	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T4	1		T13	1		T16	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T71	1		T108	1		T151	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	8	1			T49	1		T292	1		T293	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T139	1		T45	1		T294	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T100	1		T68	1		T130	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T44	1		T276	1		T295	1
auto[3]	auto[StReset]	auto[OpGenId]	14	1			T129	1		T192	2		T218	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	22	1			T27	2		T192	1		T95	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T125	1		T101	1		T105	1
auto[3]	auto[StInit]	auto[OpAdvance]	9	1			T296	1		T143	1		T297	1
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T224	1		T152	1		T200	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T298	1		T24	1		T299	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T4	1		T33	1		T101	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T17	1		T300	1		T114	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T204	1		T57	1		T224	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T27	1		T70	1		T151	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T4	1		T105	1		T209	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T301	1		T200	1		T302	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T70	1		T108	1		T303	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T70	1		T23	1		T114	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T13	1		T125	1		T217	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T88	1		T248	1		T143	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	10	1			T108	1		T97	1		T304	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T70	1		T216	1		T305	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T306	1		T23	1		T262	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	26	1			T26	1		T108	1		T188	1
auto[3]	auto[StDisabled]	auto[OpGenId]	60	1			T42	1		T124	1		T126	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T2	2		T42	3		T88	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T16	1		T217	1		T267	2
auto[3]	auto[StDisabled]	auto[OpDisable]	6	1			T143	1		T307	1		T308	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T103	1		T130	1		T309	1
auto[3]	auto[StInvalid]	auto[OpGenId]	8	1			T36	1		T277	1		T310	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T139	1		T309	1		T311	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T139	2		T312	1		T278	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T88	1		T209	1		T313	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T129	1		T95	1		T314	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T275	1		T315	1		T276	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T281	3		T316	1		T317	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T318	1		T319	1		T320	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	2	1			T321	1		T322	1		-	-
auto[4]	auto[StInit]	auto[OpGenHwOut]	13	1			T13	1		T323	1		T324	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T16	1		T325	1		T54	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T97	1		T299	1		T314	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T71	1		T326	1		T327	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T128	1		T111	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T200	1		T328	1		T329	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T205	1		T188	1		T198	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T3	1		T275	1		T108	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T51	1		T330	1		T331	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T332	1		T333	1		T329	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T334	1		T335	1		T336	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	11	1			T71	1		T337	1		T338	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	16	1			T111	1		T199	1		T273	1
auto[4]	auto[StDisabled]	auto[OpGenId]	21	1			T2	1		T42	1		T128	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T108	1		T109	1		T97	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T42	1		T125	2		T105	2
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T126	1		T69	1		T199	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T130	1		T339	1		T340	2
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T189	1		T341	1		T342	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T44	1		T192	1		T45	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T139	1		T312	1		T343	1
auto[5]	auto[StReset]	auto[OpGenId]	6	1			T344	1		T345	1		T310	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T266	1		T218	1		T199	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	18	1			T105	1		T261	1		T110	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T255	1		T346	2		T143	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T301	1		T344	1		T151	2
auto[5]	auto[StInit]	auto[OpGenSwOut]	2	1			T346	1		T347	1		-	-
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T275	1		T291	1		T198	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T346	1		T200	1		T329	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T255	1		T348	1		T39	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T290	1		T349	1		T350	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T124	1		T73	1		T70	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T351	1		T352	1		T353	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T148	1		T314	1		T354	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T27	1		T346	2		T355	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T219	1		T79	1		T262	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T348	1		T356	1		T152	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T357	1		T351	1		T319	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T88	2		T99	1		T345	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T98	1		T358	1		T224	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T188	1		T289	1		T359	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T70	1		T281	3		T360	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T136	1		T216	1		T197	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	90	1			T79	1		T361	1		T263	1
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T362	1		T93	1		T198	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T45	1		T363	1		T364	1
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T276	1		T365	1		T366	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T44	1		T218	1		T366	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T103	1		T68	1		T46	1
auto[6]	auto[StReset]	auto[OpGenId]	4	1			T367	1		T368	1		T369	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T290	1		T218	1		T199	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T101	1		T291	1		T192	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T290	1		T370	1		T53	1
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T71	1		T281	1		T371	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T372	1		T245	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	9	1			T95	1		T135	1		T373	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T374	2		T234	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T107	1		T111	1		T199	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T151	1		T143	1		T236	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T375	1		T199	1		T376	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T356	1		T377	1		T378	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T379	1		T226	1		T283	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T71	1		T108	1		T356	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T380	1		T193	1		T135	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T108	1		T281	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T381	1		T236	1		T382	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T288	1		T383	1		T384	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T105	1		T70	1		T385	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	8	1			T386	1		T287	1		T200	1
auto[6]	auto[StDisabled]	auto[OpGenId]	37	1			T214	1		T94	1		T111	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T18	1		T75	1		T197	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T33	1		T306	1		T275	1
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T387	1		T99	1		T224	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T45	1		T47	1		T363	1
auto[6]	auto[StInvalid]	auto[OpGenId]	8	1			T312	1		T45	1		T365	2
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T14	1		T292	1		T388	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T341	1		T276	1		T389	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T151	2		T236	1		T349	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T301	1		T280	1		T325	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	15	1			T33	1		T203	1		T263	1
auto[7]	auto[StInit]	auto[OpAdvance]	5	1			T390	1		T112	1		T140	1
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T152	1		T185	1		T391	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T108	1		T257	1		T392	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	5	1			T125	1		T198	1		T152	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T303	1		T304	1		T393	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T198	1		T313	1		T152	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T108	1		T151	1		T394	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T3	1		T337	1		T145	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T252	1		T95	1		T395	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T396	1		T329	1		T397	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T97	1		T112	1		T249	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T73	1		T306	1		T108	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T386	1		T398	3		T233	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	2	1			T224	1		T344	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T66	1		T109	1		T332	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T13	1		T124	1		T125	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T27	1		T109	2		T111	1
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T66	1		T76	1		T109	4
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T27	1		T128	1		T266	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T4	1		T125	1		T101	2
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T93	1		T148	1		T399	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T400	1		T401	1		T402	1
auto[7]	auto[StInvalid]	auto[OpGenId]	10	1			T130	2		T189	1		T276	2
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T14	1		T342	1		T294	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T15	1		T192	1		T403	1