Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1410

1

T2

1

T3

2

T4

1

clear_one[1]

auto[0]

auto[0]

auto[0]

386

1

T14

1

T16

1

T33

3

clear_one[1]

auto[0]

auto[0]

auto[1]

114

1

T4

1

T66

1

T105

1

clear_one[1]

auto[0]

auto[1]

auto[0]

141

1

T3

2

T5

1

T125

1

clear_one[1]

auto[0]

auto[1]

auto[1]

45

1

T42

2

T18

1

T102

1

clear_one[2]

auto[0]

auto[0]

auto[0]

409

1

T3

1

T5

1

T16

2

clear_one[2]

auto[0]

auto[0]

auto[1]

115

1

T4

2

T13

2

T16

1

clear_one[2]

auto[1]

auto[0]

auto[0]

123

1

T33

2

T26

1

T124

1

clear_one[2]

auto[1]

auto[0]

auto[1]

36

1

T26

1

T136

1

T197

1

clear_one[3]

auto[0]

auto[0]

auto[0]

398

1

T2

2

T4

2

T13

1

clear_one[3]

auto[0]

auto[1]

auto[0]

142

1

T125

1

T209

1

T75

1

clear_one[3]

auto[1]

auto[0]

auto[0]

121

1

T26

1

T124

1

T217

2

clear_one[3]

auto[1]

auto[1]

auto[0]

36

1

T23

2

T197

1

T110

3

clear_none

auto[0]

auto[0]

auto[0]

1342

1

T2

1

T3

2

T4

1

clear_none

auto[0]

auto[0]

auto[1]

123

1

T4

2

T13

3

T42

3

clear_none

auto[0]

auto[1]

auto[0]

140

1

T3

2

T88

1

T101

2

clear_none

auto[0]

auto[1]

auto[1]

38

1

T42

1

T18

2

T107

1

clear_none

auto[1]

auto[0]

auto[0]

140

1

T33

2

T26

1

T217

1

clear_none

auto[1]

auto[0]

auto[1]

19

1

T136

1

T202

1

T111

2

clear_none

auto[1]

auto[1]

auto[0]

41

1

T126

1

T110

4

T356

3

clear_none

auto[1]

auto[1]

auto[1]

30

1

T136

1

T108

1

T110

5

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1327	1			T2	1		T3	2		T4	1
clear_all	auto[1]	83	1			T42	1		T88	1		T109	6
clear_one[1]	auto[0]	651	1			T3	2		T4	1		T5	1
clear_one[1]	auto[1]	35	1			T42	1		T110	1		T255	2
clear_one[2]	auto[0]	650	1			T3	1		T4	2		T13	2
clear_one[2]	auto[1]	33	1			T128	2		T110	2		T255	2
clear_one[3]	auto[0]	670	1			T2	2		T4	2		T13	1
clear_one[3]	auto[1]	27	1			T42	3		T88	3		T110	4
clear_none	auto[0]	1780	1			T2	1		T3	4		T4	3
clear_none	auto[1]	93	1			T42	2		T88	2		T106	3