Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10961

1

T1

5

T2

3

T3

6

auto[Attestation]

7743

1

T1

3

T2

5

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2769	1			T1	1		T5	1		T16	4
auto[Aes]	3335	1			T1	1		T2	1		T16	2
auto[Kmac]	3379	1			T2	2		T3	10		T5	2
auto[Otbn]	3408	1			T1	4		T2	3		T4	11

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7660	1			T1	8		T2	8		T3	8
auto[OpGenId]	5813	1			T1	2		T2	2		T5	4
auto[OpGenSwOut]	5927	1			T1	6		T2	4		T5	3
auto[OpGenHwOut]	6964	1			T2	2		T3	10		T4	11
auto[OpDisable]	164	1			T5	1		T126	1		T66	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10739

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

15789

1

T1

8

T2

8

T3

10

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6347	1			T1	1		T2	1		T3	3
auto[StInit]	3719	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3290	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2784	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2468	1			T1	2		T2	2		T3	2
auto[StDisabled]	7920	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	306	1			T88	1		T36	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	90	1			T17	1		T78	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T69	2		T71	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	77	1			T16	1		T42	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T26	1		T40	1		T136	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	218	1			T1	1		T80	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	303	1			T42	1		T17	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	107	1			T26	1		T71	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T66	1		T209	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	67	1			T70	1		T197	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	68	1			T35	2		T40	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	214	1			T1	1		T2	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	338	1			T88	1		T27	4		T209	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	88	1			T17	1		T211	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T5	1		T43	1		T69	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T17	1		T80	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	56	1			T136	1		T212	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	230	1			T16	1		T26	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	319	1			T17	1		T88	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	98	1			T17	1		T126	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T1	1		T213	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T26	1		T66	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T88	1		T18	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	227	1			T1	1		T2	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T69	4		T95	1		T111	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T5	1		T80	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	90	1			T88	1		T27	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T214	1		T70	1		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T66	1		T69	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	204	1			T88	1		T18	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	94	1			T36	2		T69	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	96	1			T26	1		T215	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	89	1			T35	1		T66	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T18	1		T27	1		T136	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T18	1		T40	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	224	1			T16	1		T42	2		T126	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T69	1		T71	1		T108	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	90	1			T16	1		T34	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	70	1			T205	1		T93	1		T190	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T35	1		T70	2		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	70	1			T35	1		T88	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	236	1			T2	1		T16	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	93	1			T36	2		T69	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	111	1			T2	1		T35	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T5	1		T43	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T34	1		T106	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	72	1			T1	1		T80	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	223	1			T1	1		T42	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	267	1			T17	2		T66	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	101	1			T34	1		T18	2		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T70	1		T131	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T16	1		T70	1		T132	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	70	1			T26	1		T35	1		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	200	1			T16	2		T26	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	384	1			T33	15		T17	2		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	129	1			T43	1		T217	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	119	1			T16	1		T33	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	109	1			T33	1		T26	1		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	88	1			T217	1		T40	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	274	1			T33	2		T124	1		T217	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	472	1			T3	2		T17	1		T125	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	96	1			T17	1		T124	1		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	134	1			T3	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T125	1		T35	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	89	1			T2	1		T3	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	281	1			T3	2		T125	4		T101	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	478	1			T4	3		T13	2		T66	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	117	1			T13	1		T26	1		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	98	1			T215	1		T35	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T13	1		T16	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	73	1			T4	1		T13	1		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	272	1			T4	2		T13	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T36	1		T71	2		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	96	1			T34	1		T66	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T126	1		T70	3		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T26	1		T144	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T27	1		T70	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	177	1			T27	1		T136	1		T69	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	68	1			T71	1		T218	2		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T33	1		T18	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	112	1			T43	1		T34	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T217	1		T136	2		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	85	1			T33	1		T124	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	275	1			T33	2		T26	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	63	1			T71	2		T108	1		T218	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T3	1		T17	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T43	1		T124	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T3	1		T88	1		T101	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T42	1		T101	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	255	1			T3	2		T18	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T108	1		T218	1		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T4	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	121	1			T4	1		T13	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T2	1		T4	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	89	1			T18	1		T105	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	281	1			T4	2		T13	3		T16	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	206	1			T16	1		T26	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	628	1			T1	1		T17	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T35	2		T66	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	640	1			T1	1		T2	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	197	1			T5	1		T43	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	673	1			T16	1		T26	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	214	1			T1	1		T26	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	656	1			T1	1		T2	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	203	1			T88	1		T66	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	423	1			T5	1		T80	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	203	1			T35	1		T18	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	434	1			T16	1		T26	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	184	1			T35	2		T88	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	422	1			T2	1		T16	2		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T1	1		T5	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	450	1			T1	1		T2	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	179	1			T16	1		T26	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	589	1			T16	2		T26	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	296	1			T16	1		T33	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	807	1			T33	17		T43	1		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	304	1			T2	1		T3	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	865	1			T3	4		T17	2		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	237	1			T4	1		T13	2		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	885	1			T4	5		T13	4		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	185	1			T26	1		T126	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	356	1			T34	1		T66	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	274	1			T33	1		T43	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	480	1			T33	3		T26	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T3	1		T42	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	457	1			T3	3		T17	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	284	1			T2	1		T4	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	489	1			T4	3		T13	3		T5	1