Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32691

1

T1

19

T2

17

T3

22

auto[1]

261

1

T42

5

T88

4

T106

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32696	1			T1	19		T2	17		T3	22
auto[134217728:268435455]	9	1			T110	2		T356	1		T114	1
auto[268435456:402653183]	7	1			T285	1		T112	1		T273	1
auto[402653184:536870911]	8	1			T42	1		T88	1		T106	1
auto[536870912:671088639]	9	1			T110	1		T285	1		T356	1
auto[671088640:805306367]	5	1			T88	1		T106	1		T114	1
auto[805306368:939524095]	9	1			T110	2		T112	1		T351	1
auto[939524096:1073741823]	8	1			T42	1		T281	1		T114	1
auto[1073741824:1207959551]	8	1			T110	1		T410	2		T313	1
auto[1207959552:1342177279]	7	1			T42	1		T110	1		T351	1
auto[1342177280:1476395007]	6	1			T110	1		T255	1		T410	1
auto[1476395008:1610612735]	9	1			T110	1		T356	1		T398	1
auto[1610612736:1744830463]	6	1			T110	1		T351	1		T248	1
auto[1744830464:1879048191]	10	1			T109	1		T285	1		T248	1
auto[1879048192:2013265919]	7	1			T255	1		T285	2		T281	1
auto[2013265920:2147483647]	4	1			T88	1		T426	1		T427	1
auto[2147483648:2281701375]	3	1			T359	1		T428	1		T429	1
auto[2281701376:2415919103]	12	1			T88	1		T110	2		T285	1
auto[2415919104:2550136831]	13	1			T285	1		T114	1		T426	4
auto[2550136832:2684354559]	8	1			T114	1		T430	1		T431	1
auto[2684354560:2818572287]	15	1			T42	1		T106	1		T110	2
auto[2818572288:2952790015]	9	1			T106	1		T109	1		T285	2
auto[2952790016:3087007743]	10	1			T285	1		T296	3		T248	2
auto[3087007744:3221225471]	13	1			T128	1		T110	2		T281	1
auto[3221225472:3355443199]	8	1			T42	1		T109	1		T114	1
auto[3355443200:3489660927]	6	1			T110	1		T432	1		T433	1
auto[3489660928:3623878655]	6	1			T285	1		T281	1		T273	1
auto[3623878656:3758096383]	6	1			T106	1		T255	1		T434	1
auto[3758096384:3892314111]	13	1			T255	1		T285	1		T356	1
auto[3892314112:4026531839]	12	1			T109	1		T285	1		T313	1
auto[4026531840:4160749567]	4	1			T110	2		T433	1		T435	1
auto[4160749568:4294967295]	6	1			T296	1		T434	1		T436	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32691	1			T1	19		T2	17		T3	22
auto[0:134217727]	auto[1]	5	1			T410	1		T296	1		T398	1
auto[134217728:268435455]	auto[1]	9	1			T110	2		T356	1		T114	1
auto[268435456:402653183]	auto[1]	7	1			T285	1		T112	1		T273	1
auto[402653184:536870911]	auto[1]	8	1			T42	1		T88	1		T106	1
auto[536870912:671088639]	auto[1]	9	1			T110	1		T285	1		T356	1
auto[671088640:805306367]	auto[1]	5	1			T88	1		T106	1		T114	1
auto[805306368:939524095]	auto[1]	9	1			T110	2		T112	1		T351	1
auto[939524096:1073741823]	auto[1]	8	1			T42	1		T281	1		T114	1
auto[1073741824:1207959551]	auto[1]	8	1			T110	1		T410	2		T313	1
auto[1207959552:1342177279]	auto[1]	7	1			T42	1		T110	1		T351	1
auto[1342177280:1476395007]	auto[1]	6	1			T110	1		T255	1		T410	1
auto[1476395008:1610612735]	auto[1]	9	1			T110	1		T356	1		T398	1
auto[1610612736:1744830463]	auto[1]	6	1			T110	1		T351	1		T248	1
auto[1744830464:1879048191]	auto[1]	10	1			T109	1		T285	1		T248	1
auto[1879048192:2013265919]	auto[1]	7	1			T255	1		T285	2		T281	1
auto[2013265920:2147483647]	auto[1]	4	1			T88	1		T426	1		T427	1
auto[2147483648:2281701375]	auto[1]	3	1			T359	1		T428	1		T429	1
auto[2281701376:2415919103]	auto[1]	12	1			T88	1		T110	2		T285	1
auto[2415919104:2550136831]	auto[1]	13	1			T285	1		T114	1		T426	4
auto[2550136832:2684354559]	auto[1]	8	1			T114	1		T430	1		T431	1
auto[2684354560:2818572287]	auto[1]	15	1			T42	1		T106	1		T110	2
auto[2818572288:2952790015]	auto[1]	9	1			T106	1		T109	1		T285	2
auto[2952790016:3087007743]	auto[1]	10	1			T285	1		T296	3		T248	2
auto[3087007744:3221225471]	auto[1]	13	1			T128	1		T110	2		T281	1
auto[3221225472:3355443199]	auto[1]	8	1			T42	1		T109	1		T114	1
auto[3355443200:3489660927]	auto[1]	6	1			T110	1		T432	1		T433	1
auto[3489660928:3623878655]	auto[1]	6	1			T285	1		T281	1		T273	1
auto[3623878656:3758096383]	auto[1]	6	1			T106	1		T255	1		T434	1
auto[3758096384:3892314111]	auto[1]	13	1			T255	1		T285	1		T356	1
auto[3892314112:4026531839]	auto[1]	12	1			T109	1		T285	1		T313	1
auto[4026531840:4160749567]	auto[1]	4	1			T110	2		T433	1		T435	1
auto[4160749568:4294967295]	auto[1]	6	1			T296	1		T434	1		T436	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1586

1

T6

2

T14

2

T16

1

auto[1]

1852

1

T6

2

T5

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	80	1			T5	1		T215	1		T68	1
auto[134217728:268435455]	114	1			T14	1		T17	1		T71	2
auto[268435456:402653183]	106	1			T26	1		T36	1		T20	1
auto[402653184:536870911]	98	1			T107	1		T136	1		T9	1
auto[536870912:671088639]	119	1			T88	1		T18	1		T100	1
auto[671088640:805306367]	107	1			T5	1		T27	1		T139	2
auto[805306368:939524095]	99	1			T106	1		T136	1		T68	1
auto[939524096:1073741823]	111	1			T14	1		T17	1		T18	1
auto[1073741824:1207959551]	100	1			T88	1		T70	1		T212	1
auto[1207959552:1342177279]	124	1			T215	1		T88	1		T36	1
auto[1342177280:1476395007]	121	1			T42	1		T36	1		T19	1
auto[1476395008:1610612735]	105	1			T6	1		T42	1		T106	1
auto[1610612736:1744830463]	106	1			T26	2		T27	1		T46	1
auto[1744830464:1879048191]	89	1			T18	1		T100	1		T36	1
auto[1879048192:2013265919]	109	1			T100	1		T36	1		T129	1
auto[2013265920:2147483647]	121	1			T14	1		T88	1		T19	1
auto[2147483648:2281701375]	117	1			T36	1		T27	1		T68	2
auto[2281701376:2415919103]	100	1			T46	1		T197	1		T203	1
auto[2415919104:2550136831]	97	1			T100	1		T106	1		T136	1
auto[2550136832:2684354559]	102	1			T16	1		T17	1		T126	1
auto[2684354560:2818572287]	130	1			T6	1		T88	1		T106	1
auto[2818572288:2952790015]	94	1			T14	1		T387	1		T108	2
auto[2952790016:3087007743]	98	1			T74	1		T75	2		T208	1
auto[3087007744:3221225471]	123	1			T14	1		T42	1		T43	1
auto[3221225472:3355443199]	105	1			T15	1		T42	1		T127	2
auto[3355443200:3489660927]	123	1			T6	1		T15	1		T136	1
auto[3489660928:3623878655]	102	1			T36	1		T136	1		T209	1
auto[3623878656:3758096383]	91	1			T36	1		T27	1		T69	1
auto[3758096384:3892314111]	98	1			T127	1		T88	1		T18	1
auto[3892314112:4026531839]	126	1			T17	1		T126	1		T213	1
auto[4026531840:4160749567]	102	1			T42	1		T126	1		T71	2
auto[4160749568:4294967295]	121	1			T6	1		T18	2		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30	1			T68	1		T70	1		T111	1
auto[0:134217727]	auto[1]	50	1			T5	1		T215	1		T76	1
auto[134217728:268435455]	auto[0]	44	1			T17	1		T71	1		T23	1
auto[134217728:268435455]	auto[1]	70	1			T14	1		T71	1		T214	1
auto[268435456:402653183]	auto[0]	41	1			T36	1		T71	1		T387	1
auto[268435456:402653183]	auto[1]	65	1			T26	1		T20	1		T69	1
auto[402653184:536870911]	auto[0]	49	1			T108	1		T109	1		T420	1
auto[402653184:536870911]	auto[1]	49	1			T107	1		T136	1		T9	1
auto[536870912:671088639]	auto[0]	60	1			T88	1		T18	1		T75	1
auto[536870912:671088639]	auto[1]	59	1			T100	1		T205	1		T110	2
auto[671088640:805306367]	auto[0]	51	1			T139	1		T129	1		T108	1
auto[671088640:805306367]	auto[1]	56	1			T5	1		T27	1		T139	1
auto[805306368:939524095]	auto[0]	49	1			T106	1		T68	1		T71	1
auto[805306368:939524095]	auto[1]	50	1			T136	1		T71	1		T48	1
auto[939524096:1073741823]	auto[0]	51	1			T23	1		T49	1		T252	1
auto[939524096:1073741823]	auto[1]	60	1			T14	1		T17	1		T18	1
auto[1073741824:1207959551]	auto[0]	41	1			T88	1		T212	1		T190	1
auto[1073741824:1207959551]	auto[1]	59	1			T70	1		T108	2		T93	1
auto[1207959552:1342177279]	auto[0]	49	1			T266	1		T289	1		T95	1
auto[1207959552:1342177279]	auto[1]	75	1			T215	1		T88	1		T36	1
auto[1342177280:1476395007]	auto[0]	62	1			T42	1		T36	1		T209	1
auto[1342177280:1476395007]	auto[1]	59	1			T19	1		T46	1		T70	1
auto[1476395008:1610612735]	auto[0]	48	1			T6	1		T106	1		T46	1
auto[1476395008:1610612735]	auto[1]	57	1			T42	1		T69	1		T75	1
auto[1610612736:1744830463]	auto[0]	47	1			T27	1		T46	1		T108	1
auto[1610612736:1744830463]	auto[1]	59	1			T26	2		T69	1		T128	2
auto[1744830464:1879048191]	auto[0]	42	1			T18	1		T100	1		T266	1
auto[1744830464:1879048191]	auto[1]	47	1			T36	1		T69	1		T111	1
auto[1879048192:2013265919]	auto[0]	47	1			T100	1		T36	1		T216	1
auto[1879048192:2013265919]	auto[1]	62	1			T129	1		T108	2		T134	1
auto[2013265920:2147483647]	auto[0]	59	1			T19	1		T70	1		T130	1
auto[2013265920:2147483647]	auto[1]	62	1			T14	1		T88	1		T107	1
auto[2147483648:2281701375]	auto[0]	59	1			T36	1		T68	2		T69	1
auto[2147483648:2281701375]	auto[1]	58	1			T27	1		T144	1		T252	1
auto[2281701376:2415919103]	auto[0]	49	1			T197	1		T203	1		T133	1
auto[2281701376:2415919103]	auto[1]	51	1			T46	1		T356	1		T28	1
auto[2415919104:2550136831]	auto[0]	42	1			T68	1		T46	1		T214	1
auto[2415919104:2550136831]	auto[1]	55	1			T100	1		T106	1		T136	1
auto[2550136832:2684354559]	auto[0]	52	1			T16	1		T17	1		T126	1
auto[2550136832:2684354559]	auto[1]	50	1			T103	1		T70	1		T203	1
auto[2684354560:2818572287]	auto[0]	65	1			T88	1		T129	1		T44	1
auto[2684354560:2818572287]	auto[1]	65	1			T6	1		T106	1		T69	1
auto[2818572288:2952790015]	auto[0]	50	1			T14	1		T108	1		T111	1
auto[2818572288:2952790015]	auto[1]	44	1			T387	1		T108	1		T290	1
auto[2952790016:3087007743]	auto[0]	37	1			T75	1		T44	1		T133	1
auto[2952790016:3087007743]	auto[1]	61	1			T74	1		T75	1		T208	1
auto[3087007744:3221225471]	auto[0]	58	1			T14	1		T134	1		T203	1
auto[3087007744:3221225471]	auto[1]	65	1			T42	1		T43	1		T126	1
auto[3221225472:3355443199]	auto[0]	55	1			T42	1		T127	1		T36	1
auto[3221225472:3355443199]	auto[1]	50	1			T15	1		T127	1		T70	1
auto[3355443200:3489660927]	auto[0]	56	1			T23	1		T7	1		T129	1
auto[3355443200:3489660927]	auto[1]	67	1			T6	1		T15	1		T136	1
auto[3489660928:3623878655]	auto[0]	46	1			T36	1		T209	1		T49	1
auto[3489660928:3623878655]	auto[1]	56	1			T136	1		T93	1		T111	3
auto[3623878656:3758096383]	auto[0]	43	1			T36	1		T69	1		T139	1
auto[3623878656:3758096383]	auto[1]	48	1			T27	1		T70	2		T251	1
auto[3758096384:3892314111]	auto[0]	39	1			T127	1		T70	1		T216	1
auto[3758096384:3892314111]	auto[1]	59	1			T88	1		T18	1		T216	1
auto[3892314112:4026531839]	auto[0]	63	1			T144	1		T197	1		T44	1
auto[3892314112:4026531839]	auto[1]	63	1			T17	1		T126	1		T213	1
auto[4026531840:4160749567]	auto[0]	47	1			T42	1		T71	1		T23	1
auto[4026531840:4160749567]	auto[1]	55	1			T126	1		T71	1		T108	1
auto[4160749568:4294967295]	auto[0]	55	1			T6	1		T49	1		T205	1
auto[4160749568:4294967295]	auto[1]	66	1			T18	2		T27	1		T71	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1594

1

T6

3

T14

2

T15

1

auto[1]

1844

1

T6

1

T5

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T5	1		T27	1		T136	1
auto[134217728:268435455]	104	1			T14	1		T36	1		T68	1
auto[268435456:402653183]	116	1			T126	1		T136	1		T69	1
auto[402653184:536870911]	102	1			T46	1		T7	1		T144	1
auto[536870912:671088639]	105	1			T17	1		T215	1		T88	1
auto[671088640:805306367]	108	1			T17	1		T88	1		T106	1
auto[805306368:939524095]	96	1			T69	1		T108	1		T290	1
auto[939524096:1073741823]	129	1			T136	1		T266	1		T48	1
auto[1073741824:1207959551]	110	1			T100	1		T71	1		T70	1
auto[1207959552:1342177279]	114	1			T88	1		T20	1		T129	2
auto[1342177280:1476395007]	120	1			T6	1		T46	1		T71	1
auto[1476395008:1610612735]	112	1			T42	1		T100	1		T19	1
auto[1610612736:1744830463]	95	1			T26	1		T69	1		T203	1
auto[1744830464:1879048191]	94	1			T14	1		T36	1		T74	1
auto[1879048192:2013265919]	109	1			T14	1		T214	1		T139	1
auto[2013265920:2147483647]	102	1			T42	1		T68	1		T71	1
auto[2147483648:2281701375]	113	1			T126	1		T127	1		T18	1
auto[2281701376:2415919103]	106	1			T5	1		T16	1		T26	1
auto[2415919104:2550136831]	106	1			T15	1		T42	1		T17	1
auto[2550136832:2684354559]	111	1			T18	1		T100	1		T251	1
auto[2684354560:2818572287]	109	1			T36	2		T209	1		T75	1
auto[2818572288:2952790015]	102	1			T46	1		T214	1		T134	1
auto[2952790016:3087007743]	103	1			T19	1		T107	1		T69	1
auto[3087007744:3221225471]	103	1			T6	1		T14	1		T17	1
auto[3221225472:3355443199]	114	1			T26	1		T18	1		T107	1
auto[3355443200:3489660927]	104	1			T15	1		T42	1		T9	1
auto[3489660928:3623878655]	122	1			T14	1		T88	1		T36	1
auto[3623878656:3758096383]	84	1			T6	1		T36	3		T71	2
auto[3758096384:3892314111]	85	1			T6	1		T106	2		T107	1
auto[3892314112:4026531839]	113	1			T43	1		T127	1		T36	1
auto[4026531840:4160749567]	121	1			T42	1		T88	1		T75	1
auto[4160749568:4294967295]	124	1			T127	1		T88	1		T18	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T71	1		T75	1		T23	1
auto[0:134217727]	auto[1]	53	1			T5	1		T27	1		T136	1
auto[134217728:268435455]	auto[0]	48	1			T36	1		T68	1		T49	1
auto[134217728:268435455]	auto[1]	56	1			T14	1		T71	1		T134	1
auto[268435456:402653183]	auto[0]	48	1			T129	1		T205	1		T137	1
auto[268435456:402653183]	auto[1]	68	1			T126	1		T136	1		T69	1
auto[402653184:536870911]	auto[0]	45	1			T46	1		T7	1		T48	1
auto[402653184:536870911]	auto[1]	57	1			T144	1		T108	1		T390	1
auto[536870912:671088639]	auto[0]	46	1			T17	1		T88	1		T290	1
auto[536870912:671088639]	auto[1]	59	1			T215	1		T18	1		T108	1
auto[671088640:805306367]	auto[0]	55	1			T88	1		T106	1		T68	1
auto[671088640:805306367]	auto[1]	53	1			T17	1		T27	1		T70	2
auto[805306368:939524095]	auto[0]	48	1			T108	1		T290	1		T44	1
auto[805306368:939524095]	auto[1]	48	1			T69	1		T188	1		T192	1
auto[939524096:1073741823]	auto[0]	63	1			T48	1		T108	1		T197	1
auto[939524096:1073741823]	auto[1]	66	1			T136	1		T266	1		T108	2
auto[1073741824:1207959551]	auto[0]	42	1			T266	1		T108	1		T203	1
auto[1073741824:1207959551]	auto[1]	68	1			T100	1		T71	1		T70	1
auto[1207959552:1342177279]	auto[0]	49	1			T129	2		T108	1		T197	1
auto[1207959552:1342177279]	auto[1]	65	1			T88	1		T20	1		T213	1
auto[1342177280:1476395007]	auto[0]	63	1			T6	1		T71	1		T23	1
auto[1342177280:1476395007]	auto[1]	57	1			T46	1		T216	1		T108	2
auto[1476395008:1610612735]	auto[0]	56	1			T42	1		T106	1		T69	1
auto[1476395008:1610612735]	auto[1]	56	1			T100	1		T19	1		T27	1
auto[1610612736:1744830463]	auto[0]	42	1			T203	1		T44	1		T93	1
auto[1610612736:1744830463]	auto[1]	53	1			T26	1		T69	1		T205	1
auto[1744830464:1879048191]	auto[0]	51	1			T36	1		T74	1		T203	1
auto[1744830464:1879048191]	auto[1]	43	1			T14	1		T75	1		T212	1
auto[1879048192:2013265919]	auto[0]	44	1			T14	1		T139	1		T128	1
auto[1879048192:2013265919]	auto[1]	65	1			T214	1		T387	1		T111	2
auto[2013265920:2147483647]	auto[0]	44	1			T42	1		T68	1		T139	1
auto[2013265920:2147483647]	auto[1]	58	1			T71	1		T139	1		T266	1
auto[2147483648:2281701375]	auto[0]	61	1			T126	1		T252	1		T134	1
auto[2147483648:2281701375]	auto[1]	52	1			T127	1		T18	1		T70	1
auto[2281701376:2415919103]	auto[0]	36	1			T209	1		T69	1		T8	1
auto[2281701376:2415919103]	auto[1]	70	1			T5	1		T16	1		T26	1
auto[2415919104:2550136831]	auto[0]	46	1			T15	1		T266	1		T290	1
auto[2415919104:2550136831]	auto[1]	60	1			T42	1		T17	1		T126	1
auto[2550136832:2684354559]	auto[0]	56	1			T100	1		T7	1		T108	1
auto[2550136832:2684354559]	auto[1]	55	1			T18	1		T251	1		T108	1
auto[2684354560:2818572287]	auto[0]	49	1			T36	2		T209	1		T75	1
auto[2684354560:2818572287]	auto[1]	60	1			T70	1		T7	1		T412	1
auto[2818572288:2952790015]	auto[0]	46	1			T134	1		T190	1		T137	1
auto[2818572288:2952790015]	auto[1]	56	1			T46	1		T214	1		T437	1
auto[2952790016:3087007743]	auto[0]	49	1			T192	1		T289	1		T228	1
auto[2952790016:3087007743]	auto[1]	54	1			T19	1		T107	1		T69	1
auto[3087007744:3221225471]	auto[0]	49	1			T6	1		T17	1		T27	1
auto[3087007744:3221225471]	auto[1]	54	1			T14	1		T18	1		T136	1
auto[3221225472:3355443199]	auto[0]	51	1			T18	1		T107	1		T68	1
auto[3221225472:3355443199]	auto[1]	63	1			T26	1		T139	1		T144	1
auto[3355443200:3489660927]	auto[0]	48	1			T214	1		T133	2		T190	1
auto[3355443200:3489660927]	auto[1]	56	1			T15	1		T42	1		T9	1
auto[3489660928:3623878655]	auto[0]	51	1			T14	1		T88	1		T130	1
auto[3489660928:3623878655]	auto[1]	71	1			T36	1		T103	1		T69	2
auto[3623878656:3758096383]	auto[0]	41	1			T6	1		T36	3		T71	1
auto[3623878656:3758096383]	auto[1]	43	1			T71	1		T205	1		T110	1
auto[3758096384:3892314111]	auto[0]	47	1			T107	1		T68	1		T46	1
auto[3758096384:3892314111]	auto[1]	38	1			T6	1		T106	2		T27	1
auto[3892314112:4026531839]	auto[0]	50	1			T36	1		T70	1		T109	1
auto[3892314112:4026531839]	auto[1]	63	1			T43	1		T127	1		T76	1
auto[4026531840:4160749567]	auto[0]	58	1			T42	1		T49	1		T189	1
auto[4026531840:4160749567]	auto[1]	63	1			T88	1		T75	1		T139	1
auto[4160749568:4294967295]	auto[0]	63	1			T127	1		T100	1		T46	1
auto[4160749568:4294967295]	auto[1]	61	1			T88	1		T18	1		T128	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1598

1

T6

2

T14

3

T16

1

auto[1]

1840

1

T6

2

T5

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T17	2		T68	1		T69	1
auto[134217728:268435455]	114	1			T88	1		T212	1		T23	1
auto[268435456:402653183]	104	1			T106	1		T208	1		T212	1
auto[402653184:536870911]	94	1			T16	1		T42	1		T139	1
auto[536870912:671088639]	104	1			T126	1		T100	1		T19	1
auto[671088640:805306367]	82	1			T14	2		T106	1		T68	1
auto[805306368:939524095]	100	1			T42	1		T43	1		T36	1
auto[939524096:1073741823]	90	1			T6	1		T209	1		T68	1
auto[1073741824:1207959551]	112	1			T42	1		T18	1		T251	1
auto[1207959552:1342177279]	107	1			T215	1		T70	1		T7	1
auto[1342177280:1476395007]	112	1			T136	1		T71	1		T214	1
auto[1476395008:1610612735]	113	1			T88	1		T68	1		T70	1
auto[1610612736:1744830463]	113	1			T70	1		T48	1		T108	2
auto[1744830464:1879048191]	86	1			T14	1		T36	1		T107	1
auto[1879048192:2013265919]	98	1			T36	1		T27	1		T46	1
auto[2013265920:2147483647]	108	1			T36	1		T70	1		T212	1
auto[2147483648:2281701375]	112	1			T88	1		T107	1		T70	1
auto[2281701376:2415919103]	95	1			T14	1		T106	1		T108	3
auto[2415919104:2550136831]	108	1			T26	1		T17	1		T88	1
auto[2550136832:2684354559]	100	1			T6	1		T215	1		T136	1
auto[2684354560:2818572287]	97	1			T15	1		T26	1		T42	1
auto[2818572288:2952790015]	125	1			T18	1		T69	1		T74	1
auto[2952790016:3087007743]	120	1			T36	2		T106	1		T46	1
auto[3087007744:3221225471]	114	1			T126	1		T136	1		T68	1
auto[3221225472:3355443199]	103	1			T100	1		T139	1		T108	1
auto[3355443200:3489660927]	115	1			T6	1		T5	1		T14	1
auto[3489660928:3623878655]	121	1			T88	1		T103	1		T214	1
auto[3623878656:3758096383]	104	1			T5	1		T15	1		T36	1
auto[3758096384:3892314111]	92	1			T42	1		T88	1		T100	1
auto[3892314112:4026531839]	137	1			T127	1		T18	2		T100	1
auto[4026531840:4160749567]	112	1			T127	1		T27	2		T70	1
auto[4160749568:4294967295]	133	1			T6	1		T26	1		T17	1