Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1592

1

T6

2

T14

3

T15

1

auto[1]

1846

1

T6

2

T5

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T43	1		T36	2		T27	1
auto[134217728:268435455]	106	1			T18	1		T36	3		T19	1
auto[268435456:402653183]	102	1			T42	1		T106	1		T74	1
auto[402653184:536870911]	104	1			T14	1		T15	1		T126	1
auto[536870912:671088639]	120	1			T14	2		T215	1		T46	1
auto[671088640:805306367]	99	1			T6	1		T126	1		T27	1
auto[805306368:939524095]	99	1			T19	1		T27	1		T71	1
auto[939524096:1073741823]	90	1			T100	1		T107	1		T136	1
auto[1073741824:1207959551]	111	1			T14	1		T18	2		T108	2
auto[1207959552:1342177279]	121	1			T88	1		T71	1		T9	1
auto[1342177280:1476395007]	104	1			T18	1		T106	1		T68	1
auto[1476395008:1610612735]	113	1			T36	1		T68	1		T70	1
auto[1610612736:1744830463]	104	1			T42	1		T437	1		T93	1
auto[1744830464:1879048191]	111	1			T26	1		T126	1		T100	1
auto[1879048192:2013265919]	105	1			T14	1		T17	1		T127	1
auto[2013265920:2147483647]	128	1			T6	1		T17	1		T27	1
auto[2147483648:2281701375]	109	1			T6	1		T26	1		T7	1
auto[2281701376:2415919103]	95	1			T88	1		T75	1		T128	1
auto[2415919104:2550136831]	105	1			T6	1		T18	1		T107	1
auto[2550136832:2684354559]	91	1			T42	1		T103	1		T209	1
auto[2684354560:2818572287]	123	1			T27	1		T46	1		T139	1
auto[2818572288:2952790015]	112	1			T5	1		T127	2		T20	1
auto[2952790016:3087007743]	113	1			T215	1		T136	1		T71	1
auto[3087007744:3221225471]	97	1			T126	1		T88	1		T136	1
auto[3221225472:3355443199]	102	1			T88	1		T69	1		T71	1
auto[3355443200:3489660927]	115	1			T17	2		T107	1		T46	1
auto[3489660928:3623878655]	98	1			T42	1		T209	1		T68	1
auto[3623878656:3758096383]	124	1			T15	1		T88	1		T18	1
auto[3758096384:3892314111]	111	1			T36	1		T106	2		T212	1
auto[3892314112:4026531839]	104	1			T5	1		T36	1		T69	1
auto[4026531840:4160749567]	118	1			T100	1		T136	1		T70	1
auto[4160749568:4294967295]	105	1			T16	1		T26	1		T42	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T36	2		T68	1		T46	1
auto[0:134217727]	auto[1]	53	1			T43	1		T27	1		T136	1
auto[134217728:268435455]	auto[0]	40	1			T36	2		T46	1		T214	1
auto[134217728:268435455]	auto[1]	66	1			T18	1		T36	1		T19	1
auto[268435456:402653183]	auto[0]	55	1			T42	1		T106	1		T108	1
auto[268435456:402653183]	auto[1]	47	1			T74	1		T213	1		T93	3
auto[402653184:536870911]	auto[0]	45	1			T23	1		T108	2		T289	1
auto[402653184:536870911]	auto[1]	59	1			T14	1		T15	1		T126	1
auto[536870912:671088639]	auto[0]	49	1			T14	1		T46	1		T129	1
auto[536870912:671088639]	auto[1]	71	1			T14	1		T215	1		T108	1
auto[671088640:805306367]	auto[0]	42	1			T387	1		T137	1		T420	1
auto[671088640:805306367]	auto[1]	57	1			T6	1		T126	1		T27	1
auto[805306368:939524095]	auto[0]	56	1			T27	1		T266	1		T216	1
auto[805306368:939524095]	auto[1]	43	1			T19	1		T71	1		T412	1
auto[939524096:1073741823]	auto[0]	47	1			T100	1		T70	1		T7	1
auto[939524096:1073741823]	auto[1]	43	1			T107	1		T136	1		T71	1
auto[1073741824:1207959551]	auto[0]	50	1			T14	1		T18	1		T108	1
auto[1073741824:1207959551]	auto[1]	61	1			T18	1		T108	1		T110	1
auto[1207959552:1342177279]	auto[0]	48	1			T88	1		T71	1		T23	1
auto[1207959552:1342177279]	auto[1]	73	1			T9	1		T70	1		T144	1
auto[1342177280:1476395007]	auto[0]	49	1			T106	1		T68	1		T70	1
auto[1342177280:1476395007]	auto[1]	55	1			T18	1		T129	1		T108	1
auto[1476395008:1610612735]	auto[0]	55	1			T36	1		T68	1		T70	1
auto[1476395008:1610612735]	auto[1]	58	1			T216	1		T108	2		T134	1
auto[1610612736:1744830463]	auto[0]	59	1			T42	1		T93	1		T191	1
auto[1610612736:1744830463]	auto[1]	45	1			T437	1		T285	1		T198	1
auto[1744830464:1879048191]	auto[0]	45	1			T100	1		T130	1		T203	1
auto[1744830464:1879048191]	auto[1]	66	1			T26	1		T126	1		T71	1
auto[1879048192:2013265919]	auto[0]	53	1			T14	1		T68	1		T71	1
auto[1879048192:2013265919]	auto[1]	52	1			T17	1		T127	1		T290	1
auto[2013265920:2147483647]	auto[0]	60	1			T6	1		T17	1		T203	1
auto[2013265920:2147483647]	auto[1]	68	1			T27	1		T75	1		T108	1
auto[2147483648:2281701375]	auto[0]	59	1			T6	1		T7	1		T266	1
auto[2147483648:2281701375]	auto[1]	50	1			T26	1		T48	1		T108	1
auto[2281701376:2415919103]	auto[0]	41	1			T88	1		T75	1		T108	1
auto[2281701376:2415919103]	auto[1]	54	1			T128	1		T290	1		T218	1
auto[2415919104:2550136831]	auto[0]	53	1			T18	1		T139	1		T387	1
auto[2415919104:2550136831]	auto[1]	52	1			T6	1		T107	1		T69	1
auto[2550136832:2684354559]	auto[0]	47	1			T42	1		T209	1		T69	1
auto[2550136832:2684354559]	auto[1]	44	1			T103	1		T437	1		T133	1
auto[2684354560:2818572287]	auto[0]	61	1			T49	1		T108	1		T44	2
auto[2684354560:2818572287]	auto[1]	62	1			T27	1		T46	1		T139	1
auto[2818572288:2952790015]	auto[0]	52	1			T127	1		T20	1		T70	1
auto[2818572288:2952790015]	auto[1]	60	1			T5	1		T127	1		T69	1
auto[2952790016:3087007743]	auto[0]	57	1			T71	1		T130	1		T266	1
auto[2952790016:3087007743]	auto[1]	56	1			T215	1		T136	1		T75	1
auto[3087007744:3221225471]	auto[0]	43	1			T108	1		T205	1		T93	1
auto[3087007744:3221225471]	auto[1]	54	1			T126	1		T88	1		T136	1
auto[3221225472:3355443199]	auto[0]	51	1			T88	1		T75	1		T266	1
auto[3221225472:3355443199]	auto[1]	51	1			T69	1		T71	1		T49	1
auto[3355443200:3489660927]	auto[0]	44	1			T17	1		T49	1		T252	1
auto[3355443200:3489660927]	auto[1]	71	1			T17	1		T107	1		T46	1
auto[3489660928:3623878655]	auto[0]	44	1			T209	1		T7	1		T134	1
auto[3489660928:3623878655]	auto[1]	54	1			T42	1		T68	1		T208	1
auto[3623878656:3758096383]	auto[0]	58	1			T15	1		T36	1		T212	1
auto[3623878656:3758096383]	auto[1]	66	1			T88	1		T18	1		T100	1
auto[3758096384:3892314111]	auto[0]	49	1			T36	1		T106	1		T128	1
auto[3758096384:3892314111]	auto[1]	62	1			T106	1		T212	1		T7	1
auto[3892314112:4026531839]	auto[0]	40	1			T108	2		T111	1		T285	1
auto[3892314112:4026531839]	auto[1]	64	1			T5	1		T36	1		T69	1
auto[4026531840:4160749567]	auto[0]	54	1			T93	1		T255	1		T449	1
auto[4026531840:4160749567]	auto[1]	64	1			T100	1		T136	1		T70	1
auto[4160749568:4294967295]	auto[0]	40	1			T42	1		T290	1		T37	1
auto[4160749568:4294967295]	auto[1]	65	1			T16	1		T26	1		T88	1