Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1627

1

T6

3

T14

3

T16

1

auto[1]

1811

1

T6

1

T5

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T42	1		T36	1		T136	1
auto[134217728:268435455]	118	1			T6	1		T88	1		T209	1
auto[268435456:402653183]	112	1			T88	1		T18	1		T7	1
auto[402653184:536870911]	106	1			T76	1		T129	2		T213	1
auto[536870912:671088639]	106	1			T17	1		T46	1		T71	1
auto[671088640:805306367]	92	1			T5	1		T127	1		T136	2
auto[805306368:939524095]	96	1			T15	1		T27	1		T75	1
auto[939524096:1073741823]	99	1			T18	1		T136	1		T71	1
auto[1073741824:1207959551]	103	1			T14	1		T127	1		T19	1
auto[1207959552:1342177279]	106	1			T42	1		T106	1		T136	1
auto[1342177280:1476395007]	129	1			T14	1		T17	1		T100	1
auto[1476395008:1610612735]	121	1			T71	1		T108	1		T109	1
auto[1610612736:1744830463]	106	1			T100	1		T36	1		T7	1
auto[1744830464:1879048191]	124	1			T5	1		T126	1		T27	1
auto[1879048192:2013265919]	112	1			T68	1		T139	1		T7	1
auto[2013265920:2147483647]	88	1			T88	1		T19	1		T74	1
auto[2147483648:2281701375]	117	1			T106	1		T71	1		T128	1
auto[2281701376:2415919103]	87	1			T42	1		T68	1		T46	2
auto[2415919104:2550136831]	96	1			T6	1		T68	1		T23	1
auto[2550136832:2684354559]	92	1			T6	1		T16	1		T126	1
auto[2684354560:2818572287]	104	1			T42	1		T36	1		T70	2
auto[2818572288:2952790015]	110	1			T127	1		T69	1		T70	1
auto[2952790016:3087007743]	117	1			T69	1		T75	1		T23	1
auto[3087007744:3221225471]	90	1			T26	1		T17	1		T106	1
auto[3221225472:3355443199]	104	1			T14	1		T215	1		T36	1
auto[3355443200:3489660927]	116	1			T14	1		T26	1		T18	2
auto[3489660928:3623878655]	115	1			T14	1		T215	1		T18	1
auto[3623878656:3758096383]	112	1			T6	1		T43	1		T36	2
auto[3758096384:3892314111]	126	1			T15	1		T26	1		T88	1
auto[3892314112:4026531839]	116	1			T17	1		T88	1		T100	1
auto[4026531840:4160749567]	112	1			T42	1		T126	1		T103	1
auto[4160749568:4294967295]	92	1			T126	1		T88	1		T106	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T36	1		T46	1		T44	1
auto[0:134217727]	auto[1]	57	1			T42	1		T136	1		T70	1
auto[134217728:268435455]	auto[0]	59	1			T6	1		T88	1		T209	1
auto[134217728:268435455]	auto[1]	59	1			T94	1		T57	1		T253	1
auto[268435456:402653183]	auto[0]	54	1			T7	1		T266	1		T44	1
auto[268435456:402653183]	auto[1]	58	1			T88	1		T18	1		T144	1
auto[402653184:536870911]	auto[0]	54	1			T129	1		T93	2		T189	1
auto[402653184:536870911]	auto[1]	52	1			T76	1		T129	1		T213	1
auto[536870912:671088639]	auto[0]	58	1			T17	1		T46	1		T71	1
auto[536870912:671088639]	auto[1]	48	1			T108	1		T205	1		T133	1
auto[671088640:805306367]	auto[0]	47	1			T139	1		T203	1		T111	1
auto[671088640:805306367]	auto[1]	45	1			T5	1		T127	1		T136	2
auto[805306368:939524095]	auto[0]	42	1			T290	1		T188	1		T190	1
auto[805306368:939524095]	auto[1]	54	1			T15	1		T27	1		T75	1
auto[939524096:1073741823]	auto[0]	42	1			T266	1		T252	1		T189	1
auto[939524096:1073741823]	auto[1]	57	1			T18	1		T136	1		T71	1
auto[1073741824:1207959551]	auto[0]	54	1			T127	1		T70	1		T216	1
auto[1073741824:1207959551]	auto[1]	49	1			T14	1		T19	1		T69	1
auto[1207959552:1342177279]	auto[0]	46	1			T42	1		T106	1		T139	1
auto[1207959552:1342177279]	auto[1]	60	1			T136	1		T213	1		T108	1
auto[1342177280:1476395007]	auto[0]	51	1			T14	1		T100	1		T68	1
auto[1342177280:1476395007]	auto[1]	78	1			T17	1		T27	1		T9	1
auto[1476395008:1610612735]	auto[0]	51	1			T71	1		T108	1		T109	1
auto[1476395008:1610612735]	auto[1]	70	1			T412	1		T93	1		T137	1
auto[1610612736:1744830463]	auto[0]	52	1			T100	1		T36	1		T7	1
auto[1610612736:1744830463]	auto[1]	54	1			T128	1		T266	1		T290	1
auto[1744830464:1879048191]	auto[0]	56	1			T108	1		T109	1		T188	1
auto[1744830464:1879048191]	auto[1]	68	1			T5	1		T126	1		T27	1
auto[1879048192:2013265919]	auto[0]	51	1			T68	1		T44	1		T205	1
auto[1879048192:2013265919]	auto[1]	61	1			T139	1		T7	1		T362	1
auto[2013265920:2147483647]	auto[0]	36	1			T74	1		T420	1		T198	2
auto[2013265920:2147483647]	auto[1]	52	1			T88	1		T19	1		T108	1
auto[2147483648:2281701375]	auto[0]	52	1			T106	1		T128	1		T129	1
auto[2147483648:2281701375]	auto[1]	65	1			T71	1		T108	2		T110	1
auto[2281701376:2415919103]	auto[0]	44	1			T42	1		T68	1		T46	1
auto[2281701376:2415919103]	auto[1]	43	1			T46	1		T216	1		T133	1
auto[2415919104:2550136831]	auto[0]	51	1			T6	1		T68	1		T23	1
auto[2415919104:2550136831]	auto[1]	45	1			T128	1		T49	1		T108	1
auto[2550136832:2684354559]	auto[0]	43	1			T16	1		T75	1		T197	1
auto[2550136832:2684354559]	auto[1]	49	1			T6	1		T126	1		T27	1
auto[2684354560:2818572287]	auto[0]	59	1			T36	1		T70	2		T212	1
auto[2684354560:2818572287]	auto[1]	45	1			T42	1		T94	1		T420	1
auto[2818572288:2952790015]	auto[0]	50	1			T129	1		T95	1		T111	1
auto[2818572288:2952790015]	auto[1]	60	1			T127	1		T69	1		T70	1
auto[2952790016:3087007743]	auto[0]	57	1			T188	1		T137	1		T97	1
auto[2952790016:3087007743]	auto[1]	60	1			T69	1		T75	1		T23	1
auto[3087007744:3221225471]	auto[0]	41	1			T17	1		T108	1		T8	1
auto[3087007744:3221225471]	auto[1]	49	1			T26	1		T106	1		T108	1
auto[3221225472:3355443199]	auto[0]	52	1			T14	1		T70	1		T108	2
auto[3221225472:3355443199]	auto[1]	52	1			T215	1		T36	1		T70	1
auto[3355443200:3489660927]	auto[0]	46	1			T14	1		T130	1		T108	1
auto[3355443200:3489660927]	auto[1]	70	1			T26	1		T18	2		T212	1
auto[3489660928:3623878655]	auto[0]	57	1			T36	1		T20	1		T27	1
auto[3489660928:3623878655]	auto[1]	58	1			T14	1		T215	1		T18	1
auto[3623878656:3758096383]	auto[0]	59	1			T6	1		T36	2		T107	1
auto[3623878656:3758096383]	auto[1]	53	1			T43	1		T107	1		T208	1
auto[3758096384:3892314111]	auto[0]	51	1			T88	1		T36	2		T212	1
auto[3758096384:3892314111]	auto[1]	75	1			T15	1		T26	1		T18	1
auto[3892314112:4026531839]	auto[0]	49	1			T17	1		T88	1		T209	1
auto[3892314112:4026531839]	auto[1]	67	1			T100	1		T69	1		T139	1
auto[4026531840:4160749567]	auto[0]	58	1			T42	1		T126	1		T68	1
auto[4026531840:4160749567]	auto[1]	54	1			T103	1		T70	1		T212	1
auto[4160749568:4294967295]	auto[0]	48	1			T107	1		T75	1		T216	1
auto[4160749568:4294967295]	auto[1]	44	1			T126	1		T88	1		T106	1