Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7170

1

T5

4

T14

16

T15

12

auto[1]

322

1

T42

4

T88

9

T106

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2990	1			T5	2		T14	7		T15	6
auto[134217728:268435455]	183	1			T42	1		T88	1		T70	3
auto[268435456:402653183]	162	1			T103	2		T106	1		T70	2
auto[402653184:536870911]	187	1			T42	1		T18	1		T106	1
auto[536870912:671088639]	159	1			T14	1		T126	1		T18	2
auto[671088640:805306367]	158	1			T15	1		T26	1		T88	2
auto[805306368:939524095]	161	1			T88	1		T19	1		T46	1
auto[939524096:1073741823]	149	1			T14	2		T106	1		T46	1
auto[1073741824:1207959551]	128	1			T46	1		T130	1		T49	1
auto[1207959552:1342177279]	148	1			T14	1		T26	1		T42	1
auto[1342177280:1476395007]	142	1			T15	1		T100	1		T68	1
auto[1476395008:1610612735]	128	1			T42	1		T100	1		T36	1
auto[1610612736:1744830463]	144	1			T15	2		T17	1		T88	1
auto[1744830464:1879048191]	125	1			T88	2		T106	1		T27	1
auto[1879048192:2013265919]	151	1			T42	1		T88	1		T103	1
auto[2013265920:2147483647]	136	1			T100	2		T69	2		T212	1
auto[2147483648:2281701375]	134	1			T126	1		T136	1		T139	1
auto[2281701376:2415919103]	137	1			T100	1		T27	1		T214	2
auto[2415919104:2550136831]	145	1			T5	1		T14	1		T16	1
auto[2550136832:2684354559]	144	1			T16	1		T106	3		T107	1
auto[2684354560:2818572287]	141	1			T14	1		T16	1		T126	1
auto[2818572288:2952790015]	137	1			T42	1		T106	1		T69	1
auto[2952790016:3087007743]	141	1			T5	1		T15	1		T42	1
auto[3087007744:3221225471]	129	1			T42	1		T106	2		T107	1
auto[3221225472:3355443199]	152	1			T14	1		T15	1		T16	1
auto[3355443200:3489660927]	126	1			T42	1		T88	1		T18	1
auto[3489660928:3623878655]	136	1			T17	1		T36	2		T27	2
auto[3623878656:3758096383]	159	1			T14	2		T88	1		T18	1
auto[3758096384:3892314111]	138	1			T18	2		T106	1		T136	1
auto[3892314112:4026531839]	114	1			T26	1		T88	1		T18	1
auto[4026531840:4160749567]	137	1			T16	2		T17	1		T18	1
auto[4160749568:4294967295]	171	1			T16	1		T43	1		T215	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2981	1			T5	2		T14	7		T15	6
auto[0:134217727]	auto[1]	9	1			T112	1		T114	1		T410	1
auto[134217728:268435455]	auto[0]	175	1			T88	1		T70	3		T212	1
auto[134217728:268435455]	auto[1]	8	1			T42	1		T109	2		T110	1
auto[268435456:402653183]	auto[0]	150	1			T103	2		T106	1		T70	2
auto[268435456:402653183]	auto[1]	12	1			T110	1		T273	1		T359	1
auto[402653184:536870911]	auto[0]	175	1			T42	1		T18	1		T27	2
auto[402653184:536870911]	auto[1]	12	1			T106	1		T285	1		T114	1
auto[536870912:671088639]	auto[0]	146	1			T14	1		T126	1		T18	2
auto[536870912:671088639]	auto[1]	13	1			T128	1		T109	1		T285	2
auto[671088640:805306367]	auto[0]	154	1			T15	1		T26	1		T88	1
auto[671088640:805306367]	auto[1]	4	1			T88	1		T110	1		T114	1
auto[805306368:939524095]	auto[0]	146	1			T19	1		T46	1		T139	1
auto[805306368:939524095]	auto[1]	15	1			T88	1		T285	1		T281	1
auto[939524096:1073741823]	auto[0]	135	1			T14	2		T46	1		T70	1
auto[939524096:1073741823]	auto[1]	14	1			T106	1		T285	1		T356	1
auto[1073741824:1207959551]	auto[0]	120	1			T46	1		T130	1		T49	1
auto[1073741824:1207959551]	auto[1]	8	1			T110	1		T285	1		T296	1
auto[1207959552:1342177279]	auto[0]	137	1			T14	1		T26	1		T42	1
auto[1207959552:1342177279]	auto[1]	11	1			T109	1		T110	1		T285	1
auto[1342177280:1476395007]	auto[0]	136	1			T15	1		T100	1		T68	1
auto[1342177280:1476395007]	auto[1]	6	1			T110	1		T410	1		T438	1
auto[1476395008:1610612735]	auto[0]	121	1			T42	1		T100	1		T36	1
auto[1476395008:1610612735]	auto[1]	7	1			T128	1		T273	1		T398	1
auto[1610612736:1744830463]	auto[0]	122	1			T15	2		T17	1		T103	1
auto[1610612736:1744830463]	auto[1]	22	1			T88	1		T106	1		T110	1
auto[1744830464:1879048191]	auto[0]	117	1			T27	1		T128	1		T197	1
auto[1744830464:1879048191]	auto[1]	8	1			T88	2		T106	1		T273	1
auto[1879048192:2013265919]	auto[0]	136	1			T103	1		T106	1		T136	1
auto[1879048192:2013265919]	auto[1]	15	1			T42	1		T88	1		T128	1
auto[2013265920:2147483647]	auto[0]	124	1			T100	2		T69	2		T212	1
auto[2013265920:2147483647]	auto[1]	12	1			T128	2		T110	1		T285	1
auto[2147483648:2281701375]	auto[0]	126	1			T126	1		T136	1		T139	1
auto[2147483648:2281701375]	auto[1]	8	1			T285	1		T398	1		T428	1
auto[2281701376:2415919103]	auto[0]	132	1			T100	1		T27	1		T214	2
auto[2281701376:2415919103]	auto[1]	5	1			T296	1		T273	1		T398	1
auto[2415919104:2550136831]	auto[0]	135	1			T5	1		T14	1		T16	1
auto[2415919104:2550136831]	auto[1]	10	1			T109	1		T356	1		T114	1
auto[2550136832:2684354559]	auto[0]	133	1			T16	1		T107	1		T209	1
auto[2550136832:2684354559]	auto[1]	11	1			T106	3		T109	1		T110	1
auto[2684354560:2818572287]	auto[0]	134	1			T14	1		T16	1		T126	1
auto[2684354560:2818572287]	auto[1]	7	1			T106	1		T285	2		T398	1
auto[2818572288:2952790015]	auto[0]	123	1			T42	1		T106	1		T69	1
auto[2818572288:2952790015]	auto[1]	14	1			T128	1		T255	1		T356	1
auto[2952790016:3087007743]	auto[0]	129	1			T5	1		T15	1		T18	1
auto[2952790016:3087007743]	auto[1]	12	1			T42	1		T285	1		T410	1
auto[3087007744:3221225471]	auto[0]	117	1			T42	1		T107	1		T209	1
auto[3087007744:3221225471]	auto[1]	12	1			T106	2		T110	1		T281	1
auto[3221225472:3355443199]	auto[0]	145	1			T14	1		T15	1		T16	1
auto[3221225472:3355443199]	auto[1]	7	1			T88	1		T112	1		T346	1
auto[3355443200:3489660927]	auto[0]	114	1			T88	1		T18	1		T100	1
auto[3355443200:3489660927]	auto[1]	12	1			T42	1		T110	1		T359	1
auto[3489660928:3623878655]	auto[0]	131	1			T17	1		T36	2		T27	2
auto[3489660928:3623878655]	auto[1]	5	1			T410	1		T359	1		T426	1
auto[3623878656:3758096383]	auto[0]	151	1			T14	2		T88	1		T18	1
auto[3623878656:3758096383]	auto[1]	8	1			T110	1		T281	1		T114	1
auto[3758096384:3892314111]	auto[0]	131	1			T18	2		T136	1		T68	2
auto[3758096384:3892314111]	auto[1]	7	1			T106	1		T285	1		T410	1
auto[3892314112:4026531839]	auto[0]	104	1			T26	1		T18	1		T27	1
auto[3892314112:4026531839]	auto[1]	10	1			T88	1		T410	3		T439	1
auto[4026531840:4160749567]	auto[0]	130	1			T16	2		T17	1		T18	1
auto[4026531840:4160749567]	auto[1]	7	1			T110	1		T285	2		T346	1
auto[4160749568:4294967295]	auto[0]	160	1			T16	1		T43	1		T215	1
auto[4160749568:4294967295]	auto[1]	11	1			T88	1		T112	1		T440	1