| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.72 | 99.04 | 98.11 | 98.17 | 100.00 | 99.02 | 98.63 | 91.09 |
| T1007 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2577293393 | Aug 27 05:36:17 AM UTC 24 | Aug 27 05:36:28 AM UTC 24 | 106376251 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3177148874 | Aug 27 05:36:24 AM UTC 24 | Aug 27 05:36:29 AM UTC 24 | 431005267 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2412460329 | Aug 27 05:36:17 AM UTC 24 | Aug 27 05:36:29 AM UTC 24 | 173516670 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4164087006 | Aug 27 05:36:17 AM UTC 24 | Aug 27 05:36:30 AM UTC 24 | 190378281 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2864190845 | Aug 27 05:36:22 AM UTC 24 | Aug 27 05:36:31 AM UTC 24 | 70737714 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4046128233 | Aug 27 05:36:26 AM UTC 24 | Aug 27 05:36:32 AM UTC 24 | 397922372 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.551281064 | Aug 27 05:36:22 AM UTC 24 | Aug 27 05:36:32 AM UTC 24 | 34655296 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3824570451 | Aug 27 05:36:26 AM UTC 24 | Aug 27 05:36:32 AM UTC 24 | 60257284 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2907799093 | Aug 27 05:36:22 AM UTC 24 | Aug 27 05:36:33 AM UTC 24 | 175014089 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3605218117 | Aug 27 05:36:33 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 10875455 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2929556160 | Aug 27 05:36:33 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 98914335 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2264738764 | Aug 27 05:36:33 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 36001396 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3893096735 | Aug 27 05:36:36 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 22168341 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.1041617334 | Aug 27 05:36:34 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 19048049 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.2224680862 | Aug 27 05:36:13 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 10228421 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.3554130734 | Aug 27 05:36:13 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 17959998 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.339993974 | Aug 27 05:36:13 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 90785993 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.2520966214 | Aug 27 05:36:17 AM UTC 24 | Aug 27 05:36:36 AM UTC 24 | 18573097 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1305536226 | Aug 27 05:36:03 AM UTC 24 | Aug 27 05:36:37 AM UTC 24 | 79274699 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4095613082 | Aug 27 05:36:03 AM UTC 24 | Aug 27 05:36:37 AM UTC 24 | 275049233 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.3100857363 | Aug 27 05:36:04 AM UTC 24 | Aug 27 05:36:38 AM UTC 24 | 91479351 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1455840382 | Aug 27 05:36:17 AM UTC 24 | Aug 27 05:36:39 AM UTC 24 | 73765828 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2393477330 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:40 AM UTC 24 | 40736483 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.3505562879 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:40 AM UTC 24 | 19067081 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.3446596109 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:40 AM UTC 24 | 34961446 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.2524030748 | Aug 27 05:36:13 AM UTC 24 | Aug 27 05:36:40 AM UTC 24 | 820832549 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2886798188 | Aug 27 05:36:15 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 354571496 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3242703998 | Aug 27 05:36:38 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 13884192 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.527226677 | Aug 27 05:36:38 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 10321617 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1532440577 | Aug 27 05:36:36 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 15199478 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.945152124 | Aug 27 05:36:38 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 11691880 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1445335103 | Aug 27 05:36:38 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 39117303 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.2984111652 | Aug 27 05:36:38 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 45342350 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.218399637 | Aug 27 05:36:36 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 16415058 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.1314870533 | Aug 27 05:36:18 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 10446448 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.966375500 | Aug 27 05:36:36 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 38696653 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3973527893 | Aug 27 05:36:28 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 35866712 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.2403700928 | Aug 27 05:36:12 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 17880108 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.395732547 | Aug 27 05:36:28 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 14491177 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.2663634728 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 43898954 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.522755674 | Aug 27 05:36:29 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 41395942 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3861936113 | Aug 27 05:36:38 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 15099328 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1290091751 | Aug 27 05:36:26 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 10207309 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.519577880 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 38904900 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.273353639 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 14915932 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.2468712873 | Aug 27 05:36:19 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 155474402 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1020689977 | Aug 27 05:36:18 AM UTC 24 | Aug 27 05:36:41 AM UTC 24 | 106736856 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2689182045 | Aug 27 05:36:19 AM UTC 24 | Aug 27 05:36:42 AM UTC 24 | 67901194 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.612507709 | Aug 27 05:36:12 AM UTC 24 | Aug 27 05:36:42 AM UTC 24 | 81492393 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.919288351 | Aug 27 05:36:18 AM UTC 24 | Aug 27 05:36:42 AM UTC 24 | 154562213 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3110906188 | Aug 27 05:36:15 AM UTC 24 | Aug 27 05:36:42 AM UTC 24 | 395848748 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1585007121 | Aug 27 05:36:12 AM UTC 24 | Aug 27 05:36:42 AM UTC 24 | 132866343 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.2024081910 | Aug 27 05:36:12 AM UTC 24 | Aug 27 05:36:43 AM UTC 24 | 57342905 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1524768507 | Aug 27 05:36:12 AM UTC 24 | Aug 27 05:36:43 AM UTC 24 | 88974484 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.1489856495 | Aug 27 05:36:19 AM UTC 24 | Aug 27 05:36:43 AM UTC 24 | 98987245 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.730658601 | Aug 27 05:36:19 AM UTC 24 | Aug 27 05:36:43 AM UTC 24 | 182112699 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3723593021 | Aug 27 05:36:18 AM UTC 24 | Aug 27 05:36:43 AM UTC 24 | 199574099 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.97819942 | Aug 27 05:36:19 AM UTC 24 | Aug 27 05:36:44 AM UTC 24 | 57746569 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.847185906 | Aug 27 05:36:12 AM UTC 24 | Aug 27 05:36:44 AM UTC 24 | 162560171 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.216396497 | Aug 27 05:36:14 AM UTC 24 | Aug 27 05:36:47 AM UTC 24 | 55205485 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1614870483 | Aug 27 05:36:15 AM UTC 24 | Aug 27 05:36:48 AM UTC 24 | 88619525 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1182001592 | Aug 27 05:36:14 AM UTC 24 | Aug 27 05:36:48 AM UTC 24 | 237116939 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1239298071 | Aug 27 05:36:08 AM UTC 24 | Aug 27 05:36:49 AM UTC 24 | 137139980 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1442029995 | Aug 27 05:36:18 AM UTC 24 | Aug 27 05:36:52 AM UTC 24 | 1123788862 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2529945181 | Aug 27 05:36:30 AM UTC 24 | Aug 27 05:36:52 AM UTC 24 | 36133066 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.4082544473 | Aug 27 05:36:30 AM UTC 24 | Aug 27 05:36:52 AM UTC 24 | 17141819 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2977876235 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:57 AM UTC 24 | 7912032 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.965297009 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:57 AM UTC 24 | 45645542 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.545755722 | Aug 27 05:36:32 AM UTC 24 | Aug 27 05:36:57 AM UTC 24 | 18827741 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.2624353685 | Aug 27 05:36:25 AM UTC 24 | Aug 27 05:36:57 AM UTC 24 | 107619699 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.709802752 | Aug 27 05:36:05 AM UTC 24 | Aug 27 05:37:01 AM UTC 24 | 34899009 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.1385251692 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 279769025 ps |
| CPU time | 3.84 seconds |
| Started | Aug 27 05:32:02 AM UTC 24 |
| Finished | Aug 27 05:32:07 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385251692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1385251692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.2034099272 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3242895151 ps |
| CPU time | 16.31 seconds |
| Started | Aug 27 05:32:24 AM UTC 24 |
| Finished | Aug 27 05:32:41 AM UTC 24 |
| Peak memory | 226216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034099272 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2034099272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.3436529730 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 72389914 ps |
| CPU time | 3.18 seconds |
| Started | Aug 27 05:32:02 AM UTC 24 |
| Finished | Aug 27 05:32:06 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436529730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3436529730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all_with_rand_reset.2851716258 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3823531419 ps |
| CPU time | 22.09 seconds |
| Started | Aug 27 05:32:25 AM UTC 24 |
| Finished | Aug 27 05:32:48 AM UTC 24 |
| Peak memory | 232696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2851716258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr _stress_all_with_rand_reset.2851716258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.3840597448 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2134940603 ps |
| CPU time | 42.03 seconds |
| Started | Aug 27 05:32:10 AM UTC 24 |
| Finished | Aug 27 05:32:54 AM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840597448 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3840597448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.1453405808 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1230365946 ps |
| CPU time | 10.95 seconds |
| Started | Aug 27 05:32:11 AM UTC 24 |
| Finished | Aug 27 05:32:24 AM UTC 24 |
| Peak memory | 256920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453405808 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1453405808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.4162724423 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1073365759 ps |
| CPU time | 6.22 seconds |
| Started | Aug 27 05:32:00 AM UTC 24 |
| Finished | Aug 27 05:32:07 AM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162724423 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.4162724423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.3826872482 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2333338223 ps |
| CPU time | 23.36 seconds |
| Started | Aug 27 05:32:37 AM UTC 24 |
| Finished | Aug 27 05:33:02 AM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3826872482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr _stress_all_with_rand_reset.3826872482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.2430879007 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 120018496 ps |
| CPU time | 4.84 seconds |
| Started | Aug 27 05:32:40 AM UTC 24 |
| Finished | Aug 27 05:32:46 AM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430879007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2430879007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.4279354511 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 54299543 ps |
| CPU time | 2.59 seconds |
| Started | Aug 27 05:32:24 AM UTC 24 |
| Finished | Aug 27 05:32:27 AM UTC 24 |
| Peak memory | 230580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279354511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4279354511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.2512721479 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 212555786 ps |
| CPU time | 12.64 seconds |
| Started | Aug 27 05:32:17 AM UTC 24 |
| Finished | Aug 27 05:32:30 AM UTC 24 |
| Peak memory | 232640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2512721479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr _stress_all_with_rand_reset.2512721479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.558762847 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 212626990 ps |
| CPU time | 11.32 seconds |
| Started | Aug 27 05:32:34 AM UTC 24 |
| Finished | Aug 27 05:32:46 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558762847 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.558762847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1235777802 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1462691432 ps |
| CPU time | 4.04 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:50 AM UTC 24 |
| Peak memory | 226640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235777802 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.1235777802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.1961645104 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1392982364 ps |
| CPU time | 4.13 seconds |
| Started | Aug 27 05:32:10 AM UTC 24 |
| Finished | Aug 27 05:32:16 AM UTC 24 |
| Peak memory | 226348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961645104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1961645104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.3344181662 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 625210275 ps |
| CPU time | 11.93 seconds |
| Started | Aug 27 05:32:44 AM UTC 24 |
| Finished | Aug 27 05:32:57 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344181662 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3344181662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.2089876191 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1004919692 ps |
| CPU time | 9.13 seconds |
| Started | Aug 27 05:32:22 AM UTC 24 |
| Finished | Aug 27 05:32:33 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089876191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2089876191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.950613733 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 940413927 ps |
| CPU time | 32.62 seconds |
| Started | Aug 27 05:32:31 AM UTC 24 |
| Finished | Aug 27 05:33:05 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950613733 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.950613733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.1309171791 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 46705455 ps |
| CPU time | 3.97 seconds |
| Started | Aug 27 05:32:09 AM UTC 24 |
| Finished | Aug 27 05:32:14 AM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309171791 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1309171791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.2170861840 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1570188764 ps |
| CPU time | 11.07 seconds |
| Started | Aug 27 05:35:28 AM UTC 24 |
| Finished | Aug 27 05:35:41 AM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170861840 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2170861840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.1940791383 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 907741073 ps |
| CPU time | 18.6 seconds |
| Started | Aug 27 05:32:49 AM UTC 24 |
| Finished | Aug 27 05:33:08 AM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940791383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1940791383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_random.1905323522 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 540610105 ps |
| CPU time | 6.36 seconds |
| Started | Aug 27 05:32:00 AM UTC 24 |
| Finished | Aug 27 05:32:07 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905323522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1905323522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.4161947944 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 727687692 ps |
| CPU time | 5.94 seconds |
| Started | Aug 27 05:35:41 AM UTC 24 |
| Finished | Aug 27 05:35:48 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161947944 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.4161947944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.343286414 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 131523716 ps |
| CPU time | 3.33 seconds |
| Started | Aug 27 05:32:16 AM UTC 24 |
| Finished | Aug 27 05:32:21 AM UTC 24 |
| Peak memory | 218568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343286414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.343286414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.3170954324 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 194431362 ps |
| CPU time | 3.62 seconds |
| Started | Aug 27 05:32:15 AM UTC 24 |
| Finished | Aug 27 05:32:20 AM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170954324 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3170954324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2952612091 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 265662040 ps |
| CPU time | 1.57 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 223904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952612091 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.2952612091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.3841892936 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5002122329 ps |
| CPU time | 21.89 seconds |
| Started | Aug 27 05:32:58 AM UTC 24 |
| Finished | Aug 27 05:33:22 AM UTC 24 |
| Peak memory | 232480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3841892936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymg r_stress_all_with_rand_reset.3841892936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.1603265540 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 103563211 ps |
| CPU time | 4.64 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:32:51 AM UTC 24 |
| Peak memory | 218288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603265540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1603265540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.2869155162 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1071518137 ps |
| CPU time | 50.21 seconds |
| Started | Aug 27 05:32:22 AM UTC 24 |
| Finished | Aug 27 05:33:14 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869155162 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2869155162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.3142978388 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1028359443 ps |
| CPU time | 7.1 seconds |
| Started | Aug 27 05:33:11 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142978388 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3142978388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.299727759 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 132372706 ps |
| CPU time | 6.61 seconds |
| Started | Aug 27 05:32:24 AM UTC 24 |
| Finished | Aug 27 05:32:31 AM UTC 24 |
| Peak memory | 232452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299727759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.299727759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.1868391138 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 181830071 ps |
| CPU time | 6.65 seconds |
| Started | Aug 27 05:32:54 AM UTC 24 |
| Finished | Aug 27 05:33:02 AM UTC 24 |
| Peak memory | 228732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868391138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1868391138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.3195550013 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 43048272 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 05:32:06 AM UTC 24 |
| Finished | Aug 27 05:32:09 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195550013 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3195550013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.2414981146 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 274176438 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:29 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414981146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2414981146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.3780117663 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 122423865 ps |
| CPU time | 3.01 seconds |
| Started | Aug 27 05:32:04 AM UTC 24 |
| Finished | Aug 27 05:32:09 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780117663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3780117663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.2934289677 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 445945022 ps |
| CPU time | 5.55 seconds |
| Started | Aug 27 05:34:02 AM UTC 24 |
| Finished | Aug 27 05:34:16 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934289677 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2934289677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.2422624379 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 96396293 ps |
| CPU time | 6.26 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:32:53 AM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2422624379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr _stress_all_with_rand_reset.2422624379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.2897077083 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 63021232 ps |
| CPU time | 3.09 seconds |
| Started | Aug 27 05:34:33 AM UTC 24 |
| Finished | Aug 27 05:34:38 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897077083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2897077083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.297504139 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 241999322 ps |
| CPU time | 11.12 seconds |
| Started | Aug 27 05:35:01 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297504139 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.297504139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.3464542444 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1941682828 ps |
| CPU time | 31.67 seconds |
| Started | Aug 27 05:32:37 AM UTC 24 |
| Finished | Aug 27 05:33:10 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464542444 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3464542444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.2011407782 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1177004229 ps |
| CPU time | 20.82 seconds |
| Started | Aug 27 05:34:49 AM UTC 24 |
| Finished | Aug 27 05:35:32 AM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011407782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2011407782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.569598143 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1554568881 ps |
| CPU time | 17.02 seconds |
| Started | Aug 27 05:32:05 AM UTC 24 |
| Finished | Aug 27 05:32:24 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569598143 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.569598143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.3479643035 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 10853707060 ps |
| CPU time | 52.39 seconds |
| Started | Aug 27 05:33:37 AM UTC 24 |
| Finished | Aug 27 05:34:31 AM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479643035 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3479643035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2412460329 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 173516670 ps |
| CPU time | 4.32 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:29 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412460329 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.2412460329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.577560582 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1475695049 ps |
| CPU time | 48.85 seconds |
| Started | Aug 27 05:32:58 AM UTC 24 |
| Finished | Aug 27 05:33:49 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577560582 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.577560582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.4272416895 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 263719906 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 05:32:27 AM UTC 24 |
| Finished | Aug 27 05:32:32 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272416895 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4272416895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_random.495429587 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2179673779 ps |
| CPU time | 13.57 seconds |
| Started | Aug 27 05:32:34 AM UTC 24 |
| Finished | Aug 27 05:32:48 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495429587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.495429587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.1195149357 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1015753635 ps |
| CPU time | 8.09 seconds |
| Started | Aug 27 05:36:01 AM UTC 24 |
| Finished | Aug 27 05:36:23 AM UTC 24 |
| Peak memory | 228204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195149357 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.1195149357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.1123875899 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 335655378 ps |
| CPU time | 4.57 seconds |
| Started | Aug 27 05:33:01 AM UTC 24 |
| Finished | Aug 27 05:33:07 AM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123875899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1123875899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.1798859778 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 52056096 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:58 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798859778 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1798859778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.4008546938 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 459215050 ps |
| CPU time | 5.92 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:33 AM UTC 24 |
| Peak memory | 224232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008546938 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4008546938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.2346754564 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 6597128870 ps |
| CPU time | 69.89 seconds |
| Started | Aug 27 05:32:50 AM UTC 24 |
| Finished | Aug 27 05:34:02 AM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346754564 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2346754564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.1727020572 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 81154743 ps |
| CPU time | 2.36 seconds |
| Started | Aug 27 05:32:24 AM UTC 24 |
| Finished | Aug 27 05:32:27 AM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727020572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1727020572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.1504261747 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 137020988 ps |
| CPU time | 8.12 seconds |
| Started | Aug 27 05:32:05 AM UTC 24 |
| Finished | Aug 27 05:32:15 AM UTC 24 |
| Peak memory | 230400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1504261747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr _stress_all_with_rand_reset.1504261747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.2279642292 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 51438149762 ps |
| CPU time | 317.9 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:38:32 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279642292 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2279642292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.757703329 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 256528957 ps |
| CPU time | 2.38 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:18 AM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757703329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.757703329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.3114364092 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5316170273 ps |
| CPU time | 30.85 seconds |
| Started | Aug 27 05:32:42 AM UTC 24 |
| Finished | Aug 27 05:33:14 AM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114364092 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3114364092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.2524030748 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 820832549 ps |
| CPU time | 4.55 seconds |
| Started | Aug 27 05:36:13 AM UTC 24 |
| Finished | Aug 27 05:36:40 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524030748 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.2524030748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.1912365462 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 233754481 ps |
| CPU time | 3.14 seconds |
| Started | Aug 27 05:32:02 AM UTC 24 |
| Finished | Aug 27 05:32:06 AM UTC 24 |
| Peak memory | 226100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912365462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1912365462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.2289789939 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 118726399 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 05:32:08 AM UTC 24 |
| Finished | Aug 27 05:32:12 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289789939 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2289789939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.1753583551 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 269662304 ps |
| CPU time | 4.09 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:05 AM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753583551 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1753583551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.728488304 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 848569495 ps |
| CPU time | 9.63 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:33:28 AM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=728488304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr _stress_all_with_rand_reset.728488304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.3135901728 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 112558655 ps |
| CPU time | 7.01 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135901728 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3135901728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.372315845 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 144827139 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 05:32:31 AM UTC 24 |
| Finished | Aug 27 05:32:34 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372315845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.372315845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.2665194746 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 148997913 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 05:35:37 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665194746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2665194746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.2024081910 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 57342905 ps |
| CPU time | 2.21 seconds |
| Started | Aug 27 05:36:12 AM UTC 24 |
| Finished | Aug 27 05:36:43 AM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024081910 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.2024081910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.3712985582 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 218337910 ps |
| CPU time | 4.48 seconds |
| Started | Aug 27 05:34:18 AM UTC 24 |
| Finished | Aug 27 05:34:35 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712985582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3712985582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.83048818 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 160750884 ps |
| CPU time | 3.07 seconds |
| Started | Aug 27 05:34:39 AM UTC 24 |
| Finished | Aug 27 05:34:43 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=83048818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_ stress_all_with_rand_reset.83048818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.2441382846 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1163453380 ps |
| CPU time | 42.15 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:46 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441382846 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2441382846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.2167503008 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 197946285 ps |
| CPU time | 3.83 seconds |
| Started | Aug 27 05:35:35 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167503008 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2167503008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.3241640746 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 601412423 ps |
| CPU time | 12.4 seconds |
| Started | Aug 27 05:32:25 AM UTC 24 |
| Finished | Aug 27 05:32:38 AM UTC 24 |
| Peak memory | 254496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241640746 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3241640746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.2728385352 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 57178682 ps |
| CPU time | 2.69 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:23 AM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728385352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2728385352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.670008151 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 326998669 ps |
| CPU time | 4.22 seconds |
| Started | Aug 27 05:32:49 AM UTC 24 |
| Finished | Aug 27 05:32:54 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670008151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.670008151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.3494588736 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 247376183 ps |
| CPU time | 6.32 seconds |
| Started | Aug 27 05:32:00 AM UTC 24 |
| Finished | Aug 27 05:32:07 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494588736 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3494588736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.3657809192 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 49220190 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 05:32:00 AM UTC 24 |
| Finished | Aug 27 05:32:04 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657809192 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3657809192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.662645271 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 120058365 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 05:32:09 AM UTC 24 |
| Finished | Aug 27 05:32:13 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662645271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.662645271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.2488818462 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 36200945 ps |
| CPU time | 1.78 seconds |
| Started | Aug 27 05:32:57 AM UTC 24 |
| Finished | Aug 27 05:33:00 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488818462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2488818462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.4123916615 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 211728291 ps |
| CPU time | 4.35 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:21 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123916615 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4123916615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.1697797442 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 107885072 ps |
| CPU time | 5.43 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:22 AM UTC 24 |
| Peak memory | 232332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697797442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1697797442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.3541655535 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 288537201 ps |
| CPU time | 3.51 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:21 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541655535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3541655535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.3855738310 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 280067612 ps |
| CPU time | 8.16 seconds |
| Started | Aug 27 05:33:29 AM UTC 24 |
| Finished | Aug 27 05:33:38 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855738310 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3855738310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.275343920 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 166285391 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:12 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275343920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.275343920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.4074052474 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 793920312 ps |
| CPU time | 10.09 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:35:21 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074052474 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4074052474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.1656082964 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 493786027 ps |
| CPU time | 7.66 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:58 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1656082964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymg r_stress_all_with_rand_reset.1656082964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.3723593021 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 199574099 ps |
| CPU time | 2.69 seconds |
| Started | Aug 27 05:36:18 AM UTC 24 |
| Finished | Aug 27 05:36:43 AM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723593021 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.3723593021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.1781767696 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 539581509 ps |
| CPU time | 6.4 seconds |
| Started | Aug 27 05:35:53 AM UTC 24 |
| Finished | Aug 27 05:36:02 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781767696 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.1781767696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.2110699032 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 361784932 ps |
| CPU time | 6.01 seconds |
| Started | Aug 27 05:35:56 AM UTC 24 |
| Finished | Aug 27 05:36:16 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110699032 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.2110699032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.2941702655 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 172134624 ps |
| CPU time | 3.55 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:30 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941702655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2941702655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.1503649766 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 205808136 ps |
| CPU time | 3.97 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:49 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503649766 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.1503649766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.4241121673 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 722636346 ps |
| CPU time | 9.75 seconds |
| Started | Aug 27 05:33:04 AM UTC 24 |
| Finished | Aug 27 05:33:15 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241121673 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4241121673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all_with_rand_reset.2910693780 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3834970165 ps |
| CPU time | 17.43 seconds |
| Started | Aug 27 05:33:06 AM UTC 24 |
| Finished | Aug 27 05:33:24 AM UTC 24 |
| Peak memory | 231264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2910693780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymg r_stress_all_with_rand_reset.2910693780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.1379576641 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 970107184 ps |
| CPU time | 5.9 seconds |
| Started | Aug 27 05:33:13 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379576641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1379576641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.683542098 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 474973906 ps |
| CPU time | 5.97 seconds |
| Started | Aug 27 05:33:13 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683542098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.683542098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.36348009 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 776977020 ps |
| CPU time | 6.67 seconds |
| Started | Aug 27 05:33:11 AM UTC 24 |
| Finished | Aug 27 05:33:19 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36348009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.36348009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.3478409233 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 938530368 ps |
| CPU time | 6.21 seconds |
| Started | Aug 27 05:33:20 AM UTC 24 |
| Finished | Aug 27 05:33:28 AM UTC 24 |
| Peak memory | 228536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478409233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3478409233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.3459941255 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 85337834 ps |
| CPU time | 1.96 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:29 AM UTC 24 |
| Peak memory | 231276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459941255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3459941255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.2006164449 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 992927700 ps |
| CPU time | 7.19 seconds |
| Started | Aug 27 05:33:35 AM UTC 24 |
| Finished | Aug 27 05:33:43 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006164449 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2006164449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.2409334108 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 326077252 ps |
| CPU time | 3.92 seconds |
| Started | Aug 27 05:33:38 AM UTC 24 |
| Finished | Aug 27 05:33:43 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409334108 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2409334108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.3710244026 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 61359685 ps |
| CPU time | 3.36 seconds |
| Started | Aug 27 05:33:42 AM UTC 24 |
| Finished | Aug 27 05:33:47 AM UTC 24 |
| Peak memory | 230192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710244026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3710244026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.3665128643 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 422956631 ps |
| CPU time | 3.83 seconds |
| Started | Aug 27 05:33:54 AM UTC 24 |
| Finished | Aug 27 05:34:24 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665128643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3665128643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.3195151773 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3809927219 ps |
| CPU time | 30.58 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:34:51 AM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195151773 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3195151773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.1839926466 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 735953956 ps |
| CPU time | 10.72 seconds |
| Started | Aug 27 05:34:07 AM UTC 24 |
| Finished | Aug 27 05:34:22 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1839926466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg r_stress_all_with_rand_reset.1839926466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.396293341 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 90216939 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 05:34:35 AM UTC 24 |
| Finished | Aug 27 05:34:53 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396293341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.396293341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.2148027367 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 134182659 ps |
| CPU time | 2.74 seconds |
| Started | Aug 27 05:35:07 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148027367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2148027367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.3861305646 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 303231094 ps |
| CPU time | 4.51 seconds |
| Started | Aug 27 05:35:11 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861305646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3861305646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.3860281094 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 254910645 ps |
| CPU time | 4 seconds |
| Started | Aug 27 05:35:42 AM UTC 24 |
| Finished | Aug 27 05:35:54 AM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860281094 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3860281094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.689868682 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 2401402426 ps |
| CPU time | 15.31 seconds |
| Started | Aug 27 05:35:41 AM UTC 24 |
| Finished | Aug 27 05:36:01 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689868682 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.689868682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.206444694 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 190312262 ps |
| CPU time | 1.41 seconds |
| Started | Aug 27 05:35:41 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206444694 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.206444694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.2933600396 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 23263318 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 05:35:41 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933600396 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2933600396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.3886796029 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 52180510 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 05:35:41 AM UTC 24 |
| Finished | Aug 27 05:35:46 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886796029 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3886796029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4038314376 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 46604602 ps |
| CPU time | 2.07 seconds |
| Started | Aug 27 05:35:42 AM UTC 24 |
| Finished | Aug 27 05:35:52 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038314376 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.4038314376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1533299773 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 159163779 ps |
| CPU time | 4.25 seconds |
| Started | Aug 27 05:35:39 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 226712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533299773 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.1533299773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4109854715 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1867195737 ps |
| CPU time | 14.11 seconds |
| Started | Aug 27 05:35:40 AM UTC 24 |
| Finished | Aug 27 05:35:55 AM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109854715 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.4109854715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.745514053 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 20199711 ps |
| CPU time | 1.76 seconds |
| Started | Aug 27 05:35:40 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 225084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745514053 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.745514053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.1552283182 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 186539459 ps |
| CPU time | 4.39 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:50 AM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552283182 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1552283182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.275883306 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 1086880293 ps |
| CPU time | 10.14 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275883306 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.275883306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.667016238 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 84272489 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:46 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667016238 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.667016238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.515380634 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 127970065 ps |
| CPU time | 1.97 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=515380634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_wi th_rand_reset.515380634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.3379210008 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 64652258 ps |
| CPU time | 0.9 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:46 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379210008 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3379210008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.4285357253 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 14106176 ps |
| CPU time | 0.85 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:46 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285357253 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4285357253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2376083468 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 136746560 ps |
| CPU time | 1.98 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 213592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376083468 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.2376083468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2189595200 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 397604188 ps |
| CPU time | 2.14 seconds |
| Started | Aug 27 05:35:42 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 226808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189595200 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.2189595200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4132619180 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 467551548 ps |
| CPU time | 13.56 seconds |
| Started | Aug 27 05:35:42 AM UTC 24 |
| Finished | Aug 27 05:36:04 AM UTC 24 |
| Peak memory | 226100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132619180 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.4132619180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.3945486535 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 111803590 ps |
| CPU time | 2.7 seconds |
| Started | Aug 27 05:35:43 AM UTC 24 |
| Finished | Aug 27 05:35:53 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945486535 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3945486535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2948890415 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 161374176 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:35:59 AM UTC 24 |
| Finished | Aug 27 05:36:12 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2948890415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_ with_rand_reset.2948890415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.1339630486 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 76701460 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 05:35:58 AM UTC 24 |
| Finished | Aug 27 05:36:00 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339630486 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1339630486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.751228626 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 20743741 ps |
| CPU time | 0.75 seconds |
| Started | Aug 27 05:35:58 AM UTC 24 |
| Finished | Aug 27 05:36:11 AM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751228626 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.751228626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1911319288 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 169829576 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 05:35:59 AM UTC 24 |
| Finished | Aug 27 05:36:13 AM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911319288 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.1911319288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2963907746 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 98489589 ps |
| CPU time | 1.74 seconds |
| Started | Aug 27 05:35:58 AM UTC 24 |
| Finished | Aug 27 05:36:12 AM UTC 24 |
| Peak memory | 223840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963907746 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.2963907746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.852966077 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 784171145 ps |
| CPU time | 7.23 seconds |
| Started | Aug 27 05:35:58 AM UTC 24 |
| Finished | Aug 27 05:36:18 AM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852966077 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.852966077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.3559873204 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 53215968 ps |
| CPU time | 2.24 seconds |
| Started | Aug 27 05:35:58 AM UTC 24 |
| Finished | Aug 27 05:36:13 AM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559873204 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3559873204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1575994158 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 191333145 ps |
| CPU time | 2.39 seconds |
| Started | Aug 27 05:35:58 AM UTC 24 |
| Finished | Aug 27 05:36:02 AM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575994158 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.1575994158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.483954771 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 109381985 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 05:36:01 AM UTC 24 |
| Finished | Aug 27 05:36:16 AM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=483954771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_w ith_rand_reset.483954771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.3694753235 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 56821374 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 05:36:01 AM UTC 24 |
| Finished | Aug 27 05:36:16 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694753235 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3694753235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.1829876293 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 38264703 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 05:36:01 AM UTC 24 |
| Finished | Aug 27 05:36:15 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829876293 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1829876293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.374446192 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 134828403 ps |
| CPU time | 2.5 seconds |
| Started | Aug 27 05:36:01 AM UTC 24 |
| Finished | Aug 27 05:36:18 AM UTC 24 |
| Peak memory | 216032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374446192 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.374446192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1858922350 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 1114832565 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 05:35:59 AM UTC 24 |
| Finished | Aug 27 05:36:13 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858922350 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.1858922350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.123986966 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 141834941 ps |
| CPU time | 2.96 seconds |
| Started | Aug 27 05:36:00 AM UTC 24 |
| Finished | Aug 27 05:36:14 AM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123986966 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.123986966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.2460245975 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 488477484 ps |
| CPU time | 3.89 seconds |
| Started | Aug 27 05:36:01 AM UTC 24 |
| Finished | Aug 27 05:36:19 AM UTC 24 |
| Peak memory | 228320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460245975 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2460245975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4262814949 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 28169809 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 05:36:03 AM UTC 24 |
| Finished | Aug 27 05:36:16 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4262814949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_ with_rand_reset.4262814949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.778379451 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 31203062 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 05:36:02 AM UTC 24 |
| Finished | Aug 27 05:36:11 AM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778379451 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.778379451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.2874022543 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 37393668 ps |
| CPU time | 0.72 seconds |
| Started | Aug 27 05:36:02 AM UTC 24 |
| Finished | Aug 27 05:36:11 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874022543 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2874022543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4095613082 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 275049233 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 05:36:03 AM UTC 24 |
| Finished | Aug 27 05:36:37 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095613082 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.4095613082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.759910023 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 94805214 ps |
| CPU time | 2.01 seconds |
| Started | Aug 27 05:36:02 AM UTC 24 |
| Finished | Aug 27 05:36:12 AM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759910023 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.759910023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2067213085 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 500041463 ps |
| CPU time | 13.52 seconds |
| Started | Aug 27 05:36:02 AM UTC 24 |
| Finished | Aug 27 05:36:24 AM UTC 24 |
| Peak memory | 226740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067213085 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.2067213085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.863188233 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 116776484 ps |
| CPU time | 3.78 seconds |
| Started | Aug 27 05:36:02 AM UTC 24 |
| Finished | Aug 27 05:36:14 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863188233 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.863188233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.1717219049 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 271122667 ps |
| CPU time | 3.55 seconds |
| Started | Aug 27 05:36:02 AM UTC 24 |
| Finished | Aug 27 05:36:14 AM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717219049 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.1717219049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1526823220 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 487391028 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 05:36:09 AM UTC 24 |
| Finished | Aug 27 05:36:11 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1526823220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.1526823220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.3051518195 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 16226687 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 05:36:08 AM UTC 24 |
| Finished | Aug 27 05:36:11 AM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051518195 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3051518195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.709802752 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 34899009 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 05:36:05 AM UTC 24 |
| Finished | Aug 27 05:37:01 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709802752 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.709802752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1239298071 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 137139980 ps |
| CPU time | 3.4 seconds |
| Started | Aug 27 05:36:08 AM UTC 24 |
| Finished | Aug 27 05:36:49 AM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239298071 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.1239298071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1305536226 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 79274699 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 05:36:03 AM UTC 24 |
| Finished | Aug 27 05:36:37 AM UTC 24 |
| Peak memory | 226124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305536226 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.1305536226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3868057595 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 605039702 ps |
| CPU time | 7.13 seconds |
| Started | Aug 27 05:36:04 AM UTC 24 |
| Finished | Aug 27 05:36:23 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868057595 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.3868057595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.3100857363 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 91479351 ps |
| CPU time | 2.55 seconds |
| Started | Aug 27 05:36:04 AM UTC 24 |
| Finished | Aug 27 05:36:38 AM UTC 24 |
| Peak memory | 228324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100857363 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3100857363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.3466718140 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 456382647 ps |
| CPU time | 3.32 seconds |
| Started | Aug 27 05:36:04 AM UTC 24 |
| Finished | Aug 27 05:36:19 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466718140 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.3466718140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.339993974 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 90785993 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 05:36:13 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=339993974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_w ith_rand_reset.339993974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.612507709 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 81492393 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 05:36:12 AM UTC 24 |
| Finished | Aug 27 05:36:42 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612507709 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.612507709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.2403700928 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 17880108 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 05:36:12 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403700928 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2403700928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1585007121 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 132866343 ps |
| CPU time | 1.98 seconds |
| Started | Aug 27 05:36:12 AM UTC 24 |
| Finished | Aug 27 05:36:42 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585007121 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.1585007121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.847185906 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 162560171 ps |
| CPU time | 3.61 seconds |
| Started | Aug 27 05:36:12 AM UTC 24 |
| Finished | Aug 27 05:36:44 AM UTC 24 |
| Peak memory | 226768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847185906 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.847185906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1524768507 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 88974484 ps |
| CPU time | 2.58 seconds |
| Started | Aug 27 05:36:12 AM UTC 24 |
| Finished | Aug 27 05:36:43 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524768507 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1524768507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.216396497 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 55205485 ps |
| CPU time | 1.37 seconds |
| Started | Aug 27 05:36:14 AM UTC 24 |
| Finished | Aug 27 05:36:47 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=216396497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_w ith_rand_reset.216396497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.3554130734 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 17959998 ps |
| CPU time | 0.81 seconds |
| Started | Aug 27 05:36:13 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554130734 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3554130734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.2224680862 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 10228421 ps |
| CPU time | 0.71 seconds |
| Started | Aug 27 05:36:13 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224680862 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2224680862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1182001592 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 237116939 ps |
| CPU time | 1.99 seconds |
| Started | Aug 27 05:36:14 AM UTC 24 |
| Finished | Aug 27 05:36:48 AM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182001592 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.1182001592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1347339964 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 72710088 ps |
| CPU time | 1.62 seconds |
| Started | Aug 27 05:36:13 AM UTC 24 |
| Finished | Aug 27 05:36:17 AM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347339964 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.1347339964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2477699087 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 639970687 ps |
| CPU time | 7.17 seconds |
| Started | Aug 27 05:36:13 AM UTC 24 |
| Finished | Aug 27 05:36:23 AM UTC 24 |
| Peak memory | 226828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477699087 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.2477699087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1536455216 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 28891711 ps |
| CPU time | 1.72 seconds |
| Started | Aug 27 05:36:13 AM UTC 24 |
| Finished | Aug 27 05:36:17 AM UTC 24 |
| Peak memory | 228284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536455216 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1536455216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1777560903 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 53682957 ps |
| CPU time | 1.98 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:27 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1777560903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.1777560903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.2780545495 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 21729829 ps |
| CPU time | 0.75 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:26 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780545495 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2780545495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3430806912 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 88208352 ps |
| CPU time | 0.64 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:25 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430806912 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3430806912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2577293393 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 106376251 ps |
| CPU time | 3.29 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:28 AM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577293393 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.2577293393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1614870483 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 88619525 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:36:15 AM UTC 24 |
| Finished | Aug 27 05:36:48 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614870483 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.1614870483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3110906188 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 395848748 ps |
| CPU time | 6.38 seconds |
| Started | Aug 27 05:36:15 AM UTC 24 |
| Finished | Aug 27 05:36:42 AM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110906188 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.3110906188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2886798188 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 354571496 ps |
| CPU time | 4.75 seconds |
| Started | Aug 27 05:36:15 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886798188 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2886798188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.486282787 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 86475295 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:36:18 AM UTC 24 |
| Finished | Aug 27 05:36:20 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=486282787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_w ith_rand_reset.486282787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1020689977 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 106736856 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 05:36:18 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020689977 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1020689977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.1314870533 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 10446448 ps |
| CPU time | 0.65 seconds |
| Started | Aug 27 05:36:18 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314870533 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1314870533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1870166566 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 23933172 ps |
| CPU time | 1.41 seconds |
| Started | Aug 27 05:36:18 AM UTC 24 |
| Finished | Aug 27 05:36:21 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870166566 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.1870166566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4164087006 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 190378281 ps |
| CPU time | 4.75 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:30 AM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164087006 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.4164087006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1455840382 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 73765828 ps |
| CPU time | 3.69 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:39 AM UTC 24 |
| Peak memory | 232552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455840382 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.1455840382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.2520966214 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 18573097 ps |
| CPU time | 1.3 seconds |
| Started | Aug 27 05:36:17 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520966214 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2520966214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.551281064 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 34655296 ps |
| CPU time | 1.95 seconds |
| Started | Aug 27 05:36:22 AM UTC 24 |
| Finished | Aug 27 05:36:32 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=551281064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_w ith_rand_reset.551281064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2689182045 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 67901194 ps |
| CPU time | 0.82 seconds |
| Started | Aug 27 05:36:19 AM UTC 24 |
| Finished | Aug 27 05:36:42 AM UTC 24 |
| Peak memory | 213532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689182045 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2689182045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.2468712873 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 155474402 ps |
| CPU time | 0.71 seconds |
| Started | Aug 27 05:36:19 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468712873 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2468712873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.730658601 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 182112699 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 05:36:19 AM UTC 24 |
| Finished | Aug 27 05:36:43 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730658601 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.730658601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.919288351 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 154562213 ps |
| CPU time | 1.43 seconds |
| Started | Aug 27 05:36:18 AM UTC 24 |
| Finished | Aug 27 05:36:42 AM UTC 24 |
| Peak memory | 226288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919288351 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.919288351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1442029995 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 1123788862 ps |
| CPU time | 11.06 seconds |
| Started | Aug 27 05:36:18 AM UTC 24 |
| Finished | Aug 27 05:36:52 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442029995 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.1442029995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.97819942 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 57746569 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 05:36:19 AM UTC 24 |
| Finished | Aug 27 05:36:44 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97819942 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.97819942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.1489856495 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 98987245 ps |
| CPU time | 2.23 seconds |
| Started | Aug 27 05:36:19 AM UTC 24 |
| Finished | Aug 27 05:36:43 AM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489856495 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.1489856495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4046128233 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 397922372 ps |
| CPU time | 1.71 seconds |
| Started | Aug 27 05:36:26 AM UTC 24 |
| Finished | Aug 27 05:36:32 AM UTC 24 |
| Peak memory | 226208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4046128233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.4046128233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.2624353685 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 107619699 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 05:36:25 AM UTC 24 |
| Finished | Aug 27 05:36:57 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624353685 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2624353685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.3475036208 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 44948257 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 05:36:24 AM UTC 24 |
| Finished | Aug 27 05:36:25 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475036208 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3475036208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3824570451 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 60257284 ps |
| CPU time | 2.11 seconds |
| Started | Aug 27 05:36:26 AM UTC 24 |
| Finished | Aug 27 05:36:32 AM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824570451 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.3824570451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2864190845 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 70737714 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 05:36:22 AM UTC 24 |
| Finished | Aug 27 05:36:31 AM UTC 24 |
| Peak memory | 226768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864190845 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.2864190845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2907799093 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 175014089 ps |
| CPU time | 3.12 seconds |
| Started | Aug 27 05:36:22 AM UTC 24 |
| Finished | Aug 27 05:36:33 AM UTC 24 |
| Peak memory | 226764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907799093 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.2907799093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3299969815 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 117834478 ps |
| CPU time | 2.57 seconds |
| Started | Aug 27 05:36:24 AM UTC 24 |
| Finished | Aug 27 05:36:27 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299969815 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3299969815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.3177148874 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 431005267 ps |
| CPU time | 3.83 seconds |
| Started | Aug 27 05:36:24 AM UTC 24 |
| Finished | Aug 27 05:36:29 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177148874 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.3177148874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.4221627336 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 381903376 ps |
| CPU time | 6.47 seconds |
| Started | Aug 27 05:35:45 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221627336 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4221627336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2522976583 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 893885743 ps |
| CPU time | 13.26 seconds |
| Started | Aug 27 05:35:45 AM UTC 24 |
| Finished | Aug 27 05:36:03 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522976583 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2522976583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1475576083 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 147754326 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 213568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475576083 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1475576083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.103912022 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 70699577 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:35:45 AM UTC 24 |
| Finished | Aug 27 05:35:51 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=103912022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_wi th_rand_reset.103912022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.283172982 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 12050375 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283172982 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.283172982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.761205420 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 18540951 ps |
| CPU time | 0.86 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 211852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761205420 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.761205420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3697767881 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 305206382 ps |
| CPU time | 1.69 seconds |
| Started | Aug 27 05:35:45 AM UTC 24 |
| Finished | Aug 27 05:35:51 AM UTC 24 |
| Peak memory | 213132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697767881 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.3697767881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3212573379 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 76412848 ps |
| CPU time | 2.64 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:48 AM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212573379 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.3212573379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3995492740 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 309511992 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:48 AM UTC 24 |
| Peak memory | 228204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995492740 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3995492740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.4050685909 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 555809628 ps |
| CPU time | 2.66 seconds |
| Started | Aug 27 05:35:44 AM UTC 24 |
| Finished | Aug 27 05:35:48 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050685909 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.4050685909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1290091751 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 10207309 ps |
| CPU time | 0.84 seconds |
| Started | Aug 27 05:36:26 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290091751 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1290091751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.3973527893 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 35866712 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 05:36:28 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973527893 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3973527893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.395732547 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 14491177 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 05:36:28 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395732547 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.395732547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.61203949 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 15603291 ps |
| CPU time | 0.62 seconds |
| Started | Aug 27 05:36:29 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61203949 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.61203949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.522755674 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 41395942 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 05:36:29 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522755674 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.522755674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.2529945181 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 36133066 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:36:30 AM UTC 24 |
| Finished | Aug 27 05:36:52 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529945181 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2529945181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.4082544473 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 17141819 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 05:36:30 AM UTC 24 |
| Finished | Aug 27 05:36:52 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082544473 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4082544473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.965297009 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 45645542 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:57 AM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965297009 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.965297009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2977876235 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 7912032 ps |
| CPU time | 0.82 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:57 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977876235 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2977876235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.545755722 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 18827741 ps |
| CPU time | 1 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:57 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545755722 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.545755722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.3514074146 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 267627830 ps |
| CPU time | 4.17 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:54 AM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514074146 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3514074146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1330962928 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 462827074 ps |
| CPU time | 6.51 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330962928 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1330962928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4286803522 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 52672957 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:51 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286803522 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4286803522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.390665618 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 22051200 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=390665618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_wi th_rand_reset.390665618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.1876246749 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 28139792 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:51 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876246749 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1876246749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.2018774374 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 23417361 ps |
| CPU time | 0.78 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:51 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018774374 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2018774374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2294708253 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 133612319 ps |
| CPU time | 1.83 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:52 AM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294708253 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.2294708253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3471847393 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 177248770 ps |
| CPU time | 2.99 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:53 AM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471847393 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.3471847393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1191240171 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 147549394 ps |
| CPU time | 6.84 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191240171 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.1191240171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.3578527088 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 79657371 ps |
| CPU time | 3.01 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:53 AM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578527088 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3578527088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.2533102959 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 149909445 ps |
| CPU time | 4.64 seconds |
| Started | Aug 27 05:35:46 AM UTC 24 |
| Finished | Aug 27 05:35:55 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533102959 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.2533102959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2393477330 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 40736483 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:40 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393477330 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2393477330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.273353639 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 14915932 ps |
| CPU time | 0.83 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273353639 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.273353639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.3505562879 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 19067081 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:40 AM UTC 24 |
| Peak memory | 213548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505562879 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3505562879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.2663634728 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 43898954 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663634728 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2663634728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.3446596109 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 34961446 ps |
| CPU time | 0.62 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:40 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446596109 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3446596109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.519577880 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 38904900 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 05:36:32 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519577880 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.519577880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.2929556160 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 98914335 ps |
| CPU time | 0.59 seconds |
| Started | Aug 27 05:36:33 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 213388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929556160 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2929556160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3605218117 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 10875455 ps |
| CPU time | 0.61 seconds |
| Started | Aug 27 05:36:33 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605218117 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3605218117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2264738764 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 36001396 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 05:36:33 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264738764 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2264738764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.1041617334 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 19048049 ps |
| CPU time | 0.62 seconds |
| Started | Aug 27 05:36:34 AM UTC 24 |
| Finished | Aug 27 05:36:36 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041617334 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1041617334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1373319403 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 428347783 ps |
| CPU time | 11.09 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:36:07 AM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373319403 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1373319403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.21449178 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 35923425 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21449178 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.21449178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.479577725 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 20295796 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479577725 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.479577725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.4131281029 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 24056612 ps |
| CPU time | 0.78 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131281029 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4131281029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1701348202 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 607669777 ps |
| CPU time | 5.82 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:36:01 AM UTC 24 |
| Peak memory | 226764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701348202 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.1701348202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.2151910646 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 129357033 ps |
| CPU time | 3.95 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:35:59 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151910646 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2151910646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.262459354 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1048459722 ps |
| CPU time | 8.28 seconds |
| Started | Aug 27 05:35:47 AM UTC 24 |
| Finished | Aug 27 05:36:04 AM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262459354 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.262459354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.218399637 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 16415058 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 05:36:36 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218399637 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.218399637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.966375500 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 38696653 ps |
| CPU time | 0.75 seconds |
| Started | Aug 27 05:36:36 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966375500 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.966375500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.3893096735 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 22168341 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 05:36:36 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 214208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893096735 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3893096735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.1532440577 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 15199478 ps |
| CPU time | 0.61 seconds |
| Started | Aug 27 05:36:36 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532440577 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1532440577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3242703998 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 13884192 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:36:38 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242703998 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3242703998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.2984111652 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 45342350 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 05:36:38 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984111652 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2984111652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.945152124 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 11691880 ps |
| CPU time | 0.64 seconds |
| Started | Aug 27 05:36:38 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945152124 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.945152124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.527226677 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 10321617 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 05:36:38 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527226677 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.527226677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1445335103 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 39117303 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:36:38 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445335103 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1445335103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3861936113 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 15099328 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 05:36:38 AM UTC 24 |
| Finished | Aug 27 05:36:41 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861936113 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3861936113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4213792578 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 35881238 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 05:35:50 AM UTC 24 |
| Finished | Aug 27 05:36:02 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4213792578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w ith_rand_reset.4213792578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3983401542 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 142296048 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 05:35:48 AM UTC 24 |
| Finished | Aug 27 05:36:03 AM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983401542 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.3983401542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3406644137 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 1711512154 ps |
| CPU time | 11.04 seconds |
| Started | Aug 27 05:35:48 AM UTC 24 |
| Finished | Aug 27 05:36:12 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406644137 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.3406644137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.2470843053 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 411190538 ps |
| CPU time | 3.96 seconds |
| Started | Aug 27 05:35:49 AM UTC 24 |
| Finished | Aug 27 05:36:05 AM UTC 24 |
| Peak memory | 226204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470843053 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.2470843053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.415420189 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 52259760 ps |
| CPU time | 1.98 seconds |
| Started | Aug 27 05:35:52 AM UTC 24 |
| Finished | Aug 27 05:36:02 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=415420189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_wi th_rand_reset.415420189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.32759494 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 88809760 ps |
| CPU time | 1.25 seconds |
| Started | Aug 27 05:35:52 AM UTC 24 |
| Finished | Aug 27 05:36:11 AM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32759494 -assert nopostproc +UVM_TESTNAME=keymgr_ base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.32759494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.1855045491 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 46195232 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:35:51 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855045491 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1855045491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1163185366 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 328468015 ps |
| CPU time | 2 seconds |
| Started | Aug 27 05:35:52 AM UTC 24 |
| Finished | Aug 27 05:36:12 AM UTC 24 |
| Peak memory | 213272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163185366 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.1163185366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.458231512 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 50722560 ps |
| CPU time | 2.49 seconds |
| Started | Aug 27 05:35:51 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458231512 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.458231512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.1438456624 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 78831423 ps |
| CPU time | 2.99 seconds |
| Started | Aug 27 05:35:51 AM UTC 24 |
| Finished | Aug 27 05:35:58 AM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438456624 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.1438456624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3717417061 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 29699748 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 05:35:54 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3717417061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w ith_rand_reset.3717417061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.3309906850 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 43636645 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 05:35:53 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309906850 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3309906850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.2038565934 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 11772452 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 05:35:53 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038565934 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2038565934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2447433309 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 195639026 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 05:35:54 AM UTC 24 |
| Finished | Aug 27 05:35:58 AM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447433309 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.2447433309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3906856972 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 698470602 ps |
| CPU time | 1.53 seconds |
| Started | Aug 27 05:35:52 AM UTC 24 |
| Finished | Aug 27 05:36:12 AM UTC 24 |
| Peak memory | 226776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906856972 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.3906856972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.660894361 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 1964256435 ps |
| CPU time | 6.66 seconds |
| Started | Aug 27 05:35:52 AM UTC 24 |
| Finished | Aug 27 05:36:07 AM UTC 24 |
| Peak memory | 226732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660894361 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.660894361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.3638288513 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 55616323 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 05:35:53 AM UTC 24 |
| Finished | Aug 27 05:35:57 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638288513 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3638288513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.398262912 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 90536255 ps |
| CPU time | 1.55 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:35:59 AM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=398262912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_wi th_rand_reset.398262912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.866326458 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 26086820 ps |
| CPU time | 1.16 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:16 AM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866326458 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.866326458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.226551112 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 10424146 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 05:35:56 AM UTC 24 |
| Finished | Aug 27 05:36:00 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226551112 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.226551112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1515191760 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 489199576 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:17 AM UTC 24 |
| Peak memory | 213200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515191760 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.1515191760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2098808285 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 331618069 ps |
| CPU time | 2.56 seconds |
| Started | Aug 27 05:35:54 AM UTC 24 |
| Finished | Aug 27 05:35:58 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098808285 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.2098808285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3987682061 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 53646095 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 05:35:58 AM UTC 24 |
| Finished | Aug 27 05:36:01 AM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3987682061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w ith_rand_reset.3987682061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.4078622596 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 46577389 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:16 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078622596 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4078622596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.3861987818 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 42522944 ps |
| CPU time | 0.65 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:16 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861987818 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3861987818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3906450126 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 49699415 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:00 AM UTC 24 |
| Peak memory | 213592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906450126 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.3906450126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2213313351 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 56119964 ps |
| CPU time | 1.47 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:17 AM UTC 24 |
| Peak memory | 223900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213313351 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.2213313351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2624632619 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 450022520 ps |
| CPU time | 3.83 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:19 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624632619 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.2624632619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.4240563511 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 227628675 ps |
| CPU time | 1.89 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:17 AM UTC 24 |
| Peak memory | 223816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240563511 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4240563511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.1383388290 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 248102908 ps |
| CPU time | 3.49 seconds |
| Started | Aug 27 05:35:57 AM UTC 24 |
| Finished | Aug 27 05:36:19 AM UTC 24 |
| Peak memory | 226056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383388290 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.1383388290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.407801245 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 166086593 ps |
| CPU time | 5.7 seconds |
| Started | Aug 27 05:32:03 AM UTC 24 |
| Finished | Aug 27 05:32:10 AM UTC 24 |
| Peak memory | 232548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407801245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.407801245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.3983882515 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 193530366 ps |
| CPU time | 4.24 seconds |
| Started | Aug 27 05:32:01 AM UTC 24 |
| Finished | Aug 27 05:32:06 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983882515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3983882515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.3460215285 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 133669171 ps |
| CPU time | 3.67 seconds |
| Started | Aug 27 05:32:01 AM UTC 24 |
| Finished | Aug 27 05:32:06 AM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460215285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3460215285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.3948323053 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3018155017 ps |
| CPU time | 62.37 seconds |
| Started | Aug 27 05:32:06 AM UTC 24 |
| Finished | Aug 27 05:33:11 AM UTC 24 |
| Peak memory | 262364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948323053 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3948323053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.2875138205 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 125825850 ps |
| CPU time | 3.06 seconds |
| Started | Aug 27 05:31:58 AM UTC 24 |
| Finished | Aug 27 05:32:03 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875138205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2875138205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.4268035499 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 80650006 ps |
| CPU time | 4.49 seconds |
| Started | Aug 27 05:32:00 AM UTC 24 |
| Finished | Aug 27 05:32:05 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268035499 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4268035499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.3699158878 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 77133328 ps |
| CPU time | 3.16 seconds |
| Started | Aug 27 05:32:03 AM UTC 24 |
| Finished | Aug 27 05:32:07 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699158878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3699158878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.2919348000 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 62548596 ps |
| CPU time | 3.54 seconds |
| Started | Aug 27 05:31:57 AM UTC 24 |
| Finished | Aug 27 05:32:02 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919348000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2919348000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.911284476 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 13157714 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 05:32:13 AM UTC 24 |
| Finished | Aug 27 05:32:15 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911284476 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.911284476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.582310474 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 205091451 ps |
| CPU time | 4.69 seconds |
| Started | Aug 27 05:32:10 AM UTC 24 |
| Finished | Aug 27 05:32:16 AM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582310474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.582310474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.448179439 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 49873189 ps |
| CPU time | 2.12 seconds |
| Started | Aug 27 05:32:09 AM UTC 24 |
| Finished | Aug 27 05:32:12 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448179439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.448179439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.3861195622 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 230492183 ps |
| CPU time | 3.27 seconds |
| Started | Aug 27 05:32:10 AM UTC 24 |
| Finished | Aug 27 05:32:15 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861195622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3861195622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_random.3509796976 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1823609160 ps |
| CPU time | 22.1 seconds |
| Started | Aug 27 05:32:08 AM UTC 24 |
| Finished | Aug 27 05:32:31 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509796976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3509796976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.1844899405 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 76317850 ps |
| CPU time | 2.48 seconds |
| Started | Aug 27 05:32:08 AM UTC 24 |
| Finished | Aug 27 05:32:11 AM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844899405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1844899405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.4060281369 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 677905057 ps |
| CPU time | 5.54 seconds |
| Started | Aug 27 05:32:08 AM UTC 24 |
| Finished | Aug 27 05:32:15 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060281369 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4060281369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.3897681911 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 6256719815 ps |
| CPU time | 49.11 seconds |
| Started | Aug 27 05:32:08 AM UTC 24 |
| Finished | Aug 27 05:32:59 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897681911 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3897681911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.4247797531 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 44825084 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 05:32:10 AM UTC 24 |
| Finished | Aug 27 05:32:14 AM UTC 24 |
| Peak memory | 218068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247797531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4247797531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.1699968872 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 172026237 ps |
| CPU time | 2.78 seconds |
| Started | Aug 27 05:32:08 AM UTC 24 |
| Finished | Aug 27 05:32:12 AM UTC 24 |
| Peak memory | 215340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699968872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1699968872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.3209871627 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 253276701 ps |
| CPU time | 9.62 seconds |
| Started | Aug 27 05:32:11 AM UTC 24 |
| Finished | Aug 27 05:32:22 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3209871627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr _stress_all_with_rand_reset.3209871627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.3399437307 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 497690895 ps |
| CPU time | 3 seconds |
| Started | Aug 27 05:32:10 AM UTC 24 |
| Finished | Aug 27 05:32:15 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399437307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3399437307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.775520298 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 215069319 ps |
| CPU time | 2.48 seconds |
| Started | Aug 27 05:32:10 AM UTC 24 |
| Finished | Aug 27 05:32:14 AM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775520298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.775520298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.1140703200 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 15179827 ps |
| CPU time | 0.89 seconds |
| Started | Aug 27 05:32:58 AM UTC 24 |
| Finished | Aug 27 05:33:00 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140703200 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1140703200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.1553874876 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 884550015 ps |
| CPU time | 5.07 seconds |
| Started | Aug 27 05:32:56 AM UTC 24 |
| Finished | Aug 27 05:33:02 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553874876 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1553874876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.4227733803 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 59864766 ps |
| CPU time | 2 seconds |
| Started | Aug 27 05:32:58 AM UTC 24 |
| Finished | Aug 27 05:33:01 AM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227733803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4227733803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.312160158 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 66889803 ps |
| CPU time | 3.09 seconds |
| Started | Aug 27 05:32:57 AM UTC 24 |
| Finished | Aug 27 05:33:01 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312160158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.312160158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.532181992 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 228464127 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:32:58 AM UTC 24 |
| Finished | Aug 27 05:33:01 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532181992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.532181992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.524545965 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1052868919 ps |
| CPU time | 6.29 seconds |
| Started | Aug 27 05:32:57 AM UTC 24 |
| Finished | Aug 27 05:33:04 AM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524545965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.524545965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_random.3519763545 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 815742042 ps |
| CPU time | 4.72 seconds |
| Started | Aug 27 05:32:56 AM UTC 24 |
| Finished | Aug 27 05:33:01 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519763545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3519763545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.4079859028 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1442858066 ps |
| CPU time | 25.9 seconds |
| Started | Aug 27 05:32:55 AM UTC 24 |
| Finished | Aug 27 05:33:23 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079859028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.4079859028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.838999295 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 21430011 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 05:32:55 AM UTC 24 |
| Finished | Aug 27 05:32:59 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838999295 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.838999295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.2383003561 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 130193690 ps |
| CPU time | 3.71 seconds |
| Started | Aug 27 05:32:55 AM UTC 24 |
| Finished | Aug 27 05:33:00 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383003561 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2383003561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.2271448801 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 56434661 ps |
| CPU time | 2.94 seconds |
| Started | Aug 27 05:32:56 AM UTC 24 |
| Finished | Aug 27 05:32:59 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271448801 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2271448801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.2778770528 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 31820455 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 05:32:58 AM UTC 24 |
| Finished | Aug 27 05:33:02 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778770528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2778770528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1709712314 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 488488069 ps |
| CPU time | 4.89 seconds |
| Started | Aug 27 05:32:55 AM UTC 24 |
| Finished | Aug 27 05:33:01 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709712314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1709712314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.304515986 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 109211456 ps |
| CPU time | 4.8 seconds |
| Started | Aug 27 05:32:57 AM UTC 24 |
| Finished | Aug 27 05:33:03 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304515986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.304515986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.973024264 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 255985375 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 05:32:58 AM UTC 24 |
| Finished | Aug 27 05:33:03 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973024264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.973024264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.574551633 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 18447128 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:05 AM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574551633 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.574551633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.1079268369 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 234869801 ps |
| CPU time | 4.24 seconds |
| Started | Aug 27 05:33:01 AM UTC 24 |
| Finished | Aug 27 05:33:07 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079268369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1079268369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.4208718498 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 334626696 ps |
| CPU time | 10.98 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:12 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208718498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4208718498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.1047284540 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 58491267 ps |
| CPU time | 3.52 seconds |
| Started | Aug 27 05:33:01 AM UTC 24 |
| Finished | Aug 27 05:33:06 AM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047284540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1047284540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.4275381109 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 35177554 ps |
| CPU time | 1.94 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:03 AM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275381109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4275381109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_random.3099522750 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 99551688 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:03 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099522750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3099522750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.3519177840 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 724734832 ps |
| CPU time | 3.05 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:04 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519177840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3519177840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.3731145151 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 78765491 ps |
| CPU time | 3.17 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:04 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731145151 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3731145151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.218408801 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 293457005 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:04 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218408801 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.218408801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.189454340 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 56350881 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:05 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189454340 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.189454340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.3774354597 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 233997344 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 05:33:01 AM UTC 24 |
| Finished | Aug 27 05:33:05 AM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774354597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3774354597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.3910086636 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 140749233 ps |
| CPU time | 3.31 seconds |
| Started | Aug 27 05:33:00 AM UTC 24 |
| Finished | Aug 27 05:33:04 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910086636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3910086636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.3283058021 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 521959317 ps |
| CPU time | 13.7 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:18 AM UTC 24 |
| Peak memory | 231132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3283058021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg r_stress_all_with_rand_reset.3283058021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.1068252744 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 143290250 ps |
| CPU time | 3.65 seconds |
| Started | Aug 27 05:33:01 AM UTC 24 |
| Finished | Aug 27 05:33:06 AM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068252744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1068252744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.3573394057 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 119155002 ps |
| CPU time | 3.13 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:07 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573394057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3573394057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.2998030751 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 34097886 ps |
| CPU time | 0.85 seconds |
| Started | Aug 27 05:33:06 AM UTC 24 |
| Finished | Aug 27 05:33:08 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998030751 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2998030751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.3782355633 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 76187600 ps |
| CPU time | 3.74 seconds |
| Started | Aug 27 05:33:05 AM UTC 24 |
| Finished | Aug 27 05:33:10 AM UTC 24 |
| Peak memory | 218556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782355633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3782355633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.3016223465 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 89268843 ps |
| CPU time | 2.83 seconds |
| Started | Aug 27 05:33:04 AM UTC 24 |
| Finished | Aug 27 05:33:08 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016223465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3016223465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.2555386032 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 150230880 ps |
| CPU time | 3.64 seconds |
| Started | Aug 27 05:33:04 AM UTC 24 |
| Finished | Aug 27 05:33:09 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555386032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2555386032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.3950979908 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 269057108 ps |
| CPU time | 3.37 seconds |
| Started | Aug 27 05:33:04 AM UTC 24 |
| Finished | Aug 27 05:33:09 AM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950979908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3950979908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.364563347 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 88543540 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 05:33:04 AM UTC 24 |
| Finished | Aug 27 05:33:08 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364563347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.364563347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_random.1750183763 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 120661402 ps |
| CPU time | 4.83 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:09 AM UTC 24 |
| Peak memory | 220040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750183763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1750183763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.3938116264 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 112632058 ps |
| CPU time | 4.9 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:09 AM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938116264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3938116264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.3924431370 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2072239438 ps |
| CPU time | 26.16 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:30 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924431370 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3924431370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.3353772745 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 7393298189 ps |
| CPU time | 18.01 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:22 AM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353772745 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3353772745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.3636085034 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 876384892 ps |
| CPU time | 4.05 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:08 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636085034 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3636085034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.1998891771 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 45261046 ps |
| CPU time | 2.29 seconds |
| Started | Aug 27 05:33:06 AM UTC 24 |
| Finished | Aug 27 05:33:09 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998891771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1998891771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.989485338 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1221150419 ps |
| CPU time | 25.56 seconds |
| Started | Aug 27 05:33:03 AM UTC 24 |
| Finished | Aug 27 05:33:30 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989485338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.989485338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.4054423815 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 891324178 ps |
| CPU time | 8.25 seconds |
| Started | Aug 27 05:33:04 AM UTC 24 |
| Finished | Aug 27 05:33:14 AM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054423815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.4054423815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.2441263944 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 474831555 ps |
| CPU time | 5.66 seconds |
| Started | Aug 27 05:33:06 AM UTC 24 |
| Finished | Aug 27 05:33:12 AM UTC 24 |
| Peak memory | 219960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441263944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2441263944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.2332947134 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 14006620 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:12 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332947134 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2332947134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.589419060 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 123200020 ps |
| CPU time | 6.29 seconds |
| Started | Aug 27 05:33:07 AM UTC 24 |
| Finished | Aug 27 05:33:14 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589419060 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.589419060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.1770551289 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 178565526 ps |
| CPU time | 2.21 seconds |
| Started | Aug 27 05:33:09 AM UTC 24 |
| Finished | Aug 27 05:33:12 AM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770551289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1770551289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.2105163983 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 292336075 ps |
| CPU time | 2.95 seconds |
| Started | Aug 27 05:33:07 AM UTC 24 |
| Finished | Aug 27 05:33:11 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105163983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2105163983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.1543233137 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 136668224 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 05:33:08 AM UTC 24 |
| Finished | Aug 27 05:33:13 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543233137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1543233137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.90095522 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 136058802 ps |
| CPU time | 5.08 seconds |
| Started | Aug 27 05:33:08 AM UTC 24 |
| Finished | Aug 27 05:33:14 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90095522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.90095522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.1222930627 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 206531365 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:33:07 AM UTC 24 |
| Finished | Aug 27 05:33:10 AM UTC 24 |
| Peak memory | 223612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222930627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1222930627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_random.300233629 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 150823489 ps |
| CPU time | 5.56 seconds |
| Started | Aug 27 05:33:07 AM UTC 24 |
| Finished | Aug 27 05:33:14 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300233629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.300233629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.244277091 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 156290540 ps |
| CPU time | 2.86 seconds |
| Started | Aug 27 05:33:06 AM UTC 24 |
| Finished | Aug 27 05:33:10 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244277091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.244277091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.1259456114 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 419797062 ps |
| CPU time | 3.32 seconds |
| Started | Aug 27 05:33:07 AM UTC 24 |
| Finished | Aug 27 05:33:11 AM UTC 24 |
| Peak memory | 216060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259456114 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1259456114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.4183246275 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 53341012 ps |
| CPU time | 3.13 seconds |
| Started | Aug 27 05:33:07 AM UTC 24 |
| Finished | Aug 27 05:33:11 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183246275 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4183246275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.1368806480 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 432780902 ps |
| CPU time | 4.73 seconds |
| Started | Aug 27 05:33:07 AM UTC 24 |
| Finished | Aug 27 05:33:13 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368806480 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1368806480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.100864849 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2028765955 ps |
| CPU time | 15.46 seconds |
| Started | Aug 27 05:33:09 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100864849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.100864849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1859226058 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 38823591 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 05:33:06 AM UTC 24 |
| Finished | Aug 27 05:33:09 AM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859226058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1859226058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.496964136 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1741701813 ps |
| CPU time | 15.37 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:26 AM UTC 24 |
| Peak memory | 232752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=496964136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr _stress_all_with_rand_reset.496964136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.3960179854 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1229435376 ps |
| CPU time | 17.7 seconds |
| Started | Aug 27 05:33:09 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960179854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3960179854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.1215749564 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 26030850 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 05:33:13 AM UTC 24 |
| Finished | Aug 27 05:33:15 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215749564 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1215749564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.1103634053 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 108931896 ps |
| CPU time | 2.89 seconds |
| Started | Aug 27 05:33:11 AM UTC 24 |
| Finished | Aug 27 05:33:15 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103634053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1103634053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.123506573 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 876097606 ps |
| CPU time | 8.29 seconds |
| Started | Aug 27 05:33:11 AM UTC 24 |
| Finished | Aug 27 05:33:21 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123506573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.123506573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.2812426727 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4802138223 ps |
| CPU time | 18.31 seconds |
| Started | Aug 27 05:33:12 AM UTC 24 |
| Finished | Aug 27 05:33:32 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812426727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2812426727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.2070818835 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 58784409 ps |
| CPU time | 3.61 seconds |
| Started | Aug 27 05:33:11 AM UTC 24 |
| Finished | Aug 27 05:33:16 AM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070818835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2070818835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_random.1534942527 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 134744070 ps |
| CPU time | 4.96 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:16 AM UTC 24 |
| Peak memory | 226480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534942527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1534942527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.2334897239 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 922744641 ps |
| CPU time | 23.97 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:35 AM UTC 24 |
| Peak memory | 217928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334897239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2334897239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.2382932220 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 105300724 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:15 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382932220 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2382932220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.7792171 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 601781448 ps |
| CPU time | 4.57 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:16 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7792171 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.7792171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.3215556085 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 77533731 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:13 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215556085 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3215556085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.540246535 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 210917146 ps |
| CPU time | 3.44 seconds |
| Started | Aug 27 05:33:10 AM UTC 24 |
| Finished | Aug 27 05:33:15 AM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540246535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.540246535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.3748610146 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2994454511 ps |
| CPU time | 33.95 seconds |
| Started | Aug 27 05:33:13 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748610146 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3748610146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.755949418 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 70979005 ps |
| CPU time | 2.87 seconds |
| Started | Aug 27 05:33:13 AM UTC 24 |
| Finished | Aug 27 05:33:17 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755949418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.755949418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2498379504 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 22899498 ps |
| CPU time | 1.23 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 213488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498379504 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2498379504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.1757559576 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 67926263 ps |
| CPU time | 3.2 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 231424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757559576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1757559576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.567855124 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 51171346 ps |
| CPU time | 3.55 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 220124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567855124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.567855124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.3149488183 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 86405941 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149488183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3149488183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.25699376 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 87996728 ps |
| CPU time | 4.21 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:21 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25699376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.25699376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_random.2345846978 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 51117962 ps |
| CPU time | 3.13 seconds |
| Started | Aug 27 05:33:14 AM UTC 24 |
| Finished | Aug 27 05:33:18 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345846978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2345846978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.1953028843 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 38588882 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 05:33:14 AM UTC 24 |
| Finished | Aug 27 05:33:18 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953028843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1953028843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.1404183557 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 44407826 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 05:33:14 AM UTC 24 |
| Finished | Aug 27 05:33:18 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404183557 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1404183557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.3825642215 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 63840123 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 05:33:14 AM UTC 24 |
| Finished | Aug 27 05:33:18 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825642215 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3825642215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.4105836765 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 96789268 ps |
| CPU time | 4.08 seconds |
| Started | Aug 27 05:33:14 AM UTC 24 |
| Finished | Aug 27 05:33:19 AM UTC 24 |
| Peak memory | 215988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105836765 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4105836765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.3227986189 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 44555670 ps |
| CPU time | 2.74 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:20 AM UTC 24 |
| Peak memory | 224200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227986189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3227986189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.2719509541 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 323400325 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 05:33:13 AM UTC 24 |
| Finished | Aug 27 05:33:17 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719509541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2719509541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.2618831566 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 180306734 ps |
| CPU time | 2.7 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:33:21 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618831566 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2618831566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.3216486250 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 278962907 ps |
| CPU time | 6.76 seconds |
| Started | Aug 27 05:33:16 AM UTC 24 |
| Finished | Aug 27 05:33:24 AM UTC 24 |
| Peak memory | 224352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216486250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3216486250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.1903434340 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 51840328 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 05:33:20 AM UTC 24 |
| Finished | Aug 27 05:33:23 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903434340 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1903434340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.890840372 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 31706784 ps |
| CPU time | 2.98 seconds |
| Started | Aug 27 05:33:19 AM UTC 24 |
| Finished | Aug 27 05:33:23 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890840372 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.890840372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.2543228458 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 487736034 ps |
| CPU time | 2.09 seconds |
| Started | Aug 27 05:33:19 AM UTC 24 |
| Finished | Aug 27 05:33:22 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543228458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2543228458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.3867515759 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 214079121 ps |
| CPU time | 3.35 seconds |
| Started | Aug 27 05:33:20 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867515759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3867515759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.17945892 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 71492405 ps |
| CPU time | 3.59 seconds |
| Started | Aug 27 05:33:20 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17945892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.17945892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.3275567049 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 64404285 ps |
| CPU time | 2.89 seconds |
| Started | Aug 27 05:33:19 AM UTC 24 |
| Finished | Aug 27 05:33:23 AM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275567049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3275567049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_random.2730902223 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 237484773 ps |
| CPU time | 3.02 seconds |
| Started | Aug 27 05:33:19 AM UTC 24 |
| Finished | Aug 27 05:33:23 AM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730902223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2730902223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.1542752663 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 587201840 ps |
| CPU time | 6.07 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542752663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1542752663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.1281465971 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 146278529 ps |
| CPU time | 3.73 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:33:22 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281465971 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1281465971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.2484370356 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 126478201 ps |
| CPU time | 2.67 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:33:21 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484370356 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2484370356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.1280651223 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 7097914638 ps |
| CPU time | 43.08 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:34:02 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280651223 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1280651223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.3867261102 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 311345047 ps |
| CPU time | 5.29 seconds |
| Started | Aug 27 05:33:20 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867261102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3867261102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.2949580287 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 120903918 ps |
| CPU time | 2.88 seconds |
| Started | Aug 27 05:33:17 AM UTC 24 |
| Finished | Aug 27 05:33:21 AM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949580287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2949580287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.2065528891 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1339148815 ps |
| CPU time | 42.91 seconds |
| Started | Aug 27 05:33:20 AM UTC 24 |
| Finished | Aug 27 05:34:05 AM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065528891 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2065528891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.2147146917 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 984870964 ps |
| CPU time | 4.88 seconds |
| Started | Aug 27 05:33:19 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147146917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2147146917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.4025295472 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 550339238 ps |
| CPU time | 9.76 seconds |
| Started | Aug 27 05:33:20 AM UTC 24 |
| Finished | Aug 27 05:33:31 AM UTC 24 |
| Peak memory | 219940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025295472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4025295472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.2349160515 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 15093590 ps |
| CPU time | 0.89 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349160515 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2349160515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.3049517910 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 137258945 ps |
| CPU time | 6.74 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:30 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049517910 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3049517910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.1922135929 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 222758790 ps |
| CPU time | 2.12 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:26 AM UTC 24 |
| Peak memory | 228132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922135929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1922135929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.3595857304 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3742613836 ps |
| CPU time | 34.34 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:58 AM UTC 24 |
| Peak memory | 231724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595857304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3595857304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.1313219388 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 90524224 ps |
| CPU time | 3.73 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 224272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313219388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1313219388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.2963732707 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 70986361 ps |
| CPU time | 2.47 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963732707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2963732707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.3589989419 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 217142094 ps |
| CPU time | 4.16 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 217060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589989419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3589989419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_random.1493297588 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3928531251 ps |
| CPU time | 29.55 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 217232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493297588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1493297588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.2844981749 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 268293955 ps |
| CPU time | 2.42 seconds |
| Started | Aug 27 05:33:21 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844981749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2844981749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.675617300 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 56030338 ps |
| CPU time | 2.81 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675617300 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.675617300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.761699988 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 306428672 ps |
| CPU time | 3.59 seconds |
| Started | Aug 27 05:33:21 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761699988 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.761699988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.838487483 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 46674135 ps |
| CPU time | 1.88 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838487483 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.838487483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.1335065045 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 35525739 ps |
| CPU time | 1.89 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:26 AM UTC 24 |
| Peak memory | 216220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335065045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1335065045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.3669248515 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 58441958 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 05:33:21 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669248515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3669248515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.3457190635 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2049549440 ps |
| CPU time | 24.76 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:49 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457190635 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3457190635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.1790651244 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 798978920 ps |
| CPU time | 10.84 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:35 AM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1790651244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymg r_stress_all_with_rand_reset.1790651244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.3337853374 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 128059743 ps |
| CPU time | 2.06 seconds |
| Started | Aug 27 05:33:22 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337853374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3337853374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.1509064563 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 39196966 ps |
| CPU time | 2.27 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:26 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509064563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1509064563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.2836106684 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 18911647 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 05:33:27 AM UTC 24 |
| Finished | Aug 27 05:33:30 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836106684 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2836106684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.2629933058 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 981267685 ps |
| CPU time | 5.57 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:32 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629933058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2629933058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.3184130686 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 570637880 ps |
| CPU time | 5.41 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:32 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184130686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3184130686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_random.4213070069 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 440597023 ps |
| CPU time | 4.74 seconds |
| Started | Aug 27 05:33:24 AM UTC 24 |
| Finished | Aug 27 05:33:30 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213070069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.4213070069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.1201988242 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 37368653 ps |
| CPU time | 2.52 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201988242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1201988242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.1504592602 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 230929775 ps |
| CPU time | 5.04 seconds |
| Started | Aug 27 05:33:24 AM UTC 24 |
| Finished | Aug 27 05:33:30 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504592602 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1504592602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.2875330996 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 214369067 ps |
| CPU time | 8.26 seconds |
| Started | Aug 27 05:33:24 AM UTC 24 |
| Finished | Aug 27 05:33:34 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875330996 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2875330996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.367416957 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 82249407 ps |
| CPU time | 2.62 seconds |
| Started | Aug 27 05:33:24 AM UTC 24 |
| Finished | Aug 27 05:33:28 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367416957 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.367416957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.2440521236 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 594272731 ps |
| CPU time | 16.06 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:43 AM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440521236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2440521236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.1726615494 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 94094745 ps |
| CPU time | 2.7 seconds |
| Started | Aug 27 05:33:23 AM UTC 24 |
| Finished | Aug 27 05:33:27 AM UTC 24 |
| Peak memory | 215104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726615494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1726615494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.718136905 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 42755652579 ps |
| CPU time | 308.9 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:38:39 AM UTC 24 |
| Peak memory | 230724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718136905 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.718136905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.1938830898 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 196690799 ps |
| CPU time | 8.2 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:35 AM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1938830898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymg r_stress_all_with_rand_reset.1938830898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.2728578222 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 35905841 ps |
| CPU time | 2.42 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:29 AM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728578222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2728578222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.742937524 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 317179576 ps |
| CPU time | 1.76 seconds |
| Started | Aug 27 05:33:26 AM UTC 24 |
| Finished | Aug 27 05:33:29 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742937524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.742937524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.1589920538 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 15030228 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 05:33:30 AM UTC 24 |
| Finished | Aug 27 05:33:33 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589920538 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1589920538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.799610392 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 694418654 ps |
| CPU time | 31.22 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:34:00 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799610392 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.799610392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.2610621075 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 118457476 ps |
| CPU time | 5.93 seconds |
| Started | Aug 27 05:33:29 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610621075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2610621075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.1393832696 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 147654734 ps |
| CPU time | 3.17 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:32 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393832696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1393832696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.3995628162 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 14397102674 ps |
| CPU time | 23.03 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:52 AM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995628162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3995628162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.374332064 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 123575466 ps |
| CPU time | 5.89 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:35 AM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374332064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.374332064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.3767862182 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 58627409 ps |
| CPU time | 2.23 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:31 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767862182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3767862182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_random.2044813307 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 242723566 ps |
| CPU time | 6.39 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:35 AM UTC 24 |
| Peak memory | 219932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044813307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2044813307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.1814947934 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 513949873 ps |
| CPU time | 11.8 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:40 AM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814947934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1814947934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2431038286 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 70856159 ps |
| CPU time | 2.55 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:31 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431038286 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2431038286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.3907040028 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 113660673 ps |
| CPU time | 3.39 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:32 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907040028 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3907040028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.634726963 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1023463975 ps |
| CPU time | 7.11 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634726963 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.634726963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.567937728 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 123049644 ps |
| CPU time | 3.13 seconds |
| Started | Aug 27 05:33:29 AM UTC 24 |
| Finished | Aug 27 05:33:33 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567937728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.567937728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.692763193 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 941759323 ps |
| CPU time | 4.72 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:33 AM UTC 24 |
| Peak memory | 218184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692763193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.692763193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all_with_rand_reset.2494908229 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2750233161 ps |
| CPU time | 11.57 seconds |
| Started | Aug 27 05:33:29 AM UTC 24 |
| Finished | Aug 27 05:33:42 AM UTC 24 |
| Peak memory | 232416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2494908229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymg r_stress_all_with_rand_reset.2494908229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.4269716008 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 109960960 ps |
| CPU time | 4.56 seconds |
| Started | Aug 27 05:33:28 AM UTC 24 |
| Finished | Aug 27 05:33:33 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269716008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4269716008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.3371284357 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 437344829 ps |
| CPU time | 4.12 seconds |
| Started | Aug 27 05:33:29 AM UTC 24 |
| Finished | Aug 27 05:33:34 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371284357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3371284357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1999772684 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 14541330 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 05:32:18 AM UTC 24 |
| Finished | Aug 27 05:32:20 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999772684 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1999772684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.4105309122 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 722301607 ps |
| CPU time | 10.45 seconds |
| Started | Aug 27 05:32:15 AM UTC 24 |
| Finished | Aug 27 05:32:27 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105309122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4105309122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.2841960264 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 105456556 ps |
| CPU time | 5.76 seconds |
| Started | Aug 27 05:32:15 AM UTC 24 |
| Finished | Aug 27 05:32:22 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841960264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2841960264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.510821134 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 99465049 ps |
| CPU time | 5.16 seconds |
| Started | Aug 27 05:32:15 AM UTC 24 |
| Finished | Aug 27 05:32:21 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510821134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.510821134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.3602498101 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 511530573 ps |
| CPU time | 5.13 seconds |
| Started | Aug 27 05:32:15 AM UTC 24 |
| Finished | Aug 27 05:32:21 AM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602498101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3602498101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_random.848992313 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 361382425 ps |
| CPU time | 5.39 seconds |
| Started | Aug 27 05:32:14 AM UTC 24 |
| Finished | Aug 27 05:32:20 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848992313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.848992313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.751132630 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2241251525 ps |
| CPU time | 11.86 seconds |
| Started | Aug 27 05:32:17 AM UTC 24 |
| Finished | Aug 27 05:32:30 AM UTC 24 |
| Peak memory | 262472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751132630 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.751132630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.857249005 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 38254949 ps |
| CPU time | 2.44 seconds |
| Started | Aug 27 05:32:13 AM UTC 24 |
| Finished | Aug 27 05:32:16 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857249005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.857249005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.3010411097 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1805320503 ps |
| CPU time | 41.46 seconds |
| Started | Aug 27 05:32:13 AM UTC 24 |
| Finished | Aug 27 05:32:56 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010411097 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3010411097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.2136922425 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 22270158 ps |
| CPU time | 2.21 seconds |
| Started | Aug 27 05:32:13 AM UTC 24 |
| Finished | Aug 27 05:32:16 AM UTC 24 |
| Peak memory | 218288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136922425 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2136922425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.3441038262 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 141322363 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 05:32:14 AM UTC 24 |
| Finished | Aug 27 05:32:18 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441038262 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3441038262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.3446921949 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 382472612 ps |
| CPU time | 3.97 seconds |
| Started | Aug 27 05:32:16 AM UTC 24 |
| Finished | Aug 27 05:32:21 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446921949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3446921949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.1379347317 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 163553689 ps |
| CPU time | 3.27 seconds |
| Started | Aug 27 05:32:13 AM UTC 24 |
| Finished | Aug 27 05:32:17 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379347317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1379347317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.2520342844 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1988602065 ps |
| CPU time | 25.43 seconds |
| Started | Aug 27 05:32:17 AM UTC 24 |
| Finished | Aug 27 05:32:43 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520342844 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2520342844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.4095707646 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 668585381 ps |
| CPU time | 4.65 seconds |
| Started | Aug 27 05:32:15 AM UTC 24 |
| Finished | Aug 27 05:32:21 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095707646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4095707646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.770582067 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 76573395 ps |
| CPU time | 2.86 seconds |
| Started | Aug 27 05:32:16 AM UTC 24 |
| Finished | Aug 27 05:32:20 AM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770582067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.770582067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.82156015 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 51110926 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 05:33:33 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82156015 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.82156015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.2567780889 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 188051300 ps |
| CPU time | 3.7 seconds |
| Started | Aug 27 05:33:32 AM UTC 24 |
| Finished | Aug 27 05:33:37 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567780889 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2567780889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.2713698253 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 132674956 ps |
| CPU time | 2.91 seconds |
| Started | Aug 27 05:33:32 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713698253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2713698253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.4238729266 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 153520071 ps |
| CPU time | 3.95 seconds |
| Started | Aug 27 05:33:32 AM UTC 24 |
| Finished | Aug 27 05:33:37 AM UTC 24 |
| Peak memory | 228596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238729266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4238729266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.1055362579 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 30275491 ps |
| CPU time | 2.7 seconds |
| Started | Aug 27 05:33:32 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055362579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1055362579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.3628466789 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 160987371 ps |
| CPU time | 5.95 seconds |
| Started | Aug 27 05:33:32 AM UTC 24 |
| Finished | Aug 27 05:33:39 AM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628466789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3628466789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.3521055418 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 190977350 ps |
| CPU time | 2.74 seconds |
| Started | Aug 27 05:33:32 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521055418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3521055418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_random.2060804592 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 130839872 ps |
| CPU time | 2.98 seconds |
| Started | Aug 27 05:33:31 AM UTC 24 |
| Finished | Aug 27 05:33:35 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060804592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2060804592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.2255025679 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 578643566 ps |
| CPU time | 6.64 seconds |
| Started | Aug 27 05:33:30 AM UTC 24 |
| Finished | Aug 27 05:33:38 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255025679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2255025679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.3602280564 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 139704447 ps |
| CPU time | 2.75 seconds |
| Started | Aug 27 05:33:31 AM UTC 24 |
| Finished | Aug 27 05:33:34 AM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602280564 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3602280564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.1448240368 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 184769087 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 05:33:31 AM UTC 24 |
| Finished | Aug 27 05:33:34 AM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448240368 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1448240368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.4229573932 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 132941267 ps |
| CPU time | 4.07 seconds |
| Started | Aug 27 05:33:31 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229573932 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4229573932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.1808882491 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 94645442 ps |
| CPU time | 4.18 seconds |
| Started | Aug 27 05:33:33 AM UTC 24 |
| Finished | Aug 27 05:33:39 AM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808882491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1808882491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.3166959703 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 419860683 ps |
| CPU time | 10.62 seconds |
| Started | Aug 27 05:33:30 AM UTC 24 |
| Finished | Aug 27 05:33:42 AM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166959703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3166959703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.239112579 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 19505857683 ps |
| CPU time | 178.35 seconds |
| Started | Aug 27 05:33:33 AM UTC 24 |
| Finished | Aug 27 05:36:35 AM UTC 24 |
| Peak memory | 230236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239112579 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.239112579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.2145573428 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1189909315 ps |
| CPU time | 8.26 seconds |
| Started | Aug 27 05:33:32 AM UTC 24 |
| Finished | Aug 27 05:33:41 AM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145573428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2145573428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.329029820 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 51164067 ps |
| CPU time | 1.62 seconds |
| Started | Aug 27 05:33:33 AM UTC 24 |
| Finished | Aug 27 05:33:36 AM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329029820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.329029820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.3460581895 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 13851873 ps |
| CPU time | 0.91 seconds |
| Started | Aug 27 05:33:37 AM UTC 24 |
| Finished | Aug 27 05:33:39 AM UTC 24 |
| Peak memory | 213628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460581895 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3460581895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.623235609 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 79601869 ps |
| CPU time | 2.3 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:40 AM UTC 24 |
| Peak memory | 224724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623235609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.623235609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.1186498163 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 59306826 ps |
| CPU time | 2.83 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:40 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186498163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1186498163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.478086082 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 587563529 ps |
| CPU time | 6.34 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:44 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478086082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.478086082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.299184955 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 157982435 ps |
| CPU time | 3.2 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:41 AM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299184955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.299184955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.952322643 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 501377209 ps |
| CPU time | 4.21 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:42 AM UTC 24 |
| Peak memory | 232260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952322643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.952322643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_random.2095324026 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 158444615 ps |
| CPU time | 4.86 seconds |
| Started | Aug 27 05:33:35 AM UTC 24 |
| Finished | Aug 27 05:33:41 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095324026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2095324026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.1819187783 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 317413939 ps |
| CPU time | 2.9 seconds |
| Started | Aug 27 05:33:33 AM UTC 24 |
| Finished | Aug 27 05:33:38 AM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819187783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1819187783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.1411731926 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 70698311 ps |
| CPU time | 2.4 seconds |
| Started | Aug 27 05:33:35 AM UTC 24 |
| Finished | Aug 27 05:33:39 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411731926 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1411731926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.3760595799 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 82056618 ps |
| CPU time | 3.39 seconds |
| Started | Aug 27 05:33:33 AM UTC 24 |
| Finished | Aug 27 05:33:38 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760595799 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3760595799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.3355384802 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 362518307 ps |
| CPU time | 3.87 seconds |
| Started | Aug 27 05:33:35 AM UTC 24 |
| Finished | Aug 27 05:33:40 AM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355384802 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3355384802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.2713312452 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 43806899 ps |
| CPU time | 1.85 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:39 AM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713312452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2713312452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.1909645381 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 949377975 ps |
| CPU time | 22.63 seconds |
| Started | Aug 27 05:33:33 AM UTC 24 |
| Finished | Aug 27 05:33:58 AM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909645381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1909645381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.1779059643 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 106230682 ps |
| CPU time | 2.73 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:40 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779059643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1779059643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.585037231 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 248645652 ps |
| CPU time | 2.83 seconds |
| Started | Aug 27 05:33:36 AM UTC 24 |
| Finished | Aug 27 05:33:40 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585037231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.585037231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.3624904503 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 35648136 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:33:43 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624904503 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3624904503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.59241723 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 252088088 ps |
| CPU time | 2.1 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:33:44 AM UTC 24 |
| Peak memory | 228176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59241723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.59241723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.942950584 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 23213295 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:33:39 AM UTC 24 |
| Finished | Aug 27 05:33:42 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942950584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.942950584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.4238740199 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 285506880 ps |
| CPU time | 3.23 seconds |
| Started | Aug 27 05:33:39 AM UTC 24 |
| Finished | Aug 27 05:33:43 AM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238740199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4238740199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.2899712731 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 92529806 ps |
| CPU time | 1.89 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:33:44 AM UTC 24 |
| Peak memory | 231336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899712731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2899712731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.1091258807 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 102242283 ps |
| CPU time | 4.34 seconds |
| Started | Aug 27 05:33:39 AM UTC 24 |
| Finished | Aug 27 05:33:44 AM UTC 24 |
| Peak memory | 230256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091258807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1091258807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_random.2289486234 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 122306076 ps |
| CPU time | 2.66 seconds |
| Started | Aug 27 05:33:38 AM UTC 24 |
| Finished | Aug 27 05:33:41 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289486234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2289486234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.3052553849 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 35048567 ps |
| CPU time | 2.58 seconds |
| Started | Aug 27 05:33:37 AM UTC 24 |
| Finished | Aug 27 05:33:41 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052553849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3052553849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.459125619 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4909609055 ps |
| CPU time | 25.84 seconds |
| Started | Aug 27 05:33:37 AM UTC 24 |
| Finished | Aug 27 05:34:05 AM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459125619 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.459125619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.1306687665 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 56042383 ps |
| CPU time | 2.73 seconds |
| Started | Aug 27 05:33:37 AM UTC 24 |
| Finished | Aug 27 05:33:41 AM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306687665 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1306687665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.2843669545 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1587126983 ps |
| CPU time | 5.82 seconds |
| Started | Aug 27 05:33:38 AM UTC 24 |
| Finished | Aug 27 05:33:45 AM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843669545 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2843669545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.1877044480 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 379805916 ps |
| CPU time | 4.55 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:33:46 AM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877044480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1877044480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.682054495 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 183771988 ps |
| CPU time | 3.31 seconds |
| Started | Aug 27 05:33:37 AM UTC 24 |
| Finished | Aug 27 05:33:42 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682054495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.682054495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.74291547 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 615756769 ps |
| CPU time | 20.78 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:34:03 AM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74291547 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.74291547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all_with_rand_reset.1841920618 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 343328480 ps |
| CPU time | 19.47 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:34:02 AM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1841920618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymg r_stress_all_with_rand_reset.1841920618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1145430679 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 191837851 ps |
| CPU time | 5.92 seconds |
| Started | Aug 27 05:33:39 AM UTC 24 |
| Finished | Aug 27 05:33:46 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145430679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1145430679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.2203884068 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 272878021 ps |
| CPU time | 5.68 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203884068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2203884068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.3887769220 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 13593717 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:33:46 AM UTC 24 |
| Peak memory | 213716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887769220 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3887769220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.3518569695 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 208461228 ps |
| CPU time | 3.54 seconds |
| Started | Aug 27 05:33:42 AM UTC 24 |
| Finished | Aug 27 05:33:47 AM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518569695 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3518569695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.3633450470 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 6880702508 ps |
| CPU time | 16.73 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:34:01 AM UTC 24 |
| Peak memory | 231504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633450470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3633450470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.2586021272 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 47871881 ps |
| CPU time | 2.51 seconds |
| Started | Aug 27 05:33:42 AM UTC 24 |
| Finished | Aug 27 05:33:46 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586021272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2586021272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.3696695036 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 50616874 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:33:47 AM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696695036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3696695036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.2482599353 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1324871354 ps |
| CPU time | 3.35 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482599353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2482599353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_random.3502580123 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 796408882 ps |
| CPU time | 9.46 seconds |
| Started | Aug 27 05:33:42 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502580123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3502580123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.3895072182 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 131866852 ps |
| CPU time | 3.29 seconds |
| Started | Aug 27 05:33:41 AM UTC 24 |
| Finished | Aug 27 05:33:46 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895072182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3895072182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.1075908294 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1665415168 ps |
| CPU time | 3.78 seconds |
| Started | Aug 27 05:33:41 AM UTC 24 |
| Finished | Aug 27 05:33:47 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075908294 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1075908294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.153987577 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 92030122 ps |
| CPU time | 3.4 seconds |
| Started | Aug 27 05:33:41 AM UTC 24 |
| Finished | Aug 27 05:33:47 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153987577 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.153987577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.285751445 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1943314076 ps |
| CPU time | 15.34 seconds |
| Started | Aug 27 05:33:41 AM UTC 24 |
| Finished | Aug 27 05:33:59 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285751445 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.285751445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.1150207280 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 83166978 ps |
| CPU time | 3.84 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150207280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1150207280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2898447422 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 62633665 ps |
| CPU time | 2.54 seconds |
| Started | Aug 27 05:33:40 AM UTC 24 |
| Finished | Aug 27 05:33:45 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898447422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2898447422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.2012586730 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1793562521 ps |
| CPU time | 26.97 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:34:12 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012586730 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2012586730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.2055248139 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 260939894 ps |
| CPU time | 8.98 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:33:54 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2055248139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymg r_stress_all_with_rand_reset.2055248139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.1366726855 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 525612169 ps |
| CPU time | 3.01 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:33:47 AM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366726855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1366726855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.3113910076 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 270176487 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 05:33:43 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 219896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113910076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3113910076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.15086920 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 23499610 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 05:33:47 AM UTC 24 |
| Finished | Aug 27 05:33:49 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15086920 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.15086920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.3917903170 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 233575936 ps |
| CPU time | 5.84 seconds |
| Started | Aug 27 05:33:47 AM UTC 24 |
| Finished | Aug 27 05:33:54 AM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917903170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3917903170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.2205910869 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 536224380 ps |
| CPU time | 16.48 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:34:02 AM UTC 24 |
| Peak memory | 230244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205910869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2205910869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.76672975 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3498673636 ps |
| CPU time | 43.78 seconds |
| Started | Aug 27 05:33:46 AM UTC 24 |
| Finished | Aug 27 05:34:31 AM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76672975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.76672975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.559271212 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 514302126 ps |
| CPU time | 4.15 seconds |
| Started | Aug 27 05:33:46 AM UTC 24 |
| Finished | Aug 27 05:33:51 AM UTC 24 |
| Peak memory | 226204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559271212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.559271212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.2821773891 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 245642214 ps |
| CPU time | 3.94 seconds |
| Started | Aug 27 05:33:46 AM UTC 24 |
| Finished | Aug 27 05:33:51 AM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821773891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2821773891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_random.1190285704 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 284740462 ps |
| CPU time | 6.18 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:33:52 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190285704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1190285704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.2613629087 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 360167977 ps |
| CPU time | 2.61 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613629087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2613629087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.1093960756 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 507360717 ps |
| CPU time | 5.83 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:33:51 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093960756 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1093960756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.2459289482 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 77473805 ps |
| CPU time | 1.71 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:33:47 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459289482 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2459289482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.1716810845 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 26034263 ps |
| CPU time | 2.54 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716810845 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1716810845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.2216919109 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 222146697 ps |
| CPU time | 4.72 seconds |
| Started | Aug 27 05:33:47 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216919109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2216919109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.1863277419 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 81145110 ps |
| CPU time | 2.68 seconds |
| Started | Aug 27 05:33:44 AM UTC 24 |
| Finished | Aug 27 05:33:48 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863277419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1863277419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.975847191 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 173956015 ps |
| CPU time | 3.94 seconds |
| Started | Aug 27 05:33:47 AM UTC 24 |
| Finished | Aug 27 05:33:52 AM UTC 24 |
| Peak memory | 230564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975847191 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.975847191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.2937723623 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 445171193 ps |
| CPU time | 15.49 seconds |
| Started | Aug 27 05:33:47 AM UTC 24 |
| Finished | Aug 27 05:34:04 AM UTC 24 |
| Peak memory | 232632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2937723623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymg r_stress_all_with_rand_reset.2937723623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.3243036893 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 326205003 ps |
| CPU time | 7.04 seconds |
| Started | Aug 27 05:33:46 AM UTC 24 |
| Finished | Aug 27 05:33:54 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243036893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3243036893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.1147147255 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 27467967 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 05:33:47 AM UTC 24 |
| Finished | Aug 27 05:33:50 AM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147147255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1147147255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.3100272525 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 34543045 ps |
| CPU time | 1.25 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100272525 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3100272525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.1983829051 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1160804351 ps |
| CPU time | 4.93 seconds |
| Started | Aug 27 05:33:49 AM UTC 24 |
| Finished | Aug 27 05:33:55 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983829051 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1983829051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.435317988 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 796701456 ps |
| CPU time | 18.15 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:34:09 AM UTC 24 |
| Peak memory | 230360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435317988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.435317988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.2309357994 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 195815993 ps |
| CPU time | 1.66 seconds |
| Started | Aug 27 05:33:49 AM UTC 24 |
| Finished | Aug 27 05:33:51 AM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309357994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2309357994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.3546823434 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 374414022 ps |
| CPU time | 4.56 seconds |
| Started | Aug 27 05:33:49 AM UTC 24 |
| Finished | Aug 27 05:33:54 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546823434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3546823434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.74382835 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 921141119 ps |
| CPU time | 5.34 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:33:57 AM UTC 24 |
| Peak memory | 232448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74382835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.74382835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.919030258 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 167385360 ps |
| CPU time | 4.5 seconds |
| Started | Aug 27 05:33:49 AM UTC 24 |
| Finished | Aug 27 05:33:54 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919030258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.919030258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_random.710694678 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1044507093 ps |
| CPU time | 9.54 seconds |
| Started | Aug 27 05:33:48 AM UTC 24 |
| Finished | Aug 27 05:33:59 AM UTC 24 |
| Peak memory | 224080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710694678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.710694678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.1823120847 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 376192551 ps |
| CPU time | 3.6 seconds |
| Started | Aug 27 05:33:48 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823120847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1823120847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.2961136389 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 64084430 ps |
| CPU time | 3.31 seconds |
| Started | Aug 27 05:33:48 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 216124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961136389 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2961136389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.706865582 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 37432622 ps |
| CPU time | 3.4 seconds |
| Started | Aug 27 05:33:48 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706865582 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.706865582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.4163838662 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 122375084 ps |
| CPU time | 4.74 seconds |
| Started | Aug 27 05:33:48 AM UTC 24 |
| Finished | Aug 27 05:33:54 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163838662 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4163838662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.65067356 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2951990501 ps |
| CPU time | 27.85 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:34:19 AM UTC 24 |
| Peak memory | 224224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65067356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.65067356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.307940774 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 314823026 ps |
| CPU time | 6.18 seconds |
| Started | Aug 27 05:33:47 AM UTC 24 |
| Finished | Aug 27 05:33:54 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307940774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.307940774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.1423985868 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 22609283434 ps |
| CPU time | 110.15 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423985868 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1423985868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all_with_rand_reset.885928206 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 470575228 ps |
| CPU time | 7.08 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:33:59 AM UTC 24 |
| Peak memory | 232312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=885928206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr _stress_all_with_rand_reset.885928206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.1823086265 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 217846514 ps |
| CPU time | 3.65 seconds |
| Started | Aug 27 05:33:49 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823086265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1823086265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.513889249 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 101458249 ps |
| CPU time | 1.68 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:33:53 AM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513889249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.513889249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.828604494 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 24150785 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:34:46 AM UTC 24 |
| Peak memory | 213520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828604494 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.828604494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2742668228 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 57826787 ps |
| CPU time | 3.35 seconds |
| Started | Aug 27 05:33:54 AM UTC 24 |
| Finished | Aug 27 05:34:19 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742668228 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2742668228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.3615084428 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 136022893 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:34:45 AM UTC 24 |
| Peak memory | 223484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615084428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3615084428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.2852226873 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 77681859 ps |
| CPU time | 3.16 seconds |
| Started | Aug 27 05:33:54 AM UTC 24 |
| Finished | Aug 27 05:34:09 AM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852226873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2852226873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.275550009 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 102070176 ps |
| CPU time | 1.89 seconds |
| Started | Aug 27 05:33:54 AM UTC 24 |
| Finished | Aug 27 05:34:45 AM UTC 24 |
| Peak memory | 222988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275550009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.275550009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.333097495 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 30633907 ps |
| CPU time | 1.68 seconds |
| Started | Aug 27 05:33:54 AM UTC 24 |
| Finished | Aug 27 05:34:44 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333097495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.333097495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_random.2205937246 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 303839566 ps |
| CPU time | 4.22 seconds |
| Started | Aug 27 05:33:53 AM UTC 24 |
| Finished | Aug 27 05:34:09 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205937246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2205937246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.136070774 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 210054973 ps |
| CPU time | 2.82 seconds |
| Started | Aug 27 05:33:51 AM UTC 24 |
| Finished | Aug 27 05:33:55 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136070774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.136070774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.1265351615 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 216981076 ps |
| CPU time | 5.33 seconds |
| Started | Aug 27 05:33:53 AM UTC 24 |
| Finished | Aug 27 05:34:00 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265351615 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1265351615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.3523990478 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 141764249 ps |
| CPU time | 2.5 seconds |
| Started | Aug 27 05:33:53 AM UTC 24 |
| Finished | Aug 27 05:34:07 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523990478 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3523990478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.2621416562 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 403896995 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 05:33:53 AM UTC 24 |
| Finished | Aug 27 05:33:58 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621416562 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2621416562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.1553222548 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 55027376 ps |
| CPU time | 2.4 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:34:22 AM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553222548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1553222548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.286275069 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 327608257 ps |
| CPU time | 3.07 seconds |
| Started | Aug 27 05:33:50 AM UTC 24 |
| Finished | Aug 27 05:33:55 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286275069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.286275069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.3381961324 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 94158867 ps |
| CPU time | 4.05 seconds |
| Started | Aug 27 05:33:54 AM UTC 24 |
| Finished | Aug 27 05:34:30 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381961324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3381961324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.3159862472 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 188248823 ps |
| CPU time | 2.61 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:34:23 AM UTC 24 |
| Peak memory | 219964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159862472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3159862472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.1992609632 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 11186101 ps |
| CPU time | 0.62 seconds |
| Started | Aug 27 05:34:00 AM UTC 24 |
| Finished | Aug 27 05:34:12 AM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992609632 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1992609632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.769997140 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 94498680 ps |
| CPU time | 3.15 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:14 AM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769997140 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.769997140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.3174082046 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 99787397 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:13 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174082046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3174082046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.1031133091 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 606599554 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:14 AM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031133091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1031133091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.1339608909 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 80632186 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:12 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339608909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1339608909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.444869332 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 228176883 ps |
| CPU time | 6.55 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:17 AM UTC 24 |
| Peak memory | 219940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444869332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.444869332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_random.3568849823 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1260362777 ps |
| CPU time | 28.08 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:39 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568849823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3568849823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.3135777285 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2149125985 ps |
| CPU time | 37.7 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135777285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3135777285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.1379982076 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 73318103 ps |
| CPU time | 3.09 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:03 AM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379982076 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1379982076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.1604346989 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 66162755 ps |
| CPU time | 2.87 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:34:49 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604346989 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1604346989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.2070055925 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 388827381 ps |
| CPU time | 2.57 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:13 AM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070055925 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2070055925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.395847981 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 235256963 ps |
| CPU time | 2.52 seconds |
| Started | Aug 27 05:33:57 AM UTC 24 |
| Finished | Aug 27 05:34:18 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395847981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.395847981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.609422736 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 507502829 ps |
| CPU time | 2.7 seconds |
| Started | Aug 27 05:33:55 AM UTC 24 |
| Finished | Aug 27 05:34:48 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609422736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.609422736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.2802900481 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1068074740 ps |
| CPU time | 36.9 seconds |
| Started | Aug 27 05:33:58 AM UTC 24 |
| Finished | Aug 27 05:34:48 AM UTC 24 |
| Peak memory | 230940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802900481 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2802900481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.1636749048 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 214081596 ps |
| CPU time | 2.87 seconds |
| Started | Aug 27 05:33:56 AM UTC 24 |
| Finished | Aug 27 05:34:14 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636749048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1636749048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.3023595090 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 458895687 ps |
| CPU time | 3.97 seconds |
| Started | Aug 27 05:33:58 AM UTC 24 |
| Finished | Aug 27 05:34:15 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023595090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3023595090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.192854559 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 15895632 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 05:34:08 AM UTC 24 |
| Finished | Aug 27 05:34:11 AM UTC 24 |
| Peak memory | 213660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192854559 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.192854559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.3146962600 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 85741711 ps |
| CPU time | 2.65 seconds |
| Started | Aug 27 05:34:05 AM UTC 24 |
| Finished | Aug 27 05:34:23 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146962600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3146962600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.4219094433 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 189093000 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 05:34:02 AM UTC 24 |
| Finished | Aug 27 05:34:13 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219094433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4219094433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.2177976258 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 503117350 ps |
| CPU time | 4.94 seconds |
| Started | Aug 27 05:34:03 AM UTC 24 |
| Finished | Aug 27 05:34:21 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177976258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2177976258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.554474937 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1190524494 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 05:34:04 AM UTC 24 |
| Finished | Aug 27 05:34:46 AM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554474937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.554474937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.173324819 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 223532857 ps |
| CPU time | 4.66 seconds |
| Started | Aug 27 05:34:03 AM UTC 24 |
| Finished | Aug 27 05:34:20 AM UTC 24 |
| Peak memory | 232580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173324819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.173324819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_random.395054603 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1447964625 ps |
| CPU time | 6.25 seconds |
| Started | Aug 27 05:34:02 AM UTC 24 |
| Finished | Aug 27 05:34:16 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395054603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.395054603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.858109795 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 46913585 ps |
| CPU time | 2.68 seconds |
| Started | Aug 27 05:34:00 AM UTC 24 |
| Finished | Aug 27 05:34:14 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858109795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.858109795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.1875828107 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 57949338 ps |
| CPU time | 2.29 seconds |
| Started | Aug 27 05:34:01 AM UTC 24 |
| Finished | Aug 27 05:34:07 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875828107 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1875828107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.1587600169 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 41061993 ps |
| CPU time | 2.11 seconds |
| Started | Aug 27 05:34:00 AM UTC 24 |
| Finished | Aug 27 05:34:13 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587600169 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1587600169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.1391051853 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 148897666 ps |
| CPU time | 2.38 seconds |
| Started | Aug 27 05:34:01 AM UTC 24 |
| Finished | Aug 27 05:34:08 AM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391051853 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1391051853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.2987231675 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 139899564 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:34:05 AM UTC 24 |
| Finished | Aug 27 05:34:22 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987231675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2987231675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.2884339588 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 777601551 ps |
| CPU time | 16.36 seconds |
| Started | Aug 27 05:34:00 AM UTC 24 |
| Finished | Aug 27 05:34:28 AM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884339588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2884339588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.86607284 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4151628464 ps |
| CPU time | 23.31 seconds |
| Started | Aug 27 05:34:06 AM UTC 24 |
| Finished | Aug 27 05:34:33 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86607284 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.86607284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.2058910314 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 57820373 ps |
| CPU time | 3.2 seconds |
| Started | Aug 27 05:34:03 AM UTC 24 |
| Finished | Aug 27 05:34:29 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058910314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2058910314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.2893577982 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 48222961 ps |
| CPU time | 1.8 seconds |
| Started | Aug 27 05:34:06 AM UTC 24 |
| Finished | Aug 27 05:34:12 AM UTC 24 |
| Peak memory | 215948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893577982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2893577982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.2847258293 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 93955148 ps |
| CPU time | 3.06 seconds |
| Started | Aug 27 05:34:12 AM UTC 24 |
| Finished | Aug 27 05:34:44 AM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847258293 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2847258293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.1772082072 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 65927846 ps |
| CPU time | 2.01 seconds |
| Started | Aug 27 05:34:14 AM UTC 24 |
| Finished | Aug 27 05:34:17 AM UTC 24 |
| Peak memory | 228792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772082072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1772082072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.1190256119 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 972515291 ps |
| CPU time | 8.73 seconds |
| Started | Aug 27 05:34:12 AM UTC 24 |
| Finished | Aug 27 05:34:50 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190256119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1190256119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.1047537656 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 114206016 ps |
| CPU time | 3.89 seconds |
| Started | Aug 27 05:34:14 AM UTC 24 |
| Finished | Aug 27 05:34:19 AM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047537656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1047537656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.4223851030 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 40084391 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:34:14 AM UTC 24 |
| Finished | Aug 27 05:34:17 AM UTC 24 |
| Peak memory | 224304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223851030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4223851030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.4239495675 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 102720171 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 05:34:12 AM UTC 24 |
| Finished | Aug 27 05:34:43 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239495675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4239495675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_random.3778498749 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1775654471 ps |
| CPU time | 16.58 seconds |
| Started | Aug 27 05:34:11 AM UTC 24 |
| Finished | Aug 27 05:34:32 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778498749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3778498749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.1101894171 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 5459848854 ps |
| CPU time | 31.42 seconds |
| Started | Aug 27 05:34:08 AM UTC 24 |
| Finished | Aug 27 05:34:42 AM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101894171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1101894171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.379438956 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 634345392 ps |
| CPU time | 2.74 seconds |
| Started | Aug 27 05:34:10 AM UTC 24 |
| Finished | Aug 27 05:34:14 AM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379438956 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.379438956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.1159054034 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 147079842 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 05:34:09 AM UTC 24 |
| Finished | Aug 27 05:34:12 AM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159054034 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1159054034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.541319277 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 213495203 ps |
| CPU time | 3.41 seconds |
| Started | Aug 27 05:34:10 AM UTC 24 |
| Finished | Aug 27 05:34:15 AM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541319277 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.541319277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.2139264850 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 121239663 ps |
| CPU time | 1.54 seconds |
| Started | Aug 27 05:34:14 AM UTC 24 |
| Finished | Aug 27 05:34:16 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139264850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2139264850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.1765629956 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 278132673 ps |
| CPU time | 2.93 seconds |
| Started | Aug 27 05:34:08 AM UTC 24 |
| Finished | Aug 27 05:34:13 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765629956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1765629956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.1304375848 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2466496976 ps |
| CPU time | 13.61 seconds |
| Started | Aug 27 05:34:14 AM UTC 24 |
| Finished | Aug 27 05:34:29 AM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304375848 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1304375848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2737934815 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 104385432 ps |
| CPU time | 4.28 seconds |
| Started | Aug 27 05:34:14 AM UTC 24 |
| Finished | Aug 27 05:34:19 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737934815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2737934815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.1438172540 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 301368507 ps |
| CPU time | 2.3 seconds |
| Started | Aug 27 05:34:14 AM UTC 24 |
| Finished | Aug 27 05:34:17 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438172540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1438172540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.2323309763 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 139657685 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 05:32:25 AM UTC 24 |
| Finished | Aug 27 05:32:27 AM UTC 24 |
| Peak memory | 213404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323309763 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2323309763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.3285006937 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 77493069 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 05:32:22 AM UTC 24 |
| Finished | Aug 27 05:32:26 AM UTC 24 |
| Peak memory | 230180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285006937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3285006937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.4010789809 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1973668703 ps |
| CPU time | 13.16 seconds |
| Started | Aug 27 05:32:22 AM UTC 24 |
| Finished | Aug 27 05:32:37 AM UTC 24 |
| Peak memory | 224152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010789809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.4010789809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_random.796478557 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 458963997 ps |
| CPU time | 3.78 seconds |
| Started | Aug 27 05:32:21 AM UTC 24 |
| Finished | Aug 27 05:32:26 AM UTC 24 |
| Peak memory | 220116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796478557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.796478557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.4264480569 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 37991663 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 05:32:19 AM UTC 24 |
| Finished | Aug 27 05:32:22 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264480569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4264480569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.1618194162 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 184300741 ps |
| CPU time | 5.15 seconds |
| Started | Aug 27 05:32:21 AM UTC 24 |
| Finished | Aug 27 05:32:27 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618194162 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1618194162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.2667538673 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 793110709 ps |
| CPU time | 7.4 seconds |
| Started | Aug 27 05:32:21 AM UTC 24 |
| Finished | Aug 27 05:32:29 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667538673 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2667538673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.3674490054 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 24726402 ps |
| CPU time | 2.42 seconds |
| Started | Aug 27 05:32:21 AM UTC 24 |
| Finished | Aug 27 05:32:24 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674490054 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3674490054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.1728954113 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 98084599 ps |
| CPU time | 4.79 seconds |
| Started | Aug 27 05:32:24 AM UTC 24 |
| Finished | Aug 27 05:32:29 AM UTC 24 |
| Peak memory | 218348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728954113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1728954113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.1152249384 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 445705599 ps |
| CPU time | 4.82 seconds |
| Started | Aug 27 05:32:18 AM UTC 24 |
| Finished | Aug 27 05:32:24 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152249384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1152249384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.3986805738 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 179577659 ps |
| CPU time | 5.91 seconds |
| Started | Aug 27 05:32:22 AM UTC 24 |
| Finished | Aug 27 05:32:29 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986805738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3986805738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.3151724556 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 11689030 ps |
| CPU time | 0.61 seconds |
| Started | Aug 27 05:34:20 AM UTC 24 |
| Finished | Aug 27 05:34:41 AM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151724556 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3151724556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.2725824915 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 92502383 ps |
| CPU time | 4.1 seconds |
| Started | Aug 27 05:34:16 AM UTC 24 |
| Finished | Aug 27 05:34:35 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725824915 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2725824915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.3088379445 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 29690748 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 05:34:16 AM UTC 24 |
| Finished | Aug 27 05:34:32 AM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088379445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3088379445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.3469813956 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 42393854 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:34:17 AM UTC 24 |
| Finished | Aug 27 05:34:28 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469813956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3469813956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.193000783 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 160297999 ps |
| CPU time | 2.46 seconds |
| Started | Aug 27 05:34:18 AM UTC 24 |
| Finished | Aug 27 05:34:33 AM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193000783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.193000783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.3644631332 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 81847009 ps |
| CPU time | 3.09 seconds |
| Started | Aug 27 05:34:17 AM UTC 24 |
| Finished | Aug 27 05:34:29 AM UTC 24 |
| Peak memory | 219940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644631332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3644631332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_random.3089289338 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 151309553 ps |
| CPU time | 4.4 seconds |
| Started | Aug 27 05:34:16 AM UTC 24 |
| Finished | Aug 27 05:34:35 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089289338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3089289338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.1209322536 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 211683304 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 05:34:15 AM UTC 24 |
| Finished | Aug 27 05:34:47 AM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209322536 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1209322536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.1702910388 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 103694854 ps |
| CPU time | 1.47 seconds |
| Started | Aug 27 05:34:15 AM UTC 24 |
| Finished | Aug 27 05:35:01 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702910388 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1702910388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.205006368 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3348834160 ps |
| CPU time | 30.79 seconds |
| Started | Aug 27 05:34:15 AM UTC 24 |
| Finished | Aug 27 05:35:30 AM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205006368 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.205006368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.3785747620 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 71880766 ps |
| CPU time | 2.72 seconds |
| Started | Aug 27 05:34:18 AM UTC 24 |
| Finished | Aug 27 05:34:33 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785747620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3785747620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.4188683589 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 231485665 ps |
| CPU time | 3.54 seconds |
| Started | Aug 27 05:34:15 AM UTC 24 |
| Finished | Aug 27 05:34:50 AM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188683589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4188683589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.2824562871 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3041877398 ps |
| CPU time | 18.01 seconds |
| Started | Aug 27 05:34:20 AM UTC 24 |
| Finished | Aug 27 05:34:59 AM UTC 24 |
| Peak memory | 231088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824562871 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2824562871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.114482785 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 534087136 ps |
| CPU time | 16.47 seconds |
| Started | Aug 27 05:34:20 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 232640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=114482785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr _stress_all_with_rand_reset.114482785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.1539278994 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 382149085 ps |
| CPU time | 4.62 seconds |
| Started | Aug 27 05:34:17 AM UTC 24 |
| Finished | Aug 27 05:34:30 AM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539278994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1539278994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.60213422 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2324258562 ps |
| CPU time | 3.9 seconds |
| Started | Aug 27 05:34:19 AM UTC 24 |
| Finished | Aug 27 05:34:45 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60213422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.60213422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.137452278 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 49756640 ps |
| CPU time | 0.72 seconds |
| Started | Aug 27 05:34:29 AM UTC 24 |
| Finished | Aug 27 05:34:31 AM UTC 24 |
| Peak memory | 214160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137452278 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.137452278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.3486917877 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2442888256 ps |
| CPU time | 9.94 seconds |
| Started | Aug 27 05:34:23 AM UTC 24 |
| Finished | Aug 27 05:34:35 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486917877 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3486917877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.1968382952 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 102075497 ps |
| CPU time | 2.03 seconds |
| Started | Aug 27 05:34:29 AM UTC 24 |
| Finished | Aug 27 05:34:32 AM UTC 24 |
| Peak memory | 226704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968382952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1968382952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.2968670423 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 85442167 ps |
| CPU time | 3.06 seconds |
| Started | Aug 27 05:34:23 AM UTC 24 |
| Finished | Aug 27 05:34:28 AM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968670423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2968670423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.463930153 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 193350534 ps |
| CPU time | 2.82 seconds |
| Started | Aug 27 05:34:24 AM UTC 24 |
| Finished | Aug 27 05:34:28 AM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463930153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.463930153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.120220002 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 388456844 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 05:34:27 AM UTC 24 |
| Finished | Aug 27 05:34:46 AM UTC 24 |
| Peak memory | 215172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120220002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.120220002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.423132367 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 884195492 ps |
| CPU time | 2.7 seconds |
| Started | Aug 27 05:34:23 AM UTC 24 |
| Finished | Aug 27 05:34:28 AM UTC 24 |
| Peak memory | 226348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423132367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.423132367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_random.544398705 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 464486588 ps |
| CPU time | 3.85 seconds |
| Started | Aug 27 05:34:23 AM UTC 24 |
| Finished | Aug 27 05:34:29 AM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544398705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.544398705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.1574222492 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 108237366 ps |
| CPU time | 3.7 seconds |
| Started | Aug 27 05:34:21 AM UTC 24 |
| Finished | Aug 27 05:34:29 AM UTC 24 |
| Peak memory | 217508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574222492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1574222492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.1783629043 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 138916542 ps |
| CPU time | 2.86 seconds |
| Started | Aug 27 05:34:22 AM UTC 24 |
| Finished | Aug 27 05:34:33 AM UTC 24 |
| Peak memory | 217924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783629043 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1783629043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.2617271081 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 116609296 ps |
| CPU time | 2.5 seconds |
| Started | Aug 27 05:34:21 AM UTC 24 |
| Finished | Aug 27 05:34:28 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617271081 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2617271081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.3194691986 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 786170676 ps |
| CPU time | 4.02 seconds |
| Started | Aug 27 05:34:22 AM UTC 24 |
| Finished | Aug 27 05:34:34 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194691986 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3194691986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.3987765573 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 122304044 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 05:34:29 AM UTC 24 |
| Finished | Aug 27 05:34:31 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987765573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3987765573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.4102779458 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 43447352 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:34:21 AM UTC 24 |
| Finished | Aug 27 05:34:27 AM UTC 24 |
| Peak memory | 217284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102779458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4102779458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.3578385966 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1381949153 ps |
| CPU time | 37.35 seconds |
| Started | Aug 27 05:34:29 AM UTC 24 |
| Finished | Aug 27 05:35:08 AM UTC 24 |
| Peak memory | 232256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578385966 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3578385966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.1406541479 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 71294929 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 05:34:23 AM UTC 24 |
| Finished | Aug 27 05:34:28 AM UTC 24 |
| Peak memory | 224352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406541479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1406541479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.2493294637 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 37870509 ps |
| CPU time | 1.76 seconds |
| Started | Aug 27 05:34:29 AM UTC 24 |
| Finished | Aug 27 05:34:32 AM UTC 24 |
| Peak memory | 219620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493294637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2493294637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.3987178225 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 29329072 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:34:33 AM UTC 24 |
| Finished | Aug 27 05:34:36 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987178225 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3987178225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.2750882711 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 65385742 ps |
| CPU time | 3.66 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:45 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750882711 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2750882711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.1144105981 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 149134208 ps |
| CPU time | 3.18 seconds |
| Started | Aug 27 05:34:33 AM UTC 24 |
| Finished | Aug 27 05:34:38 AM UTC 24 |
| Peak memory | 224256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144105981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1144105981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.929609929 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 33486186 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:43 AM UTC 24 |
| Peak memory | 216220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929609929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.929609929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.154038932 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 353190354 ps |
| CPU time | 3.49 seconds |
| Started | Aug 27 05:34:33 AM UTC 24 |
| Finished | Aug 27 05:34:39 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154038932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.154038932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.3713460340 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 197235390 ps |
| CPU time | 2.23 seconds |
| Started | Aug 27 05:34:31 AM UTC 24 |
| Finished | Aug 27 05:34:45 AM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713460340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3713460340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_random.2557849767 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 234667448 ps |
| CPU time | 4.58 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:46 AM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557849767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2557849767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.1955659309 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 32578523 ps |
| CPU time | 1.99 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:43 AM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955659309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1955659309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.4209084068 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 96972589 ps |
| CPU time | 2.36 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:44 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209084068 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4209084068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.547074860 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 80413410 ps |
| CPU time | 3.08 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:44 AM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547074860 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.547074860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.1158771132 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 70548633 ps |
| CPU time | 2.77 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:44 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158771132 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1158771132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.3704515418 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 25043353 ps |
| CPU time | 1.3 seconds |
| Started | Aug 27 05:34:33 AM UTC 24 |
| Finished | Aug 27 05:34:36 AM UTC 24 |
| Peak memory | 213768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704515418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3704515418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.704157355 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 92432448 ps |
| CPU time | 2.13 seconds |
| Started | Aug 27 05:34:30 AM UTC 24 |
| Finished | Aug 27 05:34:43 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704157355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.704157355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.77257768 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 931732127 ps |
| CPU time | 8.53 seconds |
| Started | Aug 27 05:34:31 AM UTC 24 |
| Finished | Aug 27 05:34:51 AM UTC 24 |
| Peak memory | 223372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77257768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.77257768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.2380523808 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 18362667 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 05:34:39 AM UTC 24 |
| Finished | Aug 27 05:34:41 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380523808 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2380523808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.1463900504 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 189163014 ps |
| CPU time | 4.33 seconds |
| Started | Aug 27 05:34:35 AM UTC 24 |
| Finished | Aug 27 05:34:54 AM UTC 24 |
| Peak memory | 226068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463900504 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1463900504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.4248008661 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 268075175 ps |
| CPU time | 4.57 seconds |
| Started | Aug 27 05:34:38 AM UTC 24 |
| Finished | Aug 27 05:34:46 AM UTC 24 |
| Peak memory | 232812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248008661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4248008661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.2054865368 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 506037995 ps |
| CPU time | 3.02 seconds |
| Started | Aug 27 05:34:35 AM UTC 24 |
| Finished | Aug 27 05:34:53 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054865368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2054865368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.2680289093 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5198860894 ps |
| CPU time | 26.51 seconds |
| Started | Aug 27 05:34:37 AM UTC 24 |
| Finished | Aug 27 05:35:07 AM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680289093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2680289093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.3306984056 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2569581859 ps |
| CPU time | 10.53 seconds |
| Started | Aug 27 05:34:37 AM UTC 24 |
| Finished | Aug 27 05:34:51 AM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306984056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3306984056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_random.4120987501 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 427486592 ps |
| CPU time | 5.53 seconds |
| Started | Aug 27 05:34:35 AM UTC 24 |
| Finished | Aug 27 05:34:55 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120987501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.4120987501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.3772815119 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 52955713 ps |
| CPU time | 2.3 seconds |
| Started | Aug 27 05:34:34 AM UTC 24 |
| Finished | Aug 27 05:34:38 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772815119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3772815119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.1246946833 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1810317304 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 05:34:34 AM UTC 24 |
| Finished | Aug 27 05:34:38 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246946833 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1246946833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.3589108443 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 2954410377 ps |
| CPU time | 32.47 seconds |
| Started | Aug 27 05:34:34 AM UTC 24 |
| Finished | Aug 27 05:35:08 AM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589108443 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3589108443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.3827678333 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 167883641 ps |
| CPU time | 4.97 seconds |
| Started | Aug 27 05:34:34 AM UTC 24 |
| Finished | Aug 27 05:34:48 AM UTC 24 |
| Peak memory | 218288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827678333 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3827678333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.1093071875 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 34858756 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 05:34:39 AM UTC 24 |
| Finished | Aug 27 05:34:42 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093071875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1093071875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.411071354 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 119194841 ps |
| CPU time | 3.29 seconds |
| Started | Aug 27 05:34:33 AM UTC 24 |
| Finished | Aug 27 05:34:39 AM UTC 24 |
| Peak memory | 216040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411071354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.411071354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.2074827487 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 532869343 ps |
| CPU time | 15.22 seconds |
| Started | Aug 27 05:34:39 AM UTC 24 |
| Finished | Aug 27 05:34:55 AM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074827487 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2074827487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.10476244 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 88275707 ps |
| CPU time | 1.66 seconds |
| Started | Aug 27 05:34:37 AM UTC 24 |
| Finished | Aug 27 05:34:42 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10476244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.10476244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.408172040 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 343260596 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 05:34:39 AM UTC 24 |
| Finished | Aug 27 05:34:42 AM UTC 24 |
| Peak memory | 219860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408172040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.408172040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.2384830186 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 44054081 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:34:45 AM UTC 24 |
| Finished | Aug 27 05:34:47 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384830186 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2384830186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.1701470369 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 285270017 ps |
| CPU time | 11.87 seconds |
| Started | Aug 27 05:34:42 AM UTC 24 |
| Finished | Aug 27 05:35:02 AM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701470369 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1701470369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.2216506885 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 67017492 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 05:34:45 AM UTC 24 |
| Finished | Aug 27 05:34:49 AM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216506885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2216506885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.318228325 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 174867498 ps |
| CPU time | 1.57 seconds |
| Started | Aug 27 05:34:44 AM UTC 24 |
| Finished | Aug 27 05:34:46 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318228325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.318228325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.4060113517 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1171640020 ps |
| CPU time | 10.16 seconds |
| Started | Aug 27 05:34:44 AM UTC 24 |
| Finished | Aug 27 05:34:55 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060113517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4060113517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.830056057 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 53447722 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:34:44 AM UTC 24 |
| Finished | Aug 27 05:34:47 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830056057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.830056057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.3648850544 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 228765230 ps |
| CPU time | 2.66 seconds |
| Started | Aug 27 05:34:44 AM UTC 24 |
| Finished | Aug 27 05:34:48 AM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648850544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3648850544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_random.1096727468 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 493426180 ps |
| CPU time | 4.59 seconds |
| Started | Aug 27 05:34:42 AM UTC 24 |
| Finished | Aug 27 05:34:54 AM UTC 24 |
| Peak memory | 217816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096727468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1096727468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.69408131 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 492596931 ps |
| CPU time | 3.65 seconds |
| Started | Aug 27 05:34:40 AM UTC 24 |
| Finished | Aug 27 05:34:45 AM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69408131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.69408131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.1952056731 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 420434479 ps |
| CPU time | 3.37 seconds |
| Started | Aug 27 05:34:41 AM UTC 24 |
| Finished | Aug 27 05:34:46 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952056731 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1952056731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.2732339627 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 37188776 ps |
| CPU time | 2.27 seconds |
| Started | Aug 27 05:34:40 AM UTC 24 |
| Finished | Aug 27 05:34:44 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732339627 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2732339627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.3433453810 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 190149836 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:34:42 AM UTC 24 |
| Finished | Aug 27 05:34:52 AM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433453810 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3433453810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.3498617650 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 643026207 ps |
| CPU time | 5.03 seconds |
| Started | Aug 27 05:34:45 AM UTC 24 |
| Finished | Aug 27 05:34:51 AM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498617650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3498617650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.1300378146 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 298766985 ps |
| CPU time | 6.06 seconds |
| Started | Aug 27 05:34:40 AM UTC 24 |
| Finished | Aug 27 05:34:47 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300378146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1300378146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.3911040160 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 110705792 ps |
| CPU time | 5.87 seconds |
| Started | Aug 27 05:34:45 AM UTC 24 |
| Finished | Aug 27 05:34:52 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3911040160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymg r_stress_all_with_rand_reset.3911040160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.3382502278 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 248298735 ps |
| CPU time | 4.81 seconds |
| Started | Aug 27 05:34:44 AM UTC 24 |
| Finished | Aug 27 05:34:51 AM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382502278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3382502278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.3621706672 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 55549286 ps |
| CPU time | 2.02 seconds |
| Started | Aug 27 05:34:45 AM UTC 24 |
| Finished | Aug 27 05:34:48 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621706672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3621706672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.636531415 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 156860212 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:51 AM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636531415 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.636531415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.762192869 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 23745705 ps |
| CPU time | 1.42 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:51 AM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762192869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.762192869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.1503434687 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 219904593 ps |
| CPU time | 1.76 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503434687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1503434687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3980777405 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 64981281 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 231408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980777405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3980777405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.1424207543 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 45602092 ps |
| CPU time | 2.52 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 224056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424207543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1424207543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.3258713394 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1890179021 ps |
| CPU time | 3.8 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:34:59 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258713394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3258713394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_random.2309141996 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 90589907 ps |
| CPU time | 3.49 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:34:54 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309141996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2309141996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.1094083685 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 146158848 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 05:34:45 AM UTC 24 |
| Finished | Aug 27 05:34:49 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094083685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1094083685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.1599559894 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2399295769 ps |
| CPU time | 17.7 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:35:29 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599559894 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1599559894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.1943599162 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1381724382 ps |
| CPU time | 16.26 seconds |
| Started | Aug 27 05:34:46 AM UTC 24 |
| Finished | Aug 27 05:35:07 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943599162 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1943599162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.1307196060 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 180244564 ps |
| CPU time | 3.09 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307196060 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1307196060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.3936659909 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 337630765 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:52 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936659909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3936659909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.10814003 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 147213346 ps |
| CPU time | 2.96 seconds |
| Started | Aug 27 05:34:45 AM UTC 24 |
| Finished | Aug 27 05:34:49 AM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10814003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.10814003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.2163169619 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1710282571 ps |
| CPU time | 29.71 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 232512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163169619 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2163169619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.1593820252 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 834070009 ps |
| CPU time | 9.55 seconds |
| Started | Aug 27 05:34:47 AM UTC 24 |
| Finished | Aug 27 05:35:04 AM UTC 24 |
| Peak memory | 217576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593820252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1593820252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.317157761 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 87857133 ps |
| CPU time | 1.47 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:52 AM UTC 24 |
| Peak memory | 217552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317157761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.317157761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.1003119635 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 41036187 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 05:34:52 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003119635 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1003119635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3424940049 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 58930521 ps |
| CPU time | 4.34 seconds |
| Started | Aug 27 05:34:49 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424940049 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3424940049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.930374592 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 95875433 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 05:34:51 AM UTC 24 |
| Finished | Aug 27 05:34:58 AM UTC 24 |
| Peak memory | 228536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930374592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.930374592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.2232098405 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 145163643 ps |
| CPU time | 2.37 seconds |
| Started | Aug 27 05:34:49 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232098405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2232098405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.3071902787 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 143784130 ps |
| CPU time | 2.66 seconds |
| Started | Aug 27 05:34:51 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071902787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3071902787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.506319644 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 125650118 ps |
| CPU time | 3.58 seconds |
| Started | Aug 27 05:34:49 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506319644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.506319644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_random.1872891323 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 130472374 ps |
| CPU time | 3.66 seconds |
| Started | Aug 27 05:34:49 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872891323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1872891323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.491589461 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3504820697 ps |
| CPU time | 29.01 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491589461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.491589461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.7486692 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 28212698 ps |
| CPU time | 1.84 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:52 AM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7486692 -assert nopostproc +UVM_TESTNAME=keymgr_base_t est +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.7486692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.3701402266 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 281329335 ps |
| CPU time | 3.18 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:53 AM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701402266 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3701402266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.203337832 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 183742804 ps |
| CPU time | 2.81 seconds |
| Started | Aug 27 05:34:49 AM UTC 24 |
| Finished | Aug 27 05:35:03 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203337832 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.203337832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.1365772758 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 530546316 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 05:34:51 AM UTC 24 |
| Finished | Aug 27 05:34:58 AM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365772758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1365772758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.668252025 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1014466850 ps |
| CPU time | 4.41 seconds |
| Started | Aug 27 05:34:48 AM UTC 24 |
| Finished | Aug 27 05:34:55 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668252025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.668252025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.764045944 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 42354614 ps |
| CPU time | 2.49 seconds |
| Started | Aug 27 05:34:49 AM UTC 24 |
| Finished | Aug 27 05:34:53 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764045944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.764045944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.4268830803 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 93595978 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 05:34:52 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268830803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4268830803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.434620220 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 38964617 ps |
| CPU time | 0.81 seconds |
| Started | Aug 27 05:34:56 AM UTC 24 |
| Finished | Aug 27 05:35:00 AM UTC 24 |
| Peak memory | 213660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434620220 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.434620220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.2681537967 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 66307435 ps |
| CPU time | 3.58 seconds |
| Started | Aug 27 05:34:53 AM UTC 24 |
| Finished | Aug 27 05:34:59 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681537967 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2681537967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.4270530236 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 424213159 ps |
| CPU time | 5.18 seconds |
| Started | Aug 27 05:34:55 AM UTC 24 |
| Finished | Aug 27 05:35:05 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270530236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4270530236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.210597632 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 422414062 ps |
| CPU time | 3.23 seconds |
| Started | Aug 27 05:34:53 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210597632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.210597632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.679169649 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 85313563 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 05:34:54 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679169649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.679169649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.494990289 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 376911503 ps |
| CPU time | 2.4 seconds |
| Started | Aug 27 05:34:54 AM UTC 24 |
| Finished | Aug 27 05:34:58 AM UTC 24 |
| Peak memory | 232096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494990289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.494990289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.1568925804 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 60003651 ps |
| CPU time | 2.14 seconds |
| Started | Aug 27 05:34:53 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568925804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1568925804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_random.2542744917 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 280482320 ps |
| CPU time | 6.51 seconds |
| Started | Aug 27 05:34:53 AM UTC 24 |
| Finished | Aug 27 05:35:02 AM UTC 24 |
| Peak memory | 218052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542744917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2542744917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2571065014 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 253888495 ps |
| CPU time | 2.57 seconds |
| Started | Aug 27 05:34:52 AM UTC 24 |
| Finished | Aug 27 05:35:09 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571065014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2571065014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.3475543126 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 690096042 ps |
| CPU time | 15.34 seconds |
| Started | Aug 27 05:34:53 AM UTC 24 |
| Finished | Aug 27 05:35:11 AM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475543126 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3475543126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.1515876296 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 264166883 ps |
| CPU time | 2.04 seconds |
| Started | Aug 27 05:34:52 AM UTC 24 |
| Finished | Aug 27 05:34:58 AM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515876296 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1515876296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.844652383 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 20627721 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 05:34:53 AM UTC 24 |
| Finished | Aug 27 05:34:57 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844652383 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.844652383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1059761668 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 48341235 ps |
| CPU time | 1.65 seconds |
| Started | Aug 27 05:34:55 AM UTC 24 |
| Finished | Aug 27 05:35:01 AM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059761668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1059761668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.2167937253 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 157604069 ps |
| CPU time | 1.88 seconds |
| Started | Aug 27 05:34:52 AM UTC 24 |
| Finished | Aug 27 05:35:08 AM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167937253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2167937253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.57309139 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2437618224 ps |
| CPU time | 22.33 seconds |
| Started | Aug 27 05:34:55 AM UTC 24 |
| Finished | Aug 27 05:35:29 AM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57309139 -assert nopostproc +UVM_TESTNAME=ke ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.57309139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.3893078905 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 307650532 ps |
| CPU time | 10.9 seconds |
| Started | Aug 27 05:34:56 AM UTC 24 |
| Finished | Aug 27 05:35:18 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3893078905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg r_stress_all_with_rand_reset.3893078905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.1177444425 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 275927111 ps |
| CPU time | 4.72 seconds |
| Started | Aug 27 05:34:54 AM UTC 24 |
| Finished | Aug 27 05:35:00 AM UTC 24 |
| Peak memory | 228192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177444425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1177444425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.1492406296 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 348800269 ps |
| CPU time | 3 seconds |
| Started | Aug 27 05:34:55 AM UTC 24 |
| Finished | Aug 27 05:35:10 AM UTC 24 |
| Peak memory | 219784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492406296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1492406296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.4081465881 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 81685078 ps |
| CPU time | 0.86 seconds |
| Started | Aug 27 05:34:59 AM UTC 24 |
| Finished | Aug 27 05:35:12 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081465881 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4081465881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.2780942586 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 50427852 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:02 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780942586 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2780942586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.3982951365 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 65513592 ps |
| CPU time | 2.38 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:03 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982951365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3982951365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.3727132596 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3432727423 ps |
| CPU time | 11.28 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:12 AM UTC 24 |
| Peak memory | 220000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727132596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3727132596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.2249412387 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 47764547 ps |
| CPU time | 2.42 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:03 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249412387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2249412387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.2650299774 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 27793804 ps |
| CPU time | 1.38 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:02 AM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650299774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2650299774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.2593472723 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 483798439 ps |
| CPU time | 6.23 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:06 AM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593472723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2593472723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_random.990016529 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 140708736 ps |
| CPU time | 3.15 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:03 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990016529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.990016529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.1168605602 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 91824808 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 05:34:57 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168605602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1168605602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.3238904558 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 230123918 ps |
| CPU time | 2.64 seconds |
| Started | Aug 27 05:34:57 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238904558 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3238904558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.1949737064 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 67383703 ps |
| CPU time | 3.66 seconds |
| Started | Aug 27 05:34:57 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949737064 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1949737064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.2399500191 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 199222975 ps |
| CPU time | 2.36 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:02 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399500191 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2399500191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.641258037 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 41741862 ps |
| CPU time | 1.5 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:02 AM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641258037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.641258037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.3707940693 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 618227799 ps |
| CPU time | 5.07 seconds |
| Started | Aug 27 05:34:57 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707940693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3707940693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.2292598724 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1314318185 ps |
| CPU time | 7.89 seconds |
| Started | Aug 27 05:34:59 AM UTC 24 |
| Finished | Aug 27 05:35:19 AM UTC 24 |
| Peak memory | 230248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292598724 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2292598724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.3095792461 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 105672533 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 05:34:58 AM UTC 24 |
| Finished | Aug 27 05:35:02 AM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095792461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3095792461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.67595403 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 90507981 ps |
| CPU time | 2.71 seconds |
| Started | Aug 27 05:34:59 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67595403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.67595403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.1761154730 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 19380618 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 05:35:03 AM UTC 24 |
| Finished | Aug 27 05:35:06 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761154730 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1761154730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.2784282310 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 220015052 ps |
| CPU time | 5.91 seconds |
| Started | Aug 27 05:35:03 AM UTC 24 |
| Finished | Aug 27 05:35:11 AM UTC 24 |
| Peak memory | 220704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784282310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2784282310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1096330276 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 27742490 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 05:35:01 AM UTC 24 |
| Finished | Aug 27 05:35:06 AM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096330276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1096330276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.481576508 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 367255637 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 05:35:02 AM UTC 24 |
| Finished | Aug 27 05:35:09 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481576508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.481576508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.718240518 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 60123066 ps |
| CPU time | 1.8 seconds |
| Started | Aug 27 05:35:03 AM UTC 24 |
| Finished | Aug 27 05:35:07 AM UTC 24 |
| Peak memory | 223164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718240518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.718240518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.3410654612 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 390697923 ps |
| CPU time | 7.81 seconds |
| Started | Aug 27 05:35:02 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 232040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410654612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3410654612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_random.2724869267 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 195243663 ps |
| CPU time | 2.68 seconds |
| Started | Aug 27 05:35:01 AM UTC 24 |
| Finished | Aug 27 05:35:08 AM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724869267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2724869267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.2862862853 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 60325477 ps |
| CPU time | 3.41 seconds |
| Started | Aug 27 05:35:00 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862862853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2862862853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.133172554 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 97610192 ps |
| CPU time | 2.54 seconds |
| Started | Aug 27 05:35:00 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133172554 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.133172554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.3132081626 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1173335572 ps |
| CPU time | 7.86 seconds |
| Started | Aug 27 05:35:00 AM UTC 24 |
| Finished | Aug 27 05:35:19 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132081626 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3132081626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.3647037021 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 4921644273 ps |
| CPU time | 41.05 seconds |
| Started | Aug 27 05:35:00 AM UTC 24 |
| Finished | Aug 27 05:35:53 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647037021 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3647037021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.551641587 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 211199488 ps |
| CPU time | 3.13 seconds |
| Started | Aug 27 05:35:00 AM UTC 24 |
| Finished | Aug 27 05:35:14 AM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551641587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.551641587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.3259224837 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5848250243 ps |
| CPU time | 34.44 seconds |
| Started | Aug 27 05:35:03 AM UTC 24 |
| Finished | Aug 27 05:35:40 AM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259224837 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3259224837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.516062774 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 255560222 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 05:35:02 AM UTC 24 |
| Finished | Aug 27 05:35:09 AM UTC 24 |
| Peak memory | 217864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516062774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.516062774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.375513204 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 80483978 ps |
| CPU time | 1.44 seconds |
| Started | Aug 27 05:35:03 AM UTC 24 |
| Finished | Aug 27 05:35:07 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375513204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.375513204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.1160606342 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 17415187 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 05:32:32 AM UTC 24 |
| Finished | Aug 27 05:32:35 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160606342 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1160606342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.4117497505 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 83130385 ps |
| CPU time | 3.74 seconds |
| Started | Aug 27 05:32:28 AM UTC 24 |
| Finished | Aug 27 05:32:33 AM UTC 24 |
| Peak memory | 226460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117497505 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4117497505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.3831613247 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1508097347 ps |
| CPU time | 35.87 seconds |
| Started | Aug 27 05:32:31 AM UTC 24 |
| Finished | Aug 27 05:33:08 AM UTC 24 |
| Peak memory | 224548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831613247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3831613247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.1173562522 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 14427175 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 05:32:28 AM UTC 24 |
| Finished | Aug 27 05:32:31 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173562522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1173562522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.4210921811 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 25934110 ps |
| CPU time | 1.68 seconds |
| Started | Aug 27 05:32:30 AM UTC 24 |
| Finished | Aug 27 05:32:32 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210921811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4210921811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.2022125096 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 422694142 ps |
| CPU time | 3.26 seconds |
| Started | Aug 27 05:32:28 AM UTC 24 |
| Finished | Aug 27 05:32:33 AM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022125096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2022125096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_random.2218472246 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2682390693 ps |
| CPU time | 7.55 seconds |
| Started | Aug 27 05:32:27 AM UTC 24 |
| Finished | Aug 27 05:32:36 AM UTC 24 |
| Peak memory | 220096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218472246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2218472246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.413205018 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 665926015 ps |
| CPU time | 5.61 seconds |
| Started | Aug 27 05:32:32 AM UTC 24 |
| Finished | Aug 27 05:32:39 AM UTC 24 |
| Peak memory | 252468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413205018 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.413205018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.2965998923 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1455940116 ps |
| CPU time | 16.85 seconds |
| Started | Aug 27 05:32:26 AM UTC 24 |
| Finished | Aug 27 05:32:44 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965998923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2965998923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.887005032 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 70882722 ps |
| CPU time | 2.48 seconds |
| Started | Aug 27 05:32:27 AM UTC 24 |
| Finished | Aug 27 05:32:31 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887005032 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.887005032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.2439289784 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 326533524 ps |
| CPU time | 2.94 seconds |
| Started | Aug 27 05:32:26 AM UTC 24 |
| Finished | Aug 27 05:32:30 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439289784 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2439289784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.3896377452 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 183688678 ps |
| CPU time | 5.34 seconds |
| Started | Aug 27 05:32:31 AM UTC 24 |
| Finished | Aug 27 05:32:37 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896377452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3896377452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.3460288984 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 4880913669 ps |
| CPU time | 25.95 seconds |
| Started | Aug 27 05:32:25 AM UTC 24 |
| Finished | Aug 27 05:32:52 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460288984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3460288984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.1560267870 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1844358965 ps |
| CPU time | 10.49 seconds |
| Started | Aug 27 05:32:28 AM UTC 24 |
| Finished | Aug 27 05:32:40 AM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560267870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1560267870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.2325705946 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 263475660 ps |
| CPU time | 3.09 seconds |
| Started | Aug 27 05:32:31 AM UTC 24 |
| Finished | Aug 27 05:32:35 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325705946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2325705946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.3494603078 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 40441166 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 05:35:09 AM UTC 24 |
| Finished | Aug 27 05:35:11 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494603078 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3494603078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.3738363986 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 100708921 ps |
| CPU time | 5.56 seconds |
| Started | Aug 27 05:35:07 AM UTC 24 |
| Finished | Aug 27 05:35:17 AM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738363986 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3738363986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.4228602826 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 63176164 ps |
| CPU time | 2.76 seconds |
| Started | Aug 27 05:35:08 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228602826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4228602826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.1276040072 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 81075226 ps |
| CPU time | 2.5 seconds |
| Started | Aug 27 05:35:08 AM UTC 24 |
| Finished | Aug 27 05:35:12 AM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276040072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1276040072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.940467166 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 122477863 ps |
| CPU time | 3.6 seconds |
| Started | Aug 27 05:35:08 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940467166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.940467166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.1429486149 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 225679668 ps |
| CPU time | 4.18 seconds |
| Started | Aug 27 05:35:07 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 219440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429486149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1429486149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_random.3825858576 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 741573690 ps |
| CPU time | 4.71 seconds |
| Started | Aug 27 05:35:05 AM UTC 24 |
| Finished | Aug 27 05:35:11 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825858576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3825858576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.3820002499 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 64309878 ps |
| CPU time | 2.72 seconds |
| Started | Aug 27 05:35:03 AM UTC 24 |
| Finished | Aug 27 05:35:08 AM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820002499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3820002499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.3888415129 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 458634041 ps |
| CPU time | 3.11 seconds |
| Started | Aug 27 05:35:04 AM UTC 24 |
| Finished | Aug 27 05:35:09 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888415129 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3888415129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.1765747790 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 29874951 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 05:35:04 AM UTC 24 |
| Finished | Aug 27 05:35:07 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765747790 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1765747790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.531574226 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 148955251 ps |
| CPU time | 2.49 seconds |
| Started | Aug 27 05:35:05 AM UTC 24 |
| Finished | Aug 27 05:35:09 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531574226 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.531574226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.4081697371 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 843371294 ps |
| CPU time | 5.46 seconds |
| Started | Aug 27 05:35:08 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081697371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4081697371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.539943285 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 5908142234 ps |
| CPU time | 22.65 seconds |
| Started | Aug 27 05:35:03 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539943285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.539943285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.4246220112 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4459534591 ps |
| CPU time | 26.53 seconds |
| Started | Aug 27 05:35:09 AM UTC 24 |
| Finished | Aug 27 05:35:37 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246220112 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4246220112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.3139010534 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 232810353 ps |
| CPU time | 10.48 seconds |
| Started | Aug 27 05:35:09 AM UTC 24 |
| Finished | Aug 27 05:35:21 AM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3139010534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.3139010534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.1791092028 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 351056521 ps |
| CPU time | 3.65 seconds |
| Started | Aug 27 05:35:08 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 225912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791092028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1791092028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.202294685 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 164195038 ps |
| CPU time | 1.91 seconds |
| Started | Aug 27 05:35:09 AM UTC 24 |
| Finished | Aug 27 05:35:12 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202294685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.202294685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.1998776275 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 40996335 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 05:35:13 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998776275 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1998776275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.99453836 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 127881599 ps |
| CPU time | 3.05 seconds |
| Started | Aug 27 05:35:11 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 223556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99453836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.99453836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.3194045630 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 54839437 ps |
| CPU time | 3.37 seconds |
| Started | Aug 27 05:35:12 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 230256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194045630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3194045630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.3661886795 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 72693744 ps |
| CPU time | 3.46 seconds |
| Started | Aug 27 05:35:11 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661886795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3661886795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.3148688907 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 205423859 ps |
| CPU time | 6.66 seconds |
| Started | Aug 27 05:35:12 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148688907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3148688907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.2890800590 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 42879753 ps |
| CPU time | 3.3 seconds |
| Started | Aug 27 05:35:12 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890800590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2890800590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_random.929225228 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 510252163 ps |
| CPU time | 9.47 seconds |
| Started | Aug 27 05:35:11 AM UTC 24 |
| Finished | Aug 27 05:35:21 AM UTC 24 |
| Peak memory | 217392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929225228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.929225228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.2029153094 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 70045885 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 05:35:09 AM UTC 24 |
| Finished | Aug 27 05:35:12 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029153094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2029153094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.2170224608 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1421340577 ps |
| CPU time | 12.8 seconds |
| Started | Aug 27 05:35:10 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170224608 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2170224608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.3371424482 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 344515584 ps |
| CPU time | 5.94 seconds |
| Started | Aug 27 05:35:09 AM UTC 24 |
| Finished | Aug 27 05:35:17 AM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371424482 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3371424482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.4254144969 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 60590412 ps |
| CPU time | 3.61 seconds |
| Started | Aug 27 05:35:10 AM UTC 24 |
| Finished | Aug 27 05:35:15 AM UTC 24 |
| Peak memory | 217812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254144969 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4254144969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.3978312789 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 86226664 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 05:35:12 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978312789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3978312789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.2648560386 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 81328452 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 05:35:09 AM UTC 24 |
| Finished | Aug 27 05:35:13 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648560386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2648560386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.1942854958 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 557241269 ps |
| CPU time | 9.67 seconds |
| Started | Aug 27 05:35:13 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 228200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942854958 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1942854958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.585168363 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 118649613 ps |
| CPU time | 3.92 seconds |
| Started | Aug 27 05:35:11 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585168363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.585168363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.3289142240 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 536633359 ps |
| CPU time | 2.15 seconds |
| Started | Aug 27 05:35:13 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289142240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3289142240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.3130080061 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 67388713 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:18 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130080061 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3130080061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.2390448823 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 89969840 ps |
| CPU time | 4.57 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390448823 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2390448823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.2876522635 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 79283979 ps |
| CPU time | 3.04 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:19 AM UTC 24 |
| Peak memory | 231264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876522635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2876522635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.3505424081 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 300337416 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:19 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505424081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3505424081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.2974773741 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 67968218 ps |
| CPU time | 2.57 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:18 AM UTC 24 |
| Peak memory | 231032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974773741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2974773741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.3066049320 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 132155914 ps |
| CPU time | 4 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066049320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3066049320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_random.3615730886 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 104125991 ps |
| CPU time | 3.12 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:19 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615730886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3615730886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.2042140058 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 118369095 ps |
| CPU time | 2.53 seconds |
| Started | Aug 27 05:35:13 AM UTC 24 |
| Finished | Aug 27 05:35:17 AM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042140058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2042140058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.1566676335 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 122760327 ps |
| CPU time | 4.51 seconds |
| Started | Aug 27 05:35:14 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566676335 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1566676335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.1006362091 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 99121717 ps |
| CPU time | 1.83 seconds |
| Started | Aug 27 05:35:14 AM UTC 24 |
| Finished | Aug 27 05:35:17 AM UTC 24 |
| Peak memory | 215692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006362091 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1006362091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.3786258987 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 24544064 ps |
| CPU time | 2 seconds |
| Started | Aug 27 05:35:14 AM UTC 24 |
| Finished | Aug 27 05:35:18 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786258987 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3786258987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.1607168564 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 34939932 ps |
| CPU time | 2.59 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:18 AM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607168564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1607168564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.2676871880 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 37098456 ps |
| CPU time | 1.97 seconds |
| Started | Aug 27 05:35:13 AM UTC 24 |
| Finished | Aug 27 05:35:16 AM UTC 24 |
| Peak memory | 214236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676871880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2676871880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.175724802 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 913873617 ps |
| CPU time | 15.76 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:33 AM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175724802 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.175724802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.1788443126 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 176100278 ps |
| CPU time | 10.67 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 231164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1788443126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg r_stress_all_with_rand_reset.1788443126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.2971145279 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 310791366 ps |
| CPU time | 8.83 seconds |
| Started | Aug 27 05:35:15 AM UTC 24 |
| Finished | Aug 27 05:35:25 AM UTC 24 |
| Peak memory | 224352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971145279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2971145279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.1799023888 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 110649625 ps |
| CPU time | 2.78 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799023888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1799023888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.2159682400 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 12572408 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:21 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159682400 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2159682400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.733257940 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 197370544 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:21 AM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733257940 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.733257940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.404923625 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 83385425 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:21 AM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404923625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.404923625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.2439573780 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 272393316 ps |
| CPU time | 3.24 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:23 AM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439573780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2439573780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1178637906 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 112242217 ps |
| CPU time | 3.71 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:23 AM UTC 24 |
| Peak memory | 224304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178637906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1178637906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.2996014413 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 75784545 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:23 AM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996014413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2996014413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_random.2661526724 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 645992555 ps |
| CPU time | 8.91 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:26 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661526724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2661526724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.438421039 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 95234457 ps |
| CPU time | 2.44 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438421039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.438421039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.2630022457 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 270422342 ps |
| CPU time | 4.93 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:22 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630022457 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2630022457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.3476496844 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 175836850 ps |
| CPU time | 6.19 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476496844 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3476496844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.3838618066 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 201060655 ps |
| CPU time | 1.61 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:19 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838618066 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3838618066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.3129673378 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 184693806 ps |
| CPU time | 2.15 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:22 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129673378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3129673378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.216756160 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 52316815 ps |
| CPU time | 2.77 seconds |
| Started | Aug 27 05:35:16 AM UTC 24 |
| Finished | Aug 27 05:35:20 AM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216756160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.216756160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.2356184413 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1486208986 ps |
| CPU time | 39.14 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:36:00 AM UTC 24 |
| Peak memory | 230504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356184413 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2356184413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.4293168616 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 123652106 ps |
| CPU time | 5.09 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:25 AM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293168616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4293168616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.2481058540 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 87890159 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:21 AM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481058540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2481058540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.327538140 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 10330881 ps |
| CPU time | 0.81 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:26 AM UTC 24 |
| Peak memory | 213660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327538140 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.327538140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.3008766605 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 233752288 ps |
| CPU time | 3.56 seconds |
| Started | Aug 27 05:35:19 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008766605 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3008766605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.373773954 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 135842055 ps |
| CPU time | 4.52 seconds |
| Started | Aug 27 05:35:20 AM UTC 24 |
| Finished | Aug 27 05:35:25 AM UTC 24 |
| Peak memory | 232600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373773954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.373773954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.3679308202 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 140024339 ps |
| CPU time | 3.62 seconds |
| Started | Aug 27 05:35:19 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 217864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679308202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3679308202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.1971297644 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 93224042 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 05:35:20 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971297644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1971297644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.707040326 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 251670052 ps |
| CPU time | 2.48 seconds |
| Started | Aug 27 05:35:20 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707040326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.707040326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.272665710 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 647841571 ps |
| CPU time | 6.52 seconds |
| Started | Aug 27 05:35:19 AM UTC 24 |
| Finished | Aug 27 05:35:27 AM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272665710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.272665710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_random.3263376879 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 450207052 ps |
| CPU time | 3.41 seconds |
| Started | Aug 27 05:35:19 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263376879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3263376879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.685521369 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 96217902 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:24 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685521369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.685521369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.4144510031 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 102477273 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 05:35:19 AM UTC 24 |
| Finished | Aug 27 05:35:23 AM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144510031 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4144510031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.2041748002 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 350121114 ps |
| CPU time | 4.78 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:25 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041748002 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2041748002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.3876379321 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 400258467 ps |
| CPU time | 7.17 seconds |
| Started | Aug 27 05:35:19 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876379321 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3876379321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.2677915786 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 146634186 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 05:35:20 AM UTC 24 |
| Finished | Aug 27 05:35:23 AM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677915786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2677915786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.2558420843 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 178913249 ps |
| CPU time | 4.76 seconds |
| Started | Aug 27 05:35:18 AM UTC 24 |
| Finished | Aug 27 05:35:25 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558420843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2558420843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.4082320779 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 5826784938 ps |
| CPU time | 53 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:36:19 AM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082320779 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4082320779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.1626016686 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 120955677 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 05:35:20 AM UTC 24 |
| Finished | Aug 27 05:35:23 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626016686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1626016686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.4211975051 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 120105862 ps |
| CPU time | 3.61 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:29 AM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211975051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4211975051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.4259830828 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 90035207 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 05:35:24 AM UTC 24 |
| Finished | Aug 27 05:35:27 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259830828 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4259830828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.1747600793 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 721958295 ps |
| CPU time | 8.29 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:34 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747600793 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1747600793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.1371518386 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 230875242 ps |
| CPU time | 1.43 seconds |
| Started | Aug 27 05:35:22 AM UTC 24 |
| Finished | Aug 27 05:35:32 AM UTC 24 |
| Peak memory | 230280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371518386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1371518386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.2252008955 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 42927535 ps |
| CPU time | 1.83 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252008955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2252008955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.1621362685 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4122506954 ps |
| CPU time | 20.02 seconds |
| Started | Aug 27 05:35:22 AM UTC 24 |
| Finished | Aug 27 05:35:50 AM UTC 24 |
| Peak memory | 222692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621362685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1621362685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.671102128 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 383037611 ps |
| CPU time | 2.81 seconds |
| Started | Aug 27 05:35:22 AM UTC 24 |
| Finished | Aug 27 05:35:33 AM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671102128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.671102128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.3650885571 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 38887823 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:35:22 AM UTC 24 |
| Finished | Aug 27 05:35:32 AM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650885571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3650885571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_random.1632384333 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 7347163469 ps |
| CPU time | 35.24 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:36:01 AM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632384333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1632384333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.447415133 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 196902342 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447415133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.447415133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.3058590370 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 567701949 ps |
| CPU time | 3.9 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:30 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058590370 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3058590370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.72038812 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 464241333 ps |
| CPU time | 1.85 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:27 AM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72038812 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.72038812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.959838865 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2267029076 ps |
| CPU time | 27.38 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:53 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959838865 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.959838865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.2214132551 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 217571936 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 05:35:22 AM UTC 24 |
| Finished | Aug 27 05:35:34 AM UTC 24 |
| Peak memory | 224176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214132551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2214132551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.3775175784 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 520596679 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 05:35:21 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775175784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3775175784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.2321822825 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 15781162474 ps |
| CPU time | 100.43 seconds |
| Started | Aug 27 05:35:24 AM UTC 24 |
| Finished | Aug 27 05:37:08 AM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321822825 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2321822825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.1223319824 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 77146762 ps |
| CPU time | 3.07 seconds |
| Started | Aug 27 05:35:22 AM UTC 24 |
| Finished | Aug 27 05:35:33 AM UTC 24 |
| Peak memory | 217204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223319824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1223319824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.893921352 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 796538895 ps |
| CPU time | 7.59 seconds |
| Started | Aug 27 05:35:22 AM UTC 24 |
| Finished | Aug 27 05:35:38 AM UTC 24 |
| Peak memory | 220100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893921352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.893921352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.2565273736 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 37379363 ps |
| CPU time | 1 seconds |
| Started | Aug 27 05:35:26 AM UTC 24 |
| Finished | Aug 27 05:35:42 AM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565273736 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2565273736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.605355793 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 820795485 ps |
| CPU time | 10.18 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:40 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605355793 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.605355793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.3259033015 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 133217207 ps |
| CPU time | 3.23 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:33 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259033015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3259033015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.3106969544 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 76782121 ps |
| CPU time | 1.37 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:31 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106969544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3106969544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.4139829166 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 758019361 ps |
| CPU time | 3.86 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:34 AM UTC 24 |
| Peak memory | 224764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139829166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4139829166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.966047689 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 292804838 ps |
| CPU time | 3.69 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:34 AM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966047689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.966047689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.1754267450 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 163657095 ps |
| CPU time | 3.85 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:34 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754267450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1754267450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_random.2031891696 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 348948601 ps |
| CPU time | 5.38 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:35 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031891696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2031891696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.1087505473 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 128132827 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 05:35:24 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087505473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1087505473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.266708296 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 259865109 ps |
| CPU time | 2.36 seconds |
| Started | Aug 27 05:35:24 AM UTC 24 |
| Finished | Aug 27 05:35:27 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266708296 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.266708296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.654553997 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 103370951 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 05:35:24 AM UTC 24 |
| Finished | Aug 27 05:35:26 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654553997 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.654553997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.3841826618 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 51549369 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 05:35:24 AM UTC 24 |
| Finished | Aug 27 05:35:28 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841826618 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3841826618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.2335266741 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 20445676 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:31 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335266741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2335266741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.3008516182 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 78378818 ps |
| CPU time | 2.67 seconds |
| Started | Aug 27 05:35:24 AM UTC 24 |
| Finished | Aug 27 05:35:27 AM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008516182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3008516182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.3917112139 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 10400602857 ps |
| CPU time | 27.55 seconds |
| Started | Aug 27 05:35:26 AM UTC 24 |
| Finished | Aug 27 05:36:09 AM UTC 24 |
| Peak memory | 226216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917112139 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3917112139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all_with_rand_reset.2534307295 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 417351949 ps |
| CPU time | 17.12 seconds |
| Started | Aug 27 05:35:26 AM UTC 24 |
| Finished | Aug 27 05:35:58 AM UTC 24 |
| Peak memory | 232632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2534307295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymg r_stress_all_with_rand_reset.2534307295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.3914126013 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 309539431 ps |
| CPU time | 8.79 seconds |
| Started | Aug 27 05:35:25 AM UTC 24 |
| Finished | Aug 27 05:35:39 AM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914126013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3914126013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.3115058235 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 94856964 ps |
| CPU time | 1.68 seconds |
| Started | Aug 27 05:35:26 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115058235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3115058235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.139832487 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 31183557 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:41 AM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139832487 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.139832487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.232188053 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 141618610 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:33 AM UTC 24 |
| Peak memory | 224444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232188053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.232188053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.189045524 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 627242944 ps |
| CPU time | 4.43 seconds |
| Started | Aug 27 05:35:28 AM UTC 24 |
| Finished | Aug 27 05:35:35 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189045524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.189045524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.900313297 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 180282179 ps |
| CPU time | 1.75 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:32 AM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900313297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.900313297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.3289831606 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 65399647 ps |
| CPU time | 2.87 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:33 AM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289831606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3289831606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.1019577892 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 44355111 ps |
| CPU time | 2.66 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:33 AM UTC 24 |
| Peak memory | 230744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019577892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1019577892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_random.3065805109 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 86236831 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 05:35:28 AM UTC 24 |
| Finished | Aug 27 05:35:39 AM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065805109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3065805109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.1994097500 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 144043439 ps |
| CPU time | 4.14 seconds |
| Started | Aug 27 05:35:26 AM UTC 24 |
| Finished | Aug 27 05:35:45 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994097500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1994097500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.3005756120 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 35637686 ps |
| CPU time | 1.48 seconds |
| Started | Aug 27 05:35:28 AM UTC 24 |
| Finished | Aug 27 05:35:37 AM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005756120 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3005756120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.338527581 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 556070527 ps |
| CPU time | 3.87 seconds |
| Started | Aug 27 05:35:28 AM UTC 24 |
| Finished | Aug 27 05:35:40 AM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338527581 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.338527581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.3772937828 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 899429476 ps |
| CPU time | 4.82 seconds |
| Started | Aug 27 05:35:28 AM UTC 24 |
| Finished | Aug 27 05:35:35 AM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772937828 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3772937828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.3947621115 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 34677271 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:42 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947621115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3947621115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.1529220390 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 173706994 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 05:35:26 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529220390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1529220390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.1354070364 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 65096534 ps |
| CPU time | 3.2 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354070364 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1354070364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.2257164581 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1760897864 ps |
| CPU time | 15.95 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2257164581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.2257164581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.3142960728 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 285102872 ps |
| CPU time | 8.53 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:49 AM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142960728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3142960728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.3087255945 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 3524709847 ps |
| CPU time | 15.83 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:47 AM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087255945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3087255945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2783958932 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 19533799 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:35:36 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783958932 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2783958932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.1548311191 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 31138478 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 05:35:31 AM UTC 24 |
| Finished | Aug 27 05:35:38 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548311191 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1548311191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.3512797846 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 92635488 ps |
| CPU time | 4.82 seconds |
| Started | Aug 27 05:35:33 AM UTC 24 |
| Finished | Aug 27 05:35:46 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512797846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3512797846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.3216998307 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 76658784 ps |
| CPU time | 1.47 seconds |
| Started | Aug 27 05:35:32 AM UTC 24 |
| Finished | Aug 27 05:35:42 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216998307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3216998307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.2368390806 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 221392754 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 05:35:33 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368390806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2368390806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.3424618383 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 237499637 ps |
| CPU time | 2.21 seconds |
| Started | Aug 27 05:35:33 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 231172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424618383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3424618383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.3275306188 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 197244199 ps |
| CPU time | 1.63 seconds |
| Started | Aug 27 05:35:33 AM UTC 24 |
| Finished | Aug 27 05:35:42 AM UTC 24 |
| Peak memory | 224480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275306188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3275306188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_random.3120729754 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 349929854 ps |
| CPU time | 8.7 seconds |
| Started | Aug 27 05:35:31 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 224292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120729754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3120729754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.1204603595 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 85684524 ps |
| CPU time | 2.89 seconds |
| Started | Aug 27 05:35:30 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204603595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1204603595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.3163398607 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 146709626 ps |
| CPU time | 2.67 seconds |
| Started | Aug 27 05:35:30 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163398607 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3163398607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.3646886279 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 144939214 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 05:35:30 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646886279 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3646886279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.2971777720 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 141703799 ps |
| CPU time | 2.17 seconds |
| Started | Aug 27 05:35:30 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971777720 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2971777720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.4078330756 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 26074291 ps |
| CPU time | 1.72 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:35:37 AM UTC 24 |
| Peak memory | 216220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078330756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4078330756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.4099518329 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 237751429 ps |
| CPU time | 2.17 seconds |
| Started | Aug 27 05:35:29 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099518329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.4099518329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1363390983 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1692524457 ps |
| CPU time | 17.96 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:35:53 AM UTC 24 |
| Peak memory | 232180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363390983 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1363390983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.2694993536 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1092806616 ps |
| CPU time | 12.87 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:35:48 AM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2694993536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg r_stress_all_with_rand_reset.2694993536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.4272721050 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2141876105 ps |
| CPU time | 55.68 seconds |
| Started | Aug 27 05:35:33 AM UTC 24 |
| Finished | Aug 27 05:36:37 AM UTC 24 |
| Peak memory | 230168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272721050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.4272721050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.651924513 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 829913527 ps |
| CPU time | 2.43 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:35:37 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651924513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.651924513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.863855803 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 27729725 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 05:35:39 AM UTC 24 |
| Finished | Aug 27 05:35:40 AM UTC 24 |
| Peak memory | 213660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863855803 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.863855803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.2705527294 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 58177530 ps |
| CPU time | 1.55 seconds |
| Started | Aug 27 05:35:35 AM UTC 24 |
| Finished | Aug 27 05:35:41 AM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705527294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2705527294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.3626925810 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 280645003 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 05:35:36 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626925810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3626925810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.1497310436 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 78881931 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 05:35:36 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 224240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497310436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1497310436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.156445275 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 164120736 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 05:35:35 AM UTC 24 |
| Finished | Aug 27 05:35:42 AM UTC 24 |
| Peak memory | 213880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156445275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.156445275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_random.2187656396 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 1560681831 ps |
| CPU time | 9.53 seconds |
| Started | Aug 27 05:35:35 AM UTC 24 |
| Finished | Aug 27 05:35:46 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187656396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2187656396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.4202970925 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 84555799 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:35:38 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202970925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.4202970925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.2323815889 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 106540472 ps |
| CPU time | 2.44 seconds |
| Started | Aug 27 05:35:35 AM UTC 24 |
| Finished | Aug 27 05:35:42 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323815889 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2323815889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.409653540 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 412259227 ps |
| CPU time | 5.02 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:35:40 AM UTC 24 |
| Peak memory | 216184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409653540 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.409653540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.1536697062 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 158112553 ps |
| CPU time | 4.17 seconds |
| Started | Aug 27 05:35:35 AM UTC 24 |
| Finished | Aug 27 05:35:44 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536697062 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1536697062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.3176793944 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 275976322 ps |
| CPU time | 3.87 seconds |
| Started | Aug 27 05:35:39 AM UTC 24 |
| Finished | Aug 27 05:35:45 AM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176793944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3176793944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.2543056591 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 6909559984 ps |
| CPU time | 45.03 seconds |
| Started | Aug 27 05:35:34 AM UTC 24 |
| Finished | Aug 27 05:36:21 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543056591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2543056591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.2258650132 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3403475433 ps |
| CPU time | 28.24 seconds |
| Started | Aug 27 05:35:39 AM UTC 24 |
| Finished | Aug 27 05:36:08 AM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258650132 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2258650132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.215138937 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 549537687 ps |
| CPU time | 15.71 seconds |
| Started | Aug 27 05:35:39 AM UTC 24 |
| Finished | Aug 27 05:35:56 AM UTC 24 |
| Peak memory | 232392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=215138937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr _stress_all_with_rand_reset.215138937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.20010245 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 66555258 ps |
| CPU time | 2.73 seconds |
| Started | Aug 27 05:35:36 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20010245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.20010245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.3916588378 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 141049732 ps |
| CPU time | 1.56 seconds |
| Started | Aug 27 05:35:39 AM UTC 24 |
| Finished | Aug 27 05:35:43 AM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916588378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3916588378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.1495305870 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 157692637 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 05:32:37 AM UTC 24 |
| Finished | Aug 27 05:32:39 AM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495305870 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1495305870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.2395774270 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 555732339 ps |
| CPU time | 4.77 seconds |
| Started | Aug 27 05:32:36 AM UTC 24 |
| Finished | Aug 27 05:32:42 AM UTC 24 |
| Peak memory | 228200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395774270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2395774270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.2913501934 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 63389895 ps |
| CPU time | 3 seconds |
| Started | Aug 27 05:32:34 AM UTC 24 |
| Finished | Aug 27 05:32:38 AM UTC 24 |
| Peak memory | 230164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913501934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2913501934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.553768499 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 120691187 ps |
| CPU time | 3.73 seconds |
| Started | Aug 27 05:32:36 AM UTC 24 |
| Finished | Aug 27 05:32:41 AM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553768499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.553768499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.3313269017 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 63848769 ps |
| CPU time | 2.94 seconds |
| Started | Aug 27 05:32:36 AM UTC 24 |
| Finished | Aug 27 05:32:40 AM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313269017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3313269017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.1054350299 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 78616670 ps |
| CPU time | 3.78 seconds |
| Started | Aug 27 05:32:34 AM UTC 24 |
| Finished | Aug 27 05:32:39 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054350299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1054350299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.3441466499 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 125306239 ps |
| CPU time | 4.35 seconds |
| Started | Aug 27 05:32:32 AM UTC 24 |
| Finished | Aug 27 05:32:38 AM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441466499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3441466499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.2163697685 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 413891619 ps |
| CPU time | 3.87 seconds |
| Started | Aug 27 05:32:32 AM UTC 24 |
| Finished | Aug 27 05:32:37 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163697685 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2163697685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.3809175254 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 103511859 ps |
| CPU time | 5.66 seconds |
| Started | Aug 27 05:32:32 AM UTC 24 |
| Finished | Aug 27 05:32:39 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809175254 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3809175254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.2750150275 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2671738334 ps |
| CPU time | 18 seconds |
| Started | Aug 27 05:32:34 AM UTC 24 |
| Finished | Aug 27 05:32:53 AM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750150275 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2750150275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.4000971841 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 211288636 ps |
| CPU time | 3.37 seconds |
| Started | Aug 27 05:32:36 AM UTC 24 |
| Finished | Aug 27 05:32:41 AM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000971841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4000971841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.3347312541 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 85733315 ps |
| CPU time | 4.8 seconds |
| Started | Aug 27 05:32:32 AM UTC 24 |
| Finished | Aug 27 05:32:38 AM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347312541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3347312541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.1194760449 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 174963691 ps |
| CPU time | 5.37 seconds |
| Started | Aug 27 05:32:35 AM UTC 24 |
| Finished | Aug 27 05:32:41 AM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194760449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1194760449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.3331660376 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 517751011 ps |
| CPU time | 9.49 seconds |
| Started | Aug 27 05:32:36 AM UTC 24 |
| Finished | Aug 27 05:32:47 AM UTC 24 |
| Peak memory | 219936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331660376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3331660376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.1248281319 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 264267404 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 05:32:42 AM UTC 24 |
| Finished | Aug 27 05:32:44 AM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248281319 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1248281319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3019158352 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 61901015 ps |
| CPU time | 4.43 seconds |
| Started | Aug 27 05:32:39 AM UTC 24 |
| Finished | Aug 27 05:32:44 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019158352 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3019158352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.2129432865 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 173176637 ps |
| CPU time | 3.44 seconds |
| Started | Aug 27 05:32:40 AM UTC 24 |
| Finished | Aug 27 05:32:45 AM UTC 24 |
| Peak memory | 218616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129432865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2129432865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.1744812933 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 65767568 ps |
| CPU time | 3.56 seconds |
| Started | Aug 27 05:32:39 AM UTC 24 |
| Finished | Aug 27 05:32:43 AM UTC 24 |
| Peak memory | 218372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744812933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1744812933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.1485857301 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 293688043 ps |
| CPU time | 2.75 seconds |
| Started | Aug 27 05:32:40 AM UTC 24 |
| Finished | Aug 27 05:32:44 AM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485857301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1485857301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.562883720 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 67403293 ps |
| CPU time | 2.56 seconds |
| Started | Aug 27 05:32:40 AM UTC 24 |
| Finished | Aug 27 05:32:44 AM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562883720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.562883720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_random.1652510864 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 992994585 ps |
| CPU time | 4.83 seconds |
| Started | Aug 27 05:32:39 AM UTC 24 |
| Finished | Aug 27 05:32:45 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652510864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1652510864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.366491240 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 167659977 ps |
| CPU time | 5.33 seconds |
| Started | Aug 27 05:32:37 AM UTC 24 |
| Finished | Aug 27 05:32:44 AM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366491240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.366491240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.1458635698 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 59767007 ps |
| CPU time | 3.07 seconds |
| Started | Aug 27 05:32:39 AM UTC 24 |
| Finished | Aug 27 05:32:43 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458635698 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1458635698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.324629526 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 62967681 ps |
| CPU time | 3.03 seconds |
| Started | Aug 27 05:32:39 AM UTC 24 |
| Finished | Aug 27 05:32:43 AM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324629526 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.324629526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.1650806675 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 394717177 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 05:32:39 AM UTC 24 |
| Finished | Aug 27 05:32:43 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650806675 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1650806675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.1206476870 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 77319421 ps |
| CPU time | 2.42 seconds |
| Started | Aug 27 05:32:41 AM UTC 24 |
| Finished | Aug 27 05:32:45 AM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206476870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1206476870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.3530349339 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 5243227212 ps |
| CPU time | 40.59 seconds |
| Started | Aug 27 05:32:37 AM UTC 24 |
| Finished | Aug 27 05:33:19 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530349339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3530349339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.1554269806 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 327536972 ps |
| CPU time | 9.04 seconds |
| Started | Aug 27 05:32:42 AM UTC 24 |
| Finished | Aug 27 05:32:52 AM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1554269806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr _stress_all_with_rand_reset.1554269806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.2027906651 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 270054395 ps |
| CPU time | 6.72 seconds |
| Started | Aug 27 05:32:40 AM UTC 24 |
| Finished | Aug 27 05:32:48 AM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027906651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2027906651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3538014244 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1038171850 ps |
| CPU time | 6.2 seconds |
| Started | Aug 27 05:32:42 AM UTC 24 |
| Finished | Aug 27 05:32:49 AM UTC 24 |
| Peak memory | 219932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538014244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3538014244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.852232580 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 15311994 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:32:48 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852232580 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.852232580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.3188433443 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 120142972 ps |
| CPU time | 2.05 seconds |
| Started | Aug 27 05:32:44 AM UTC 24 |
| Finished | Aug 27 05:32:47 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188433443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3188433443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.3800175988 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 29879497 ps |
| CPU time | 2.13 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:32:49 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800175988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3800175988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.4289109726 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 132896327 ps |
| CPU time | 4.5 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:32:51 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289109726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.4289109726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.3372809025 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 201270438 ps |
| CPU time | 4.31 seconds |
| Started | Aug 27 05:32:44 AM UTC 24 |
| Finished | Aug 27 05:32:50 AM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372809025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3372809025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_random.980656082 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 541111906 ps |
| CPU time | 4.49 seconds |
| Started | Aug 27 05:32:44 AM UTC 24 |
| Finished | Aug 27 05:32:50 AM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980656082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.980656082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.4282675786 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 25733183 ps |
| CPU time | 2.08 seconds |
| Started | Aug 27 05:32:43 AM UTC 24 |
| Finished | Aug 27 05:32:46 AM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282675786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4282675786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.490551923 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 66554394 ps |
| CPU time | 3.58 seconds |
| Started | Aug 27 05:32:43 AM UTC 24 |
| Finished | Aug 27 05:32:48 AM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490551923 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.490551923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.1365059571 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 21040264 ps |
| CPU time | 1.75 seconds |
| Started | Aug 27 05:32:43 AM UTC 24 |
| Finished | Aug 27 05:32:46 AM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365059571 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1365059571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.901226199 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 128822062 ps |
| CPU time | 2.39 seconds |
| Started | Aug 27 05:32:44 AM UTC 24 |
| Finished | Aug 27 05:32:48 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901226199 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.901226199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.941357315 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 73049555 ps |
| CPU time | 1.66 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:32:48 AM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941357315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.941357315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.1741447076 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 124815025 ps |
| CPU time | 2.13 seconds |
| Started | Aug 27 05:32:43 AM UTC 24 |
| Finished | Aug 27 05:32:46 AM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741447076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1741447076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.2606248340 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 8731697135 ps |
| CPU time | 52.15 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:33:39 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606248340 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2606248340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.4098762447 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 344756374 ps |
| CPU time | 5.42 seconds |
| Started | Aug 27 05:32:44 AM UTC 24 |
| Finished | Aug 27 05:32:51 AM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098762447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4098762447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.3366921117 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 346811434 ps |
| CPU time | 6.21 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:32:53 AM UTC 24 |
| Peak memory | 220264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366921117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3366921117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.2244003374 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 49883464 ps |
| CPU time | 1.39 seconds |
| Started | Aug 27 05:32:50 AM UTC 24 |
| Finished | Aug 27 05:32:52 AM UTC 24 |
| Peak memory | 213576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244003374 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2244003374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.504359470 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 64319060 ps |
| CPU time | 5.34 seconds |
| Started | Aug 27 05:32:47 AM UTC 24 |
| Finished | Aug 27 05:32:54 AM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504359470 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.504359470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.1002356940 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 133919441 ps |
| CPU time | 4.28 seconds |
| Started | Aug 27 05:32:48 AM UTC 24 |
| Finished | Aug 27 05:32:54 AM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002356940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1002356940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.1483859827 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 130249142 ps |
| CPU time | 5.09 seconds |
| Started | Aug 27 05:32:49 AM UTC 24 |
| Finished | Aug 27 05:32:55 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483859827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1483859827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.1528718206 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 108994172 ps |
| CPU time | 3.52 seconds |
| Started | Aug 27 05:32:48 AM UTC 24 |
| Finished | Aug 27 05:32:53 AM UTC 24 |
| Peak memory | 230184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528718206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1528718206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_random.2408582807 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 40913231 ps |
| CPU time | 3.62 seconds |
| Started | Aug 27 05:32:47 AM UTC 24 |
| Finished | Aug 27 05:32:52 AM UTC 24 |
| Peak memory | 220172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408582807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2408582807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.3870135389 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1653359306 ps |
| CPU time | 17.44 seconds |
| Started | Aug 27 05:32:47 AM UTC 24 |
| Finished | Aug 27 05:33:06 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870135389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3870135389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.4085879989 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 348075958 ps |
| CPU time | 6.22 seconds |
| Started | Aug 27 05:32:47 AM UTC 24 |
| Finished | Aug 27 05:32:54 AM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085879989 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4085879989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.383599963 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 92116703 ps |
| CPU time | 2.98 seconds |
| Started | Aug 27 05:32:47 AM UTC 24 |
| Finished | Aug 27 05:32:51 AM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383599963 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.383599963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.190116744 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1094243164 ps |
| CPU time | 3.61 seconds |
| Started | Aug 27 05:32:47 AM UTC 24 |
| Finished | Aug 27 05:32:52 AM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190116744 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.190116744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3801485029 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 37993482 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 05:32:50 AM UTC 24 |
| Finished | Aug 27 05:32:53 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801485029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3801485029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1262178238 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 4466431010 ps |
| CPU time | 19.18 seconds |
| Started | Aug 27 05:32:46 AM UTC 24 |
| Finished | Aug 27 05:33:06 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262178238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1262178238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all_with_rand_reset.3633549703 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 176081443 ps |
| CPU time | 7.12 seconds |
| Started | Aug 27 05:32:50 AM UTC 24 |
| Finished | Aug 27 05:32:58 AM UTC 24 |
| Peak memory | 232636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3633549703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr _stress_all_with_rand_reset.3633549703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.634045961 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 732778354 ps |
| CPU time | 16.95 seconds |
| Started | Aug 27 05:32:49 AM UTC 24 |
| Finished | Aug 27 05:33:07 AM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634045961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.634045961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.3082042778 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5447749130 ps |
| CPU time | 7.5 seconds |
| Started | Aug 27 05:32:50 AM UTC 24 |
| Finished | Aug 27 05:32:58 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082042778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3082042778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.3118190335 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 9874752 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 05:32:54 AM UTC 24 |
| Finished | Aug 27 05:32:56 AM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118190335 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3118190335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.2844029091 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 270100099 ps |
| CPU time | 2.88 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:57 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844029091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2844029091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.3526331474 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 95725794 ps |
| CPU time | 3.57 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:57 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526331474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3526331474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.4046895002 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 241499050 ps |
| CPU time | 4.38 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:58 AM UTC 24 |
| Peak memory | 224304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046895002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4046895002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.2159797240 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 247633337 ps |
| CPU time | 4.47 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:58 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159797240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2159797240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_random.2299134432 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 26483021 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:56 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299134432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2299134432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.2990368962 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1598202869 ps |
| CPU time | 37.89 seconds |
| Started | Aug 27 05:32:51 AM UTC 24 |
| Finished | Aug 27 05:33:31 AM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990368962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2990368962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.3952103337 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 297340168 ps |
| CPU time | 5.81 seconds |
| Started | Aug 27 05:32:51 AM UTC 24 |
| Finished | Aug 27 05:32:58 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952103337 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3952103337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.910892243 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 115520595 ps |
| CPU time | 2.43 seconds |
| Started | Aug 27 05:32:51 AM UTC 24 |
| Finished | Aug 27 05:32:55 AM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910892243 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.910892243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.1582044382 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 93812534 ps |
| CPU time | 2.89 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:57 AM UTC 24 |
| Peak memory | 216180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582044382 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1582044382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.3455961085 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 90129825 ps |
| CPU time | 3.15 seconds |
| Started | Aug 27 05:32:54 AM UTC 24 |
| Finished | Aug 27 05:32:58 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455961085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3455961085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.539679012 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 585699143 ps |
| CPU time | 4.77 seconds |
| Started | Aug 27 05:32:51 AM UTC 24 |
| Finished | Aug 27 05:32:57 AM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539679012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.539679012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.3629222227 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 846767004 ps |
| CPU time | 29.95 seconds |
| Started | Aug 27 05:32:54 AM UTC 24 |
| Finished | Aug 27 05:33:25 AM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629222227 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3629222227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.3931607000 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1070743792 ps |
| CPU time | 9.3 seconds |
| Started | Aug 27 05:32:54 AM UTC 24 |
| Finished | Aug 27 05:33:05 AM UTC 24 |
| Peak memory | 232380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3931607000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr _stress_all_with_rand_reset.3931607000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.886095520 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 476565591 ps |
| CPU time | 4.88 seconds |
| Started | Aug 27 05:32:53 AM UTC 24 |
| Finished | Aug 27 05:32:59 AM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886095520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.886095520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.1200097215 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 60732753 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 05:32:54 AM UTC 24 |
| Finished | Aug 27 05:32:57 AM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200097215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1200097215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |