| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 83.33 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 12 | 2 | 10 | 83.33 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| fault_cp | 12 | 2 | 10 | 83.33 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 12 | 2 | 10 | 83.33 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| auto[FaultKmacOp] | 0 | 1 | 1 | |
| auto[FaultKmacOut] | 0 | 1 | 1 |
| NAME | COUNT | STATUS |
| auto[FaultRegIntg] | 0 | Excluded |
| auto[FaultShadow] | 0 | Excluded |
| auto[FaultLastPos] | 0 | Illegal |
| illegal | 0 | Illegal |
| ignore | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[FaultKmacCmd] | 17 | 1 | T25 | 1 | T26 | 1 | T31 | 1 | ||||
| auto[FaultKmacFsm] | 180 | 1 | T11 | 40 | T12 | 20 | T13 | 40 | ||||
| auto[FaultKmacDone] | 10 | 1 | T28 | 1 | T29 | 1 | T30 | 1 | ||||
| auto[FaultCtrlFsm] | 270 | 1 | T11 | 60 | T12 | 30 | T13 | 60 | ||||
| auto[FaultCtrlFsmChk] | 5 | 1 | T5 | 1 | T27 | 1 | T20 | 1 | ||||
| auto[FaultCtrlCnt] | 90 | 1 | T11 | 20 | T12 | 10 | T13 | 20 | ||||
| auto[FaultReseedCnt] | 90 | 1 | T11 | 20 | T12 | 10 | T13 | 20 | ||||
| auto[FaultSideFsm] | 90 | 1 | T11 | 20 | T12 | 10 | T13 | 20 | ||||
| auto[FaultSideSel] | 10 | 1 | T38 | 1 | T39 | 1 | T40 | 1 | ||||
| auto[FaultKeyEcc] | 8 | 1 | T115 | 1 | T120 | 1 | T117 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |