Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	42	1			T18	1		T128	1		T26	1
auto[OpGenId]	9	1			T14	1		T235	2		T9	1
auto[OpGenSwOut]	21	1			T87	1		T236	2		T10	1
auto[OpGenHwOut]	21	1			T6	1		T7	1		T38	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1814	1			T14	1		T6	4		T11	180
auto[StInit]	75	1			T2	1		T6	1		T115	1
auto[StCreatorRootKey]	57	1			T17	1		T6	1		T38	1
auto[StOwnerIntKey]	53	1			T18	1		T128	1		T74	1
auto[StOwnerKey]	39	1			T7	1		T41	1		T132	1
auto[StDisabled]	443	1			T5	1		T14	1		T6	4
auto[StInvalid]	50	1			T35	1		T37	1		T51	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3525

1

T1

1

T2

2

T3

1

auto[1]

93

1

T14

1

T18

1

T6

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1808	1			T14	1		T6	4		T11	180
auto[StReset]	auto[1]	6	1			T134	1		T200	1		T237	1
auto[StInit]	auto[0]	41	1			T2	1		T6	1		T115	1
auto[StInit]	auto[1]	34	1			T27	1		T8	1		T198	1
auto[StCreatorRootKey]	auto[0]	39	1			T17	1		T39	1		T99	1
auto[StCreatorRootKey]	auto[1]	18	1			T6	1		T38	1		T64	1
auto[StOwnerIntKey]	auto[0]	37	1			T74	1		T85	1		T63	1
auto[StOwnerIntKey]	auto[1]	16	1			T18	1		T128	1		T236	2
auto[StOwnerKey]	auto[0]	30	1			T41	1		T132	1		T139	1
auto[StOwnerKey]	auto[1]	9	1			T7	1		T87	1		T198	1
auto[StDisabled]	auto[0]	433	1			T5	1		T6	4		T102	1
auto[StDisabled]	auto[1]	10	1			T14	1		T26	1		T223	1
auto[StInvalid]	auto[0]	50	1			T35	1		T37	1		T51	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[StDisabled]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T134	1		T200	1		T135	1
auto[StReset]	auto[OpGenSwOut]	1	1			T238	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	2	1			T237	1		T239	1		-	-
auto[StInit]	auto[OpAdvance]	16	1			T27	1		T240	1		T61	1
auto[StInit]	auto[OpGenId]	2	1			T235	1		T9	1		-	-
auto[StInit]	auto[OpGenSwOut]	8	1			T101	1		T134	1		T241	1
auto[StInit]	auto[OpGenHwOut]	8	1			T8	1		T198	1		T30	1
auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T64	1		T242	1		T243	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T244	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T10	1		T245	1		T246	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	3	1			T6	1		T38	1		T247	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T18	1		T128	1		T236	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T248	1		T249	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T236	1		T250	1		T150	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T10	1		T251	1		T252	1
auto[StOwnerKey]	auto[OpAdvance]	1	1			T198	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenId]	3	1			T235	1		T253	1		T254	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T87	1		T236	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	3	1			T7	1		T255	1		T256	1
auto[StDisabled]	auto[OpAdvance]	8	1			T26	1		T223	1		T257	1
auto[StDisabled]	auto[OpGenId]	1	1			T14	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	1	1			T258	1		-	-		-	-