Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4757

1

T1

4

T3

13

T4

10

auto[1]

575

1

T4

3

T15

2

T6

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4757

1

T1

4

T3

13

T4

10

auto[1]

575

1

T4

3

T15

2

T6

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4809

1

T1

4

T3

10

T4

13

auto[1]

523

1

T3

3

T14

1

T6

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4809

1

T1

4

T3

10

T4

13

auto[1]

523

1

T3

3

T14

1

T6

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	403	1			T1	1		T5	1		T14	3
auto[OpGenId]	1083	1			T1	1		T14	2		T35	1
auto[OpGenSwOut]	1210	1			T14	3		T15	4		T18	1
auto[OpGenHwOut]	2578	1			T1	2		T3	13		T4	13
auto[OpDisable]	58	1			T133	1		T127	1		T63	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	403	1			T1	1		T5	1		T14	3
auto[OpGenId]	1083	1			T1	1		T14	2		T35	1
auto[OpGenSwOut]	1210	1			T14	3		T15	4		T18	1
auto[OpGenHwOut]	2578	1			T1	2		T3	13		T4	13
auto[OpDisable]	58	1			T133	1		T127	1		T63	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4713

1

T1

2

T3

13

T4

13

auto[1]

619

1

T1

2

T14

1

T15

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4713

1

T1

2

T3

13

T4

13

auto[1]

619

1

T1

2

T14

1

T15

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5047

1

T1

4

T3

13

T4

13

auto[1]

285

1

T79

3

T80

4

T116

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1838	1			T1	1		T3	4		T4	4
auto[1]	721	1			T1	2		T3	1		T4	3
auto[2]	723	1			T1	1		T3	1		T4	1
auto[3]	655	1			T3	2		T4	3		T14	1
auto[4]	325	1			T3	2		T14	1		T35	1
auto[5]	340	1			T3	1		T14	1		T34	3
auto[6]	367	1			T3	1		T15	1		T35	1
auto[7]	363	1			T3	1		T4	2		T35	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1395	1			T3	5		T4	2		T14	2
clear_one[1]	721	1			T1	2		T3	1		T4	3
clear_one[2]	723	1			T1	1		T3	1		T4	1
clear_one[3]	655	1			T3	2		T4	3		T14	1
clear_none	1838	1			T1	1		T3	4		T4	4

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	998	1			T3	5		T4	5		T14	1
auto[StInit]	648	1			T3	1		T4	1		T5	1
auto[StCreatorRootKey]	583	1			T3	1		T4	1		T14	2
auto[StOwnerIntKey]	496	1			T1	1		T3	1		T4	1
auto[StOwnerKey]	497	1			T1	1		T3	1		T4	1
auto[StDisabled]	1835	1			T1	2		T3	4		T4	4
auto[StInvalid]	275	1			T35	6		T36	4		T37	6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	998	1			T3	5		T4	5		T14	1
auto[StInit]	648	1			T3	1		T4	1		T5	1
auto[StCreatorRootKey]	583	1			T3	1		T4	1		T14	2
auto[StOwnerIntKey]	496	1			T1	1		T3	1		T4	1
auto[StOwnerKey]	497	1			T1	1		T3	1		T4	1
auto[StDisabled]	1835	1			T1	2		T3	4		T4	4
auto[StInvalid]	275	1			T35	6		T36	4		T37	6

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T259	1		T260	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	151	1			T6	3		T80	1		T71	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	178	1			T15	1		T133	1		T24	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	265	1			T3	3		T4	3		T14	1
auto[0]	auto[StInit]	auto[OpAdvance]	59	1			T5	1		T18	1		T6	1
auto[0]	auto[StInit]	auto[OpGenId]	80	1			T6	1		T228	1		T216	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	93	1			T14	1		T218	1		T69	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	170	1			T34	1		T96	1		T227	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T79	1		T87	1		T261	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	47	1			T219	1		T214	1		T262	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	57	1			T98	1		T79	1		T151	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	74	1			T93	1		T263	1		T7	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T1	1		T104	1		T10	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	29	1			T91	1		T128	1		T8	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T129	1		T86	1		T142	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	55	1			T19	1		T153	1		T264	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T48	1		T64	1		T265	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	20	1			T91	1		T95	1		T79	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	29	1			T219	1		T151	1		T8	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T3	1		T227	1		T230	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	20	1			T6	2		T107	1		T89	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T263	1		T266	1		T151	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	82	1			T14	1		T79	1		T216	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T4	1		T6	2		T96	2
auto[0]	auto[StDisabled]	auto[OpDisable]	14	1			T86	1		T89	1		T144	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	9	1			T37	2		T267	1		T268	2
auto[0]	auto[StInvalid]	auto[OpGenId]	18	1			T37	1		T50	1		T269	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T35	1		T36	1		T50	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	27	1			T51	2		T222	1		T155	1
auto[1]	auto[StReset]	auto[OpGenId]	22	1			T24	1		T8	1		T107	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	21	1			T80	1		T232	1		T38	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	50	1			T4	1		T234	1		T270	2
auto[1]	auto[StInit]	auto[OpAdvance]	1	1			T223	1		-	-		-	-
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T64	1		T89	1		T200	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	22	1			T6	1		T7	1		T23	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T124	1		T152	1		T39	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T26	1		T48	1		T271	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T232	1		T221	1		T223	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T69	1		T31	1		T107	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T96	1		T272	1		T273	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T14	1		T221	1		T198	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T14	1		T8	1		T223	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T18	1		T116	1		T10	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T4	1		T70	1		T274	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T275	1		T200	1		T276	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T1	1		T217	1		T277	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T278	1		T199	1		T279	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T70	1		T72	1		T264	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	26	1			T24	1		T104	1		T48	1
auto[1]	auto[StDisabled]	auto[OpGenId]	58	1			T79	1		T69	1		T221	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T116	1		T262	1		T277	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T1	1		T3	1		T4	1
auto[1]	auto[StDisabled]	auto[OpDisable]	4	1			T127	1		T198	1		T236	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T280	1		T281	1		T282	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T283	1		T268	2		T284	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T36	1		T37	1		T222	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T65	1		T285	1		T286	1
auto[2]	auto[StReset]	auto[OpGenId]	14	1			T287	1		T236	1		T288	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T222	1		T127	1		T226	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	51	1			T3	1		T6	1		T96	1
auto[2]	auto[StInit]	auto[OpAdvance]	8	1			T288	1		T53	1		T54	1
auto[2]	auto[StInit]	auto[OpGenId]	15	1			T23	1		T289	1		T198	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	8	1			T236	2		T55	1		T125	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T66	1		T290	1		T29	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T14	1		T80	1		T137	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T291	1		T292	1		T293	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T15	1		T80	1		T24	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T4	1		T70	1		T72	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T262	1		T294	1		T295	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T69	1		T261	1		T294	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T296	1		T198	1		T200	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T231	1		T66	1		T63	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T297	1		T298	1		T299	2
auto[2]	auto[StOwnerKey]	auto[OpGenId]	16	1			T262	1		T106	1		T198	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	26	1			T15	1		T8	1		T223	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T231	1		T80	1		T152	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	17	1			T217	1		T8	1		T223	1
auto[2]	auto[StDisabled]	auto[OpGenId]	41	1			T300	1		T301	1		T223	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T91	1		T95	1		T151	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T1	1		T15	2		T96	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T134	1		T302	1		T303	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	13	1			T35	1		T222	1		T304	2
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T50	1		T305	1		T268	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T36	1		T51	2		T222	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T35	1		T71	1		T222	1
auto[3]	auto[StReset]	auto[OpGenId]	13	1			T25	1		T223	1		T306	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	22	1			T219	1		T222	1		T266	2
auto[3]	auto[StReset]	auto[OpGenHwOut]	40	1			T3	1		T4	1		T34	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T289	1		T307	1		T308	1
auto[3]	auto[StInit]	auto[OpGenId]	7	1			T14	1		T309	1		T310	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T22	1		T87	1		T311	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T4	1		T217	1		T270	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T18	1		T116	1		T104	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T25	1		T312	1		T10	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T128	1		T63	1		T8	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T227	1		T141	1		T313	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T219	1		T223	1		T309	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T218	1		T63	1		T87	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T10	1		T314	1		T315	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T102	1		T227	1		T233	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T223	1		T311	1		T235	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	18	1			T98	1		T223	1		T10	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T25	1		T266	1		T45	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T34	1		T272	1		T63	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	19	1			T80	1		T45	1		T156	1
auto[3]	auto[StDisabled]	auto[OpGenId]	57	1			T69	1		T214	1		T205	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T91	1		T80	1		T87	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	136	1			T3	1		T4	1		T34	1
auto[3]	auto[StDisabled]	auto[OpDisable]	18	1			T133	1		T130	1		T131	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	3	1			T285	1		T316	1		T317	1
auto[3]	auto[StInvalid]	auto[OpGenId]	7	1			T46	1		T318	1		T319	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T37	1		T320	1		T321	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T50	1		T304	1		T268	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T322	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T323	1		T10	1		T46	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	5	1			T288	1		T310	1		T324	2
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T34	1		T24	1		T7	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T105	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T325	1		T326	1		T202	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T21	1		T22	1		T23	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	11	1			T72	1		T21	1		T273	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T298	1		T327	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T104	2		T236	1		T328	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T102	1		T132	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T3	1		T218	1		T104	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T311	1		T329	1		T246	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T323	1		T223	1		T330	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T146	1		T331	1		T332	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T133	1		T130	1		T194	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T214	1		T253	1		T333	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T89	1		T334	1		T335	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T326	1		T202	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T102	1		T234	1		T313	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T14	1		T52	1		T322	1
auto[4]	auto[StDisabled]	auto[OpGenId]	23	1			T6	1		T198	1		T336	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T19	1		T311	1		T337	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T3	1		T227	1		T152	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T63	1		T338	1		T250	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T71	1		T286	1		T339	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T35	1		T340	1		T341	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T62	1		T339	1		T342	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T340	1		T319	1		T321	1
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T80	1		T127	1		T308	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	13	1			T25	1		T219	1		T222	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	17	1			T34	1		T283	1		T311	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T132	1		T326	1		T343	2
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T181	1		T344	1		T326	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	9	1			T6	1		T345	1		T54	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	6	1			T346	1		T347	1		T348	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T349	1		T350	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T89	1		T351	1		T235	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T14	1		T311	1		T352	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T34	1		T231	1		T233	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T156	1		T64	1		T202	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T98	1		T10	1		T353	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T226	1		T49	1		T354	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T3	1		T34	1		T355	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T356	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T357	1		T310	1		T254	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T86	1		T358	1		T310	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T153	1		T274	1		T359	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	11	1			T91	1		T151	1		T8	1
auto[5]	auto[StDisabled]	auto[OpGenId]	31	1			T6	2		T95	1		T216	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T219	1		T266	1		T48	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T6	1		T95	1		T231	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T182	1		T360	1		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T155	1		T283	1		T342	1
auto[5]	auto[StInvalid]	auto[OpGenId]	2	1			T47	1		T361	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T50	1		T62	1		T362	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T155	1		T363	1		T364	1
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T8	1		T223	1		T365	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	3	1			T366	1		T247	1		T360	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T219	1		T264	1		T193	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T52	1		T367	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T8	1		T32	1		T368	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T15	1		T54	1		T369	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	15	1			T3	1		T151	1		T370	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T253	1		T371	1		T372	2
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T296	1		T223	1		T201	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T373	1		T200	1		T374	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T230	1		T66	1		T234	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T198	1		T202	1		T360	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T131	1		T375	1		T376	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T216	1		T236	1		T377	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T96	1		T72	1		T152	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T378	1		T379	1		T350	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	11	1			T8	1		T223	1		T322	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T236	1		T311	1		T380	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T96	1		T381	1		T382	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T79	1		T218	1		T383	2
auto[6]	auto[StDisabled]	auto[OpGenId]	33	1			T154	1		T130	1		T384	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T79	1		T19	1		T312	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T34	1		T233	1		T66	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T8	1		T198	1		T366	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T35	1		T385	1		T364	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T37	1		T320	2		T386	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T222	1		T283	1		T284	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T222	1		T46	1		T363	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T48	1		T31	1		T387	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	7	1			T232	1		T363	1		T388	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	27	1			T34	1		T66	1		T234	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T389	1		T390	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T8	1		T223	1		T391	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T8	1		T223	1		T392	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	5	1			T80	2		T393	1		T394	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T395	1		-	-		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T396	1		T397	1		T398	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T64	1		T33	1		T254	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T264	1		T290	1		T370	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T389	2		T56	1		T399	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T205	1		T287	1		T365	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T26	1		T90	1		T344	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T230	1		T272	1		T400	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T401	1		T402	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	12	1			T105	1		T198	1		T10	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T389	2		T403	1		T404	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T4	1		T216	1		T233	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T218	1		T10	1		T405	1
auto[7]	auto[StDisabled]	auto[OpGenId]	31	1			T116	1		T210	1		T406	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T8	2		T407	1		T223	2
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T3	1		T4	1		T227	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T125	1		T408	1		T149	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T46	1		T347	1		T409	1
auto[7]	auto[StInvalid]	auto[OpGenId]	10	1			T50	1		T283	1		T340	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T340	1		T286	1		T410	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T35	1		T36	1		T385	1