Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1395

1

T3

5

T4

2

T14

2

clear_one[1]

auto[0]

auto[0]

auto[0]

426

1

T1

1

T4

3

T14

1

clear_one[1]

auto[0]

auto[0]

auto[1]

147

1

T1

1

T18

1

T34

2

clear_one[1]

auto[0]

auto[1]

auto[0]

111

1

T3

1

T96

2

T66

1

clear_one[1]

auto[0]

auto[1]

auto[1]

37

1

T14

1

T79

1

T24

2

clear_one[2]

auto[0]

auto[0]

auto[0]

390

1

T3

1

T14

1

T15

2

clear_one[2]

auto[0]

auto[0]

auto[1]

136

1

T1

1

T231

3

T70

1

clear_one[2]

auto[1]

auto[0]

auto[0]

129

1

T4

1

T15

1

T227

1

clear_one[2]

auto[1]

auto[0]

auto[1]

68

1

T15

1

T80

1

T104

1

clear_one[3]

auto[0]

auto[0]

auto[0]

375

1

T3

1

T4

2

T14

1

clear_one[3]

auto[0]

auto[1]

auto[0]

120

1

T3

1

T98

1

T66

2

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T4

1

T25

1

T227

3

clear_one[3]

auto[1]

auto[1]

auto[0]

33

1

T91

1

T232

1

T45

2

clear_none

auto[0]

auto[0]

auto[0]

1322

1

T1

1

T3

3

T4

3

clear_none

auto[0]

auto[0]

auto[1]

127

1

T93

1

T19

1

T230

4

clear_none

auto[0]

auto[1]

auto[0]

137

1

T3

1

T6

1

T96

2

clear_none

auto[0]

auto[1]

auto[1]

34

1

T6

1

T79

2

T224

1

clear_none

auto[1]

auto[0]

auto[0]

118

1

T4

1

T25

1

T227

1

clear_none

auto[1]

auto[0]

auto[1]

49

1

T6

1

T91

2

T104

3

clear_none

auto[1]

auto[1]

auto[0]

30

1

T6

1

T263

1

T45

1

clear_none

auto[1]

auto[1]

auto[1]

21

1

T224

1

T89

2

T183

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1321	1			T3	5		T4	2		T14	2
clear_all	auto[1]	74	1			T79	1		T80	1		T116	1
clear_one[1]	auto[0]	683	1			T1	2		T3	1		T4	3
clear_one[1]	auto[1]	38	1			T116	1		T107	3		T411	2
clear_one[2]	auto[0]	658	1			T1	1		T3	1		T4	1
clear_one[2]	auto[1]	65	1			T80	2		T412	1		T294	4
clear_one[3]	auto[0]	629	1			T3	2		T4	3		T14	1
clear_one[3]	auto[1]	26	1			T80	1		T104	2		T413	4
clear_none	auto[0]	1756	1			T1	1		T3	4		T4	4
clear_none	auto[1]	82	1			T79	2		T104	5		T106	1