Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11208

1

T1

12

T3

20

T4

18

auto[Attestation]

7734

1

T1

9

T2

1

T3

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2737	1			T1	3		T14	5		T15	4
auto[Aes]	3485	1			T1	4		T4	22		T14	7
auto[Kmac]	3482	1			T1	4		T3	22		T14	3
auto[Otbn]	3390	1			T1	3		T2	1		T14	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7730	1			T1	8		T2	1		T3	8
auto[OpGenId]	5848	1			T1	7		T5	3		T14	9
auto[OpGenSwOut]	6181	1			T1	8		T2	1		T14	11
auto[OpGenHwOut]	6913	1			T1	6		T3	22		T4	22
auto[OpDisable]	118	1			T98	1		T133	1		T124	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10674

1

T1

7

T2

1

T3

8

auto[OpDoneFail]

16116

1

T1

22

T2

1

T3

22

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6541	1			T1	5		T2	1		T3	15
auto[StInit]	3744	1			T1	3		T2	1		T3	2
auto[StCreatorRootKey]	3182	1			T1	2		T3	2		T4	2
auto[StOwnerIntKey]	2799	1			T1	1		T3	2		T4	2
auto[StOwnerKey]	2519	1			T1	2		T3	2		T4	2
auto[StDisabled]	8005	1			T1	16		T3	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	355	1			T1	1		T14	2		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	96	1			T6	1		T93	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	88	1			T6	1		T93	1		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T6	1		T41	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T25	1		T63	1		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	234	1			T19	2		T133	1		T80	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	366	1			T1	1		T6	3		T92	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	115	1			T15	1		T97	1		T21	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	89	1			T15	1		T19	1		T215	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	54	1			T6	1		T216	1		T217	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	76	1			T79	1		T24	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	230	1			T1	1		T14	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	373	1			T1	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	124	1			T19	1		T74	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T79	1		T102	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T6	1		T218	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	72	1			T14	1		T25	1		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	201	1			T1	1		T6	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	329	1			T6	3		T79	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	100	1			T6	2		T21	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T25	1		T220	1		T80	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T18	1		T6	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T219	1		T74	1		T221	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	233	1			T15	1		T91	1		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	86	1			T74	1		T222	4		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T91	1		T67	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T218	1		T69	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T6	2		T116	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T14	1		T15	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	225	1			T1	1		T6	2		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	82	1			T74	1		T222	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	95	1			T98	1		T25	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	87	1			T14	1		T133	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	83	1			T91	1		T95	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	67	1			T19	1		T116	1		T215	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	253	1			T1	2		T14	2		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	86	1			T74	1		T87	4		T223	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	97	1			T93	2		T69	1		T219	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T25	1		T63	1		T224	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T225	1		T151	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	58	1			T79	1		T67	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	218	1			T91	2		T98	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T222	1		T63	1		T87	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	125	1			T2	1		T14	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T6	1		T95	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T6	1		T214	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	74	1			T14	1		T45	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	207	1			T91	1		T92	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	279	1			T14	1		T15	1		T6	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	87	1			T91	1		T218	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T91	1		T25	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T79	1		T19	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T216	1		T102	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	171	1			T1	1		T6	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	469	1			T4	14		T14	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	96	1			T17	1		T19	2		T227	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	125	1			T91	1		T93	1		T227	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T4	1		T14	1		T228	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	92	1			T4	1		T6	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	299	1			T4	2		T15	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	525	1			T3	14		T36	2		T96	11
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T3	1		T91	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T153	1		T45	1		T229	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T3	1		T79	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T3	1		T79	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	284	1			T3	3		T6	2		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	410	1			T1	1		T34	10		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T34	1		T6	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T93	1		T216	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T230	1		T133	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T6	1		T19	1		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	306	1			T1	2		T14	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	61	1			T222	1		T63	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	85	1			T133	1		T115	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	71	1			T17	1		T98	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T228	1		T102	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T6	1		T102	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	161	1			T14	1		T25	2		T232	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	51	1			T222	1		T8	4		T87	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	112	1			T4	1		T102	1		T233	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	101	1			T4	1		T6	1		T218	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	100	1			T227	1		T233	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T218	1		T80	1		T233	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	278	1			T4	2		T14	1		T227	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	35	1			T222	1		T8	4		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	124	1			T6	1		T75	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T3	1		T6	1		T93	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T14	1		T96	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	74	1			T96	1		T98	1		T215	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	280	1			T1	2		T3	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T8	2		T89	1		T223	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	135	1			T91	1		T19	1		T231	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	112	1			T34	1		T230	1		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T14	1		T18	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	85	1			T34	1		T6	3		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	281	1			T15	1		T34	3		T231	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	210	1			T6	2		T93	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	693	1			T1	1		T14	2		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	195	1			T15	1		T6	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	735	1			T1	2		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	218	1			T14	1		T6	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	716	1			T1	2		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T18	1		T6	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	678	1			T15	1		T6	5		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T14	1		T15	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	414	1			T1	1		T6	2		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	213	1			T14	1		T91	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	454	1			T1	2		T14	2		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	214	1			T79	1		T25	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	414	1			T91	2		T93	2		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T14	1		T6	2		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	423	1			T2	1		T14	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	170	1			T91	1		T79	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	559	1			T1	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	281	1			T4	2		T6	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	882	1			T4	16		T14	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	263	1			T3	2		T79	2		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	939	1			T3	18		T36	2		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T6	1		T93	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	829	1			T1	3		T14	1		T34	12
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T17	1		T6	1		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	326	1			T14	1		T25	2		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	264	1			T4	1		T6	1		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	461	1			T4	3		T14	1		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	266	1			T3	1		T14	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	452	1			T1	2		T3	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	287	1			T14	1		T18	1		T34	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	498	1			T15	1		T34	3		T91	1