Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32792

1

T1

33

T2

3

T3

35

auto[1]

284

1

T80

9

T116

3

T104

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32799	1			T1	33		T2	3		T3	35
auto[134217728:268435455]	12	1			T80	1		T105	1		T389	1
auto[268435456:402653183]	6	1			T389	1		T383	1		T298	1
auto[402653184:536870911]	8	1			T412	1		T294	1		T444	1
auto[536870912:671088639]	6	1			T389	1		T383	1		T425	1
auto[671088640:805306367]	5	1			T411	1		T383	1		T297	1
auto[805306368:939524095]	10	1			T412	1		T294	1		T383	1
auto[939524096:1073741823]	10	1			T116	1		T104	1		T412	2
auto[1073741824:1207959551]	10	1			T104	1		T107	2		T383	1
auto[1207959552:1342177279]	8	1			T412	1		T295	1		T445	1
auto[1342177280:1476395007]	9	1			T104	2		T107	1		T389	1
auto[1476395008:1610612735]	7	1			T107	1		T412	1		T294	1
auto[1610612736:1744830463]	10	1			T295	1		T413	1		T383	1
auto[1744830464:1879048191]	8	1			T80	2		T294	1		T383	1
auto[1879048192:2013265919]	11	1			T105	1		T107	1		T413	1
auto[2013265920:2147483647]	4	1			T106	1		T445	1		T297	1
auto[2147483648:2281701375]	8	1			T104	1		T107	1		T411	1
auto[2281701376:2415919103]	7	1			T412	1		T295	1		T383	2
auto[2415919104:2550136831]	6	1			T411	2		T294	1		T383	1
auto[2550136832:2684354559]	13	1			T107	1		T389	1		T295	1
auto[2684354560:2818572287]	13	1			T116	1		T105	1		T107	1
auto[2818572288:2952790015]	9	1			T107	1		T413	1		T444	2
auto[2952790016:3087007743]	6	1			T389	1		T413	1		T260	1
auto[3087007744:3221225471]	12	1			T116	1		T106	1		T294	1
auto[3221225472:3355443199]	8	1			T80	1		T259	1		T298	1
auto[3355443200:3489660927]	12	1			T411	1		T322	2		T412	1
auto[3489660928:3623878655]	6	1			T80	1		T389	1		T260	1
auto[3623878656:3758096383]	11	1			T80	2		T294	1		T446	1
auto[3758096384:3892314111]	12	1			T322	1		T413	1		T383	1
auto[3892314112:4026531839]	10	1			T80	1		T297	2		T298	1
auto[4026531840:4160749567]	11	1			T105	1		T107	1		T412	1
auto[4160749568:4294967295]	9	1			T80	1		T411	1		T294	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32792	1			T1	33		T2	3		T3	35
auto[0:134217727]	auto[1]	7	1			T413	1		T383	2		T329	1
auto[134217728:268435455]	auto[1]	12	1			T80	1		T105	1		T389	1
auto[268435456:402653183]	auto[1]	6	1			T389	1		T383	1		T298	1
auto[402653184:536870911]	auto[1]	8	1			T412	1		T294	1		T444	1
auto[536870912:671088639]	auto[1]	6	1			T389	1		T383	1		T425	1
auto[671088640:805306367]	auto[1]	5	1			T411	1		T383	1		T297	1
auto[805306368:939524095]	auto[1]	10	1			T412	1		T294	1		T383	1
auto[939524096:1073741823]	auto[1]	10	1			T116	1		T104	1		T412	2
auto[1073741824:1207959551]	auto[1]	10	1			T104	1		T107	2		T383	1
auto[1207959552:1342177279]	auto[1]	8	1			T412	1		T295	1		T445	1
auto[1342177280:1476395007]	auto[1]	9	1			T104	2		T107	1		T389	1
auto[1476395008:1610612735]	auto[1]	7	1			T107	1		T412	1		T294	1
auto[1610612736:1744830463]	auto[1]	10	1			T295	1		T413	1		T383	1
auto[1744830464:1879048191]	auto[1]	8	1			T80	2		T294	1		T383	1
auto[1879048192:2013265919]	auto[1]	11	1			T105	1		T107	1		T413	1
auto[2013265920:2147483647]	auto[1]	4	1			T106	1		T445	1		T297	1
auto[2147483648:2281701375]	auto[1]	8	1			T104	1		T107	1		T411	1
auto[2281701376:2415919103]	auto[1]	7	1			T412	1		T295	1		T383	2
auto[2415919104:2550136831]	auto[1]	6	1			T411	2		T294	1		T383	1
auto[2550136832:2684354559]	auto[1]	13	1			T107	1		T389	1		T295	1
auto[2684354560:2818572287]	auto[1]	13	1			T116	1		T105	1		T107	1
auto[2818572288:2952790015]	auto[1]	9	1			T107	1		T413	1		T444	2
auto[2952790016:3087007743]	auto[1]	6	1			T389	1		T413	1		T260	1
auto[3087007744:3221225471]	auto[1]	12	1			T116	1		T106	1		T294	1
auto[3221225472:3355443199]	auto[1]	8	1			T80	1		T259	1		T298	1
auto[3355443200:3489660927]	auto[1]	12	1			T411	1		T322	2		T412	1
auto[3489660928:3623878655]	auto[1]	6	1			T80	1		T389	1		T260	1
auto[3623878656:3758096383]	auto[1]	11	1			T80	2		T294	1		T446	1
auto[3758096384:3892314111]	auto[1]	12	1			T322	1		T413	1		T383	1
auto[3892314112:4026531839]	auto[1]	10	1			T80	1		T297	2		T298	1
auto[4026531840:4160749567]	auto[1]	11	1			T105	1		T107	1		T412	1
auto[4160749568:4294967295]	auto[1]	9	1			T80	1		T411	1		T294	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1581

1

T1

1

T5

3

T14

8

auto[1]

1772

1

T1

2

T5

2

T14

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T14	1		T25	1		T7	1
auto[134217728:268435455]	114	1			T5	1		T6	1		T25	1
auto[268435456:402653183]	102	1			T18	1		T79	1		T102	1
auto[402653184:536870911]	114	1			T5	1		T14	1		T6	1
auto[536870912:671088639]	99	1			T6	2		T37	1		T71	1
auto[671088640:805306367]	113	1			T14	1		T35	1		T36	1
auto[805306368:939524095]	93	1			T6	1		T25	1		T80	1
auto[939524096:1073741823]	104	1			T14	1		T19	1		T133	1
auto[1073741824:1207959551]	90	1			T1	1		T6	1		T19	1
auto[1207959552:1342177279]	89	1			T91	1		T93	1		T80	1
auto[1342177280:1476395007]	106	1			T6	1		T219	1		T23	1
auto[1476395008:1610612735]	108	1			T6	2		T102	1		T24	1
auto[1610612736:1744830463]	98	1			T25	1		T80	1		T51	1
auto[1744830464:1879048191]	93	1			T14	1		T79	1		T19	1
auto[1879048192:2013265919]	95	1			T19	1		T102	1		T80	1
auto[2013265920:2147483647]	115	1			T14	1		T19	1		T220	1
auto[2147483648:2281701375]	85	1			T1	1		T6	1		T80	1
auto[2281701376:2415919103]	112	1			T14	2		T18	1		T79	1
auto[2415919104:2550136831]	109	1			T6	1		T91	1		T25	1
auto[2550136832:2684354559]	110	1			T6	2		T219	1		T221	1
auto[2684354560:2818572287]	104	1			T228	1		T50	1		T124	1
auto[2818572288:2952790015]	110	1			T14	3		T24	1		T116	1
auto[2952790016:3087007743]	113	1			T18	1		T35	1		T218	1
auto[3087007744:3221225471]	110	1			T6	1		T79	1		T19	1
auto[3221225472:3355443199]	103	1			T14	1		T6	3		T50	1
auto[3355443200:3489660927]	109	1			T5	1		T6	1		T51	1
auto[3489660928:3623878655]	111	1			T6	1		T80	3		T71	1
auto[3623878656:3758096383]	99	1			T36	1		T228	1		T115	1
auto[3758096384:3892314111]	102	1			T6	2		T98	1		T37	1
auto[3892314112:4026531839]	112	1			T5	1		T91	1		T79	1
auto[4026531840:4160749567]	116	1			T5	1		T18	1		T36	1
auto[4160749568:4294967295]	120	1			T1	1		T14	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T25	1		T7	1		T141	1
auto[0:134217727]	auto[1]	46	1			T14	1		T116	2		T126	1
auto[134217728:268435455]	auto[0]	63	1			T5	1		T6	1		T25	1
auto[134217728:268435455]	auto[1]	51	1			T128	1		T263	1		T116	1
auto[268435456:402653183]	auto[0]	48	1			T50	1		T219	1		T38	1
auto[268435456:402653183]	auto[1]	54	1			T18	1		T79	1		T102	1
auto[402653184:536870911]	auto[0]	59	1			T14	1		T6	1		T25	1
auto[402653184:536870911]	auto[1]	55	1			T5	1		T132	1		T262	1
auto[536870912:671088639]	auto[0]	51	1			T6	1		T37	1		T71	1
auto[536870912:671088639]	auto[1]	48	1			T6	1		T45	1		T300	1
auto[671088640:805306367]	auto[0]	48	1			T14	1		T6	1		T37	1
auto[671088640:805306367]	auto[1]	65	1			T35	1		T36	1		T6	1
auto[805306368:939524095]	auto[0]	40	1			T155	1		T312	1		T193	1
auto[805306368:939524095]	auto[1]	53	1			T6	1		T25	1		T80	1
auto[939524096:1073741823]	auto[0]	43	1			T14	1		T24	1		T263	1
auto[939524096:1073741823]	auto[1]	61	1			T19	1		T133	1		T214	1
auto[1073741824:1207959551]	auto[0]	36	1			T19	1		T222	1		T63	1
auto[1073741824:1207959551]	auto[1]	54	1			T1	1		T6	1		T116	1
auto[1207959552:1342177279]	auto[0]	37	1			T93	1		T223	1		T288	1
auto[1207959552:1342177279]	auto[1]	52	1			T91	1		T80	1		T217	1
auto[1342177280:1476395007]	auto[0]	44	1			T6	1		T219	1		T406	1
auto[1342177280:1476395007]	auto[1]	62	1			T23	1		T210	1		T8	1
auto[1476395008:1610612735]	auto[0]	49	1			T24	1		T136	1		T8	1
auto[1476395008:1610612735]	auto[1]	59	1			T6	2		T102	1		T221	1
auto[1610612736:1744830463]	auto[0]	45	1			T25	1		T51	1		T63	1
auto[1610612736:1744830463]	auto[1]	53	1			T80	1		T224	1		T65	1
auto[1744830464:1879048191]	auto[0]	44	1			T14	1		T142	1		T349	1
auto[1744830464:1879048191]	auto[1]	49	1			T79	1		T19	1		T50	1
auto[1879048192:2013265919]	auto[0]	47	1			T24	1		T21	1		T222	1
auto[1879048192:2013265919]	auto[1]	48	1			T19	1		T102	1		T80	1
auto[2013265920:2147483647]	auto[0]	57	1			T14	1		T19	1		T48	1
auto[2013265920:2147483647]	auto[1]	58	1			T220	1		T26	1		T214	1
auto[2147483648:2281701375]	auto[0]	47	1			T6	1		T80	1		T71	1
auto[2147483648:2281701375]	auto[1]	38	1			T1	1		T49	1		T131	1
auto[2281701376:2415919103]	auto[0]	47	1			T8	1		T269	1		T87	1
auto[2281701376:2415919103]	auto[1]	65	1			T14	2		T18	1		T79	1
auto[2415919104:2550136831]	auto[0]	52	1			T25	1		T263	1		T104	1
auto[2415919104:2550136831]	auto[1]	57	1			T6	1		T91	1		T220	1
auto[2550136832:2684354559]	auto[0]	55	1			T6	1		T219	1		T38	1
auto[2550136832:2684354559]	auto[1]	55	1			T6	1		T221	1		T283	1
auto[2684354560:2818572287]	auto[0]	45	1			T228	1		T124	1		T7	1
auto[2684354560:2818572287]	auto[1]	59	1			T50	1		T63	1		T48	1
auto[2818572288:2952790015]	auto[0]	51	1			T14	2		T24	1		T136	2
auto[2818572288:2952790015]	auto[1]	59	1			T14	1		T116	1		T221	1
auto[2952790016:3087007743]	auto[0]	55	1			T218	1		T219	1		T64	1
auto[2952790016:3087007743]	auto[1]	58	1			T18	1		T35	1		T128	1
auto[3087007744:3221225471]	auto[0]	47	1			T6	1		T222	1		T430	1
auto[3087007744:3221225471]	auto[1]	63	1			T79	1		T19	1		T127	1
auto[3221225472:3355443199]	auto[0]	53	1			T6	2		T71	1		T22	1
auto[3221225472:3355443199]	auto[1]	50	1			T14	1		T6	1		T50	1
auto[3355443200:3489660927]	auto[0]	47	1			T5	1		T24	1		T155	1
auto[3355443200:3489660927]	auto[1]	62	1			T6	1		T51	1		T104	1
auto[3489660928:3623878655]	auto[0]	49	1			T80	1		T71	1		T222	2
auto[3489660928:3623878655]	auto[1]	62	1			T6	1		T80	2		T21	1
auto[3623878656:3758096383]	auto[0]	55	1			T228	1		T73	1		T217	1
auto[3623878656:3758096383]	auto[1]	44	1			T36	1		T115	1		T24	1
auto[3758096384:3892314111]	auto[0]	37	1			T71	1		T151	1		T45	1
auto[3758096384:3892314111]	auto[1]	65	1			T6	2		T98	1		T37	1
auto[3892314112:4026531839]	auto[0]	56	1			T115	1		T24	1		T217	1
auto[3892314112:4026531839]	auto[1]	56	1			T5	1		T91	1		T79	1
auto[4026531840:4160749567]	auto[0]	61	1			T5	1		T124	1		T22	1
auto[4026531840:4160749567]	auto[1]	55	1			T18	1		T36	1		T74	1
auto[4160749568:4294967295]	auto[0]	64	1			T1	1		T14	1		T6	1
auto[4160749568:4294967295]	auto[1]	56	1			T128	1		T124	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1563

1

T5

3

T14

5

T18

1

auto[1]

1790

1

T1

3

T5

2

T14

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T80	1		T50	1		T38	1
auto[134217728:268435455]	114	1			T36	1		T6	1		T79	1
auto[268435456:402653183]	100	1			T263	1		T7	1		T38	1
auto[402653184:536870911]	109	1			T1	1		T6	1		T124	1
auto[536870912:671088639]	102	1			T50	1		T24	1		T219	1
auto[671088640:805306367]	110	1			T6	1		T228	1		T102	1
auto[805306368:939524095]	100	1			T5	1		T14	1		T6	1
auto[939524096:1073741823]	108	1			T24	1		T23	1		T224	1
auto[1073741824:1207959551]	110	1			T14	1		T6	1		T218	1
auto[1207959552:1342177279]	112	1			T5	2		T36	1		T93	1
auto[1342177280:1476395007]	96	1			T14	2		T18	1		T37	1
auto[1476395008:1610612735]	107	1			T98	1		T25	2		T80	1
auto[1610612736:1744830463]	93	1			T6	2		T19	1		T25	1
auto[1744830464:1879048191]	101	1			T35	1		T24	1		T141	1
auto[1879048192:2013265919]	123	1			T14	1		T79	1		T25	1
auto[2013265920:2147483647]	113	1			T5	1		T14	1		T36	1
auto[2147483648:2281701375]	101	1			T6	2		T128	1		T73	1
auto[2281701376:2415919103]	135	1			T1	1		T102	1		T80	1
auto[2415919104:2550136831]	103	1			T14	2		T6	2		T80	1
auto[2550136832:2684354559]	91	1			T14	1		T6	1		T151	1
auto[2684354560:2818572287]	120	1			T1	1		T14	1		T6	1
auto[2818572288:2952790015]	98	1			T18	1		T35	1		T6	1
auto[2952790016:3087007743]	95	1			T14	1		T222	1		T63	1
auto[3087007744:3221225471]	105	1			T6	1		T24	1		T71	1
auto[3221225472:3355443199]	108	1			T14	1		T6	1		T133	1
auto[3355443200:3489660927]	107	1			T18	1		T6	1		T25	1
auto[3489660928:3623878655]	99	1			T14	1		T91	1		T219	1
auto[3623878656:3758096383]	99	1			T5	1		T228	1		T79	1
auto[3758096384:3892314111]	103	1			T6	4		T25	1		T37	1
auto[3892314112:4026531839]	102	1			T6	1		T91	1		T79	1
auto[4026531840:4160749567]	95	1			T18	1		T102	1		T128	1
auto[4160749568:4294967295]	108	1			T6	1		T79	1		T19	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T38	1		T222	1		T217	1
auto[0:134217727]	auto[1]	48	1			T80	1		T50	1		T104	1
auto[134217728:268435455]	auto[0]	52	1			T263	1		T155	2		T312	1
auto[134217728:268435455]	auto[1]	62	1			T36	1		T6	1		T79	1
auto[268435456:402653183]	auto[0]	49	1			T263	1		T7	1		T38	1
auto[268435456:402653183]	auto[1]	51	1			T217	1		T224	1		T130	1
auto[402653184:536870911]	auto[0]	57	1			T124	1		T74	1		T193	1
auto[402653184:536870911]	auto[1]	52	1			T1	1		T6	1		T217	1
auto[536870912:671088639]	auto[0]	40	1			T24	1		T219	1		T21	1
auto[536870912:671088639]	auto[1]	62	1			T50	1		T215	1		T151	1
auto[671088640:805306367]	auto[0]	54	1			T6	1		T228	1		T80	1
auto[671088640:805306367]	auto[1]	56	1			T102	1		T133	1		T80	1
auto[805306368:939524095]	auto[0]	37	1			T5	1		T312	1		T142	1
auto[805306368:939524095]	auto[1]	63	1			T14	1		T6	1		T19	1
auto[939524096:1073741823]	auto[0]	48	1			T198	1		T236	1		T288	1
auto[939524096:1073741823]	auto[1]	60	1			T24	1		T23	1		T224	1
auto[1073741824:1207959551]	auto[0]	52	1			T6	1		T115	1		T24	1
auto[1073741824:1207959551]	auto[1]	58	1			T14	1		T218	1		T50	1
auto[1207959552:1342177279]	auto[0]	44	1			T5	1		T93	1		T71	1
auto[1207959552:1342177279]	auto[1]	68	1			T5	1		T36	1		T126	1
auto[1342177280:1476395007]	auto[0]	48	1			T14	1		T37	1		T50	1
auto[1342177280:1476395007]	auto[1]	48	1			T14	1		T18	1		T214	1
auto[1476395008:1610612735]	auto[0]	54	1			T25	2		T263	1		T21	1
auto[1476395008:1610612735]	auto[1]	53	1			T98	1		T80	1		T312	1
auto[1610612736:1744830463]	auto[0]	46	1			T6	1		T19	1		T24	1
auto[1610612736:1744830463]	auto[1]	47	1			T6	1		T25	1		T80	1
auto[1744830464:1879048191]	auto[0]	48	1			T222	1		T48	1		T132	1
auto[1744830464:1879048191]	auto[1]	53	1			T35	1		T24	1		T141	1
auto[1879048192:2013265919]	auto[0]	66	1			T25	1		T7	1		T136	2
auto[1879048192:2013265919]	auto[1]	57	1			T14	1		T79	1		T23	1
auto[2013265920:2147483647]	auto[0]	57	1			T14	1		T6	1		T63	1
auto[2013265920:2147483647]	auto[1]	56	1			T5	1		T36	1		T19	1
auto[2147483648:2281701375]	auto[0]	43	1			T6	2		T73	1		T323	1
auto[2147483648:2281701375]	auto[1]	58	1			T128	1		T45	1		T224	1
auto[2281701376:2415919103]	auto[0]	69	1			T80	1		T51	1		T219	1
auto[2281701376:2415919103]	auto[1]	66	1			T1	1		T102	1		T210	1
auto[2415919104:2550136831]	auto[0]	44	1			T80	1		T71	1		T132	1
auto[2415919104:2550136831]	auto[1]	59	1			T14	2		T6	2		T50	1
auto[2550136832:2684354559]	auto[0]	38	1			T14	1		T6	1		T151	1
auto[2550136832:2684354559]	auto[1]	53	1			T156	1		T300	1		T289	1
auto[2684354560:2818572287]	auto[0]	60	1			T6	1		T37	1		T115	1
auto[2684354560:2818572287]	auto[1]	60	1			T1	1		T14	1		T91	1
auto[2818572288:2952790015]	auto[0]	48	1			T18	1		T19	1		T124	1
auto[2818572288:2952790015]	auto[1]	50	1			T35	1		T6	1		T91	1
auto[2952790016:3087007743]	auto[0]	47	1			T14	1		T222	1		T63	1
auto[2952790016:3087007743]	auto[1]	48	1			T8	1		T106	1		T52	1
auto[3087007744:3221225471]	auto[0]	47	1			T6	1		T71	1		T217	1
auto[3087007744:3221225471]	auto[1]	58	1			T24	1		T28	1		T23	1
auto[3221225472:3355443199]	auto[0]	54	1			T14	1		T127	1		T48	1
auto[3221225472:3355443199]	auto[1]	54	1			T6	1		T133	1		T220	1
auto[3355443200:3489660927]	auto[0]	50	1			T6	1		T25	1		T219	1
auto[3355443200:3489660927]	auto[1]	57	1			T18	1		T221	1		T305	1
auto[3489660928:3623878655]	auto[0]	45	1			T104	1		T229	1		T210	1
auto[3489660928:3623878655]	auto[1]	54	1			T14	1		T91	1		T219	1
auto[3623878656:3758096383]	auto[0]	49	1			T5	1		T228	1		T218	1
auto[3623878656:3758096383]	auto[1]	50	1			T79	1		T80	1		T128	1
auto[3758096384:3892314111]	auto[0]	46	1			T6	1		T25	1		T71	1
auto[3758096384:3892314111]	auto[1]	57	1			T6	3		T37	1		T51	1
auto[3892314112:4026531839]	auto[0]	46	1			T71	1		T262	1		T283	1
auto[3892314112:4026531839]	auto[1]	56	1			T6	1		T91	1		T79	1
auto[4026531840:4160749567]	auto[0]	44	1			T141	1		T217	1		T64	1
auto[4026531840:4160749567]	auto[1]	51	1			T18	1		T102	1		T128	1
auto[4160749568:4294967295]	auto[0]	43	1			T6	1		T26	1		T38	1
auto[4160749568:4294967295]	auto[1]	65	1			T79	1		T19	1		T124	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1581

1

T5

2

T14

5

T18

1

auto[1]

1772

1

T1

3

T5

3

T14

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T1	1		T50	2		T24	1
auto[134217728:268435455]	114	1			T6	1		T102	1		T133	1
auto[268435456:402653183]	107	1			T1	1		T14	1		T35	1
auto[402653184:536870911]	115	1			T79	1		T25	1		T128	1
auto[536870912:671088639]	101	1			T5	1		T6	1		T19	2
auto[671088640:805306367]	122	1			T263	1		T141	1		T151	1
auto[805306368:939524095]	92	1			T6	1		T220	1		T24	1
auto[939524096:1073741823]	92	1			T14	1		T6	2		T219	1
auto[1073741824:1207959551]	102	1			T91	1		T80	1		T115	1
auto[1207959552:1342177279]	102	1			T14	2		T133	1		T50	1
auto[1342177280:1476395007]	114	1			T5	1		T6	1		T25	1
auto[1476395008:1610612735]	101	1			T6	1		T80	1		T26	1
auto[1610612736:1744830463]	108	1			T6	3		T228	1		T19	1
auto[1744830464:1879048191]	111	1			T6	1		T25	1		T80	1
auto[1879048192:2013265919]	102	1			T5	1		T14	1		T18	1
auto[2013265920:2147483647]	98	1			T6	1		T93	1		T128	1
auto[2147483648:2281701375]	112	1			T36	1		T79	2		T102	1
auto[2281701376:2415919103]	106	1			T6	2		T37	1		T128	1
auto[2415919104:2550136831]	96	1			T14	1		T18	1		T6	2
auto[2550136832:2684354559]	102	1			T24	2		T38	1		T127	1
auto[2684354560:2818572287]	100	1			T6	1		T220	1		T219	1
auto[2818572288:2952790015]	89	1			T80	2		T136	1		T283	1
auto[2952790016:3087007743]	108	1			T14	1		T36	1		T124	1
auto[3087007744:3221225471]	113	1			T14	2		T133	1		T80	1
auto[3221225472:3355443199]	99	1			T14	1		T6	1		T283	1
auto[3355443200:3489660927]	95	1			T5	1		T6	1		T218	1
auto[3489660928:3623878655]	100	1			T1	1		T79	1		T37	1
auto[3623878656:3758096383]	109	1			T18	1		T91	2		T79	1
auto[3758096384:3892314111]	119	1			T25	3		T73	1		T21	2
auto[3892314112:4026531839]	97	1			T19	1		T80	1		T116	1
auto[4026531840:4160749567]	108	1			T5	1		T14	2		T35	1
auto[4160749568:4294967295]	103	1			T14	1		T18	1		T6	1