Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4614

1

T1

6

T5

8

T14

22

auto[1]

2092

1

T5

2

T14

4

T18

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	180	1			T6	2		T79	2		T71	2
auto[134217728:268435455]	230	1			T14	2		T18	2		T93	2
auto[268435456:402653183]	208	1			T6	4		T19	2		T220	2
auto[402653184:536870911]	242	1			T1	2		T14	2		T6	2
auto[536870912:671088639]	212	1			T14	2		T218	2		T24	2
auto[671088640:805306367]	212	1			T6	2		T24	2		T116	2
auto[805306368:939524095]	186	1			T1	2		T6	4		T71	2
auto[939524096:1073741823]	290	1			T36	2		T128	2		T24	2
auto[1073741824:1207959551]	188	1			T5	2		T14	2		T91	2
auto[1207959552:1342177279]	214	1			T5	2		T14	2		T6	2
auto[1342177280:1476395007]	228	1			T18	2		T19	2		T80	2
auto[1476395008:1610612735]	220	1			T14	2		T6	2		T79	2
auto[1610612736:1744830463]	172	1			T1	2		T5	2		T14	2
auto[1744830464:1879048191]	186	1			T14	2		T6	2		T51	2
auto[1879048192:2013265919]	222	1			T14	2		T35	2		T37	2
auto[2013265920:2147483647]	200	1			T6	2		T102	2		T25	2
auto[2147483648:2281701375]	216	1			T6	2		T71	2		T219	2
auto[2281701376:2415919103]	182	1			T14	2		T18	2		T24	4
auto[2415919104:2550136831]	236	1			T14	2		T35	2		T124	2
auto[2550136832:2684354559]	196	1			T19	2		T263	2		T7	2
auto[2684354560:2818572287]	238	1			T14	2		T6	2		T91	2
auto[2818572288:2952790015]	206	1			T133	2		T80	2		T73	2
auto[2952790016:3087007743]	214	1			T14	2		T228	2		T218	2
auto[3087007744:3221225471]	200	1			T5	2		T6	4		T91	2
auto[3221225472:3355443199]	212	1			T6	2		T51	2		T21	2
auto[3355443200:3489660927]	196	1			T5	2		T36	2		T6	2
auto[3489660928:3623878655]	216	1			T18	2		T6	4		T19	2
auto[3623878656:3758096383]	190	1			T91	2		T102	2		T133	2
auto[3758096384:3892314111]	204	1			T36	2		T19	2		T133	2
auto[3892314112:4026531839]	194	1			T6	4		T102	2		T50	2
auto[4026531840:4160749567]	208	1			T6	4		T228	2		T79	2
auto[4160749568:4294967295]	208	1			T115	2		T151	2		T63	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	128	1			T6	2		T79	2		T71	2
auto[0:134217727]	auto[1]	52	1			T26	2		T7	2		T126	2
auto[134217728:268435455]	auto[0]	148	1			T14	2		T79	2		T19	2
auto[134217728:268435455]	auto[1]	82	1			T18	2		T93	2		T25	2
auto[268435456:402653183]	auto[0]	132	1			T6	4		T19	2		T224	2
auto[268435456:402653183]	auto[1]	76	1			T220	2		T215	2		T48	2
auto[402653184:536870911]	auto[0]	164	1			T1	2		T6	2		T79	2
auto[402653184:536870911]	auto[1]	78	1			T14	2		T25	2		T126	2
auto[536870912:671088639]	auto[0]	156	1			T14	2		T218	2		T24	2
auto[536870912:671088639]	auto[1]	56	1			T141	2		T23	2		T306	2
auto[671088640:805306367]	auto[0]	134	1			T6	2		T24	2		T116	2
auto[671088640:805306367]	auto[1]	78	1			T222	2		T28	2		T64	2
auto[805306368:939524095]	auto[0]	140	1			T1	2		T6	4		T71	2
auto[805306368:939524095]	auto[1]	46	1			T214	2		T63	2		T28	2
auto[939524096:1073741823]	auto[0]	202	1			T36	2		T24	2		T263	2
auto[939524096:1073741823]	auto[1]	88	1			T128	2		T104	2		T45	2
auto[1073741824:1207959551]	auto[0]	142	1			T5	2		T14	2		T91	2
auto[1073741824:1207959551]	auto[1]	46	1			T223	2		T449	2		T322	2
auto[1207959552:1342177279]	auto[0]	140	1			T5	2		T14	2		T6	2
auto[1207959552:1342177279]	auto[1]	74	1			T22	2		T155	2		T64	4
auto[1342177280:1476395007]	auto[0]	162	1			T19	2		T50	2		T24	2
auto[1342177280:1476395007]	auto[1]	66	1			T18	2		T80	2		T65	2
auto[1476395008:1610612735]	auto[0]	148	1			T14	2		T6	2		T79	2
auto[1476395008:1610612735]	auto[1]	72	1			T124	2		T63	2		T132	2
auto[1610612736:1744830463]	auto[0]	114	1			T1	2		T5	2		T14	2
auto[1610612736:1744830463]	auto[1]	58	1			T25	2		T128	2		T7	2
auto[1744830464:1879048191]	auto[0]	118	1			T14	2		T6	2		T51	2
auto[1744830464:1879048191]	auto[1]	68	1			T63	4		T86	2		T448	2
auto[1879048192:2013265919]	auto[0]	138	1			T14	2		T37	2		T217	2
auto[1879048192:2013265919]	auto[1]	84	1			T35	2		T141	4		T222	2
auto[2013265920:2147483647]	auto[0]	138	1			T80	2		T221	2		T136	2
auto[2013265920:2147483647]	auto[1]	62	1			T6	2		T102	2		T25	2
auto[2147483648:2281701375]	auto[0]	160	1			T6	2		T71	2		T219	2
auto[2147483648:2281701375]	auto[1]	56	1			T127	2		T155	2		T87	2
auto[2281701376:2415919103]	auto[0]	136	1			T24	4		T263	2		T156	2
auto[2281701376:2415919103]	auto[1]	46	1			T14	2		T18	2		T210	2
auto[2415919104:2550136831]	auto[0]	162	1			T14	2		T219	2		T217	2
auto[2415919104:2550136831]	auto[1]	74	1			T35	2		T124	2		T38	2
auto[2550136832:2684354559]	auto[0]	122	1			T19	2		T263	2		T210	2
auto[2550136832:2684354559]	auto[1]	74	1			T7	2		T86	2		T265	2
auto[2684354560:2818572287]	auto[0]	174	1			T14	2		T6	2		T91	2
auto[2684354560:2818572287]	auto[1]	64	1			T141	2		T217	2		T64	2
auto[2818572288:2952790015]	auto[0]	146	1			T133	2		T80	2		T73	2
auto[2818572288:2952790015]	auto[1]	60	1			T65	2		T210	2		T269	2
auto[2952790016:3087007743]	auto[0]	158	1			T14	2		T218	2		T50	2
auto[2952790016:3087007743]	auto[1]	56	1			T228	2		T26	2		T7	2
auto[3087007744:3221225471]	auto[0]	122	1			T5	2		T6	2		T38	2
auto[3087007744:3221225471]	auto[1]	78	1			T6	2		T91	2		T38	2
auto[3221225472:3355443199]	auto[0]	146	1			T6	2		T21	2		T156	2
auto[3221225472:3355443199]	auto[1]	66	1			T51	2		T214	2		T63	2
auto[3355443200:3489660927]	auto[0]	136	1			T26	2		T226	2		T140	2
auto[3355443200:3489660927]	auto[1]	60	1			T5	2		T36	2		T6	2
auto[3489660928:3623878655]	auto[0]	138	1			T6	4		T19	2		T80	2
auto[3489660928:3623878655]	auto[1]	78	1			T18	2		T24	2		T74	2
auto[3623878656:3758096383]	auto[0]	128	1			T91	2		T80	2		T24	2
auto[3623878656:3758096383]	auto[1]	62	1			T102	2		T133	2		T115	2
auto[3758096384:3892314111]	auto[0]	152	1			T36	2		T19	2		T80	2
auto[3758096384:3892314111]	auto[1]	52	1			T133	2		T220	2		T219	2
auto[3892314112:4026531839]	auto[0]	132	1			T6	2		T50	2		T128	2
auto[3892314112:4026531839]	auto[1]	62	1			T6	2		T102	2		T87	2
auto[4026531840:4160749567]	auto[0]	144	1			T6	4		T79	2		T80	2
auto[4026531840:4160749567]	auto[1]	64	1			T228	2		T25	2		T103	2
auto[4160749568:4294967295]	auto[0]	154	1			T115	2		T151	2		T269	2
auto[4160749568:4294967295]	auto[1]	54	1			T63	2		T142	2		T29	4