Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2947

1

T1

3

T5

4

T14

11

auto[1]

245

1

T79

1

T80

10

T116

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T14	1		T19	1		T25	1
auto[134217728:268435455]	103	1			T102	1		T22	2		T215	1
auto[268435456:402653183]	118	1			T79	1		T80	2		T24	1
auto[402653184:536870911]	109	1			T14	1		T18	1		T6	1
auto[536870912:671088639]	98	1			T50	1		T219	1		T263	1
auto[671088640:805306367]	105	1			T14	1		T133	1		T80	1
auto[805306368:939524095]	112	1			T14	1		T6	1		T80	1
auto[939524096:1073741823]	93	1			T14	1		T98	1		T219	1
auto[1073741824:1207959551]	98	1			T36	1		T79	1		T19	1
auto[1207959552:1342177279]	79	1			T25	1		T71	1		T312	1
auto[1342177280:1476395007]	106	1			T19	1		T80	1		T219	1
auto[1476395008:1610612735]	106	1			T6	1		T19	1		T26	1
auto[1610612736:1744830463]	98	1			T1	1		T91	1		T25	1
auto[1744830464:1879048191]	91	1			T6	1		T79	1		T218	1
auto[1879048192:2013265919]	100	1			T14	1		T36	1		T6	1
auto[2013265920:2147483647]	96	1			T14	1		T18	1		T133	1
auto[2147483648:2281701375]	97	1			T6	2		T91	1		T133	1
auto[2281701376:2415919103]	99	1			T79	1		T37	1		T80	1
auto[2415919104:2550136831]	110	1			T35	1		T19	1		T80	1
auto[2550136832:2684354559]	99	1			T14	1		T79	1		T19	1
auto[2684354560:2818572287]	98	1			T6	2		T91	1		T51	1
auto[2818572288:2952790015]	96	1			T14	2		T218	1		T80	1
auto[2952790016:3087007743]	87	1			T1	1		T6	1		T25	1
auto[3087007744:3221225471]	101	1			T14	1		T228	1		T79	1
auto[3221225472:3355443199]	100	1			T5	1		T80	1		T51	1
auto[3355443200:3489660927]	97	1			T6	2		T80	1		T50	1
auto[3489660928:3623878655]	99	1			T1	1		T35	1		T116	1
auto[3623878656:3758096383]	113	1			T5	1		T18	1		T6	2
auto[3758096384:3892314111]	78	1			T5	1		T151	1		T262	1
auto[3892314112:4026531839]	95	1			T6	1		T37	1		T80	1
auto[4026531840:4160749567]	113	1			T91	1		T24	1		T21	1
auto[4160749568:4294967295]	112	1			T5	1		T36	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	82	1			T14	1		T19	1		T25	1
auto[0:134217727]	auto[1]	4	1			T412	1		T425	1		T450	1
auto[134217728:268435455]	auto[0]	87	1			T102	1		T22	2		T215	1
auto[134217728:268435455]	auto[1]	16	1			T104	2		T411	1		T294	1
auto[268435456:402653183]	auto[0]	111	1			T79	1		T80	1		T24	1
auto[268435456:402653183]	auto[1]	7	1			T80	1		T294	1		T295	1
auto[402653184:536870911]	auto[0]	105	1			T14	1		T18	1		T6	1
auto[402653184:536870911]	auto[1]	4	1			T383	1		T371	1		T450	1
auto[536870912:671088639]	auto[0]	91	1			T50	1		T219	1		T263	1
auto[536870912:671088639]	auto[1]	7	1			T411	1		T294	1		T297	1
auto[671088640:805306367]	auto[0]	99	1			T14	1		T133	1		T80	1
auto[671088640:805306367]	auto[1]	6	1			T389	1		T444	1		T371	1
auto[805306368:939524095]	auto[0]	105	1			T14	1		T6	1		T50	1
auto[805306368:939524095]	auto[1]	7	1			T80	1		T389	1		T383	1
auto[939524096:1073741823]	auto[0]	89	1			T14	1		T98	1		T219	1
auto[939524096:1073741823]	auto[1]	4	1			T322	1		T446	1		T444	1
auto[1073741824:1207959551]	auto[0]	87	1			T36	1		T79	1		T19	1
auto[1073741824:1207959551]	auto[1]	11	1			T80	1		T105	1		T107	1
auto[1207959552:1342177279]	auto[0]	75	1			T25	1		T71	1		T312	1
auto[1207959552:1342177279]	auto[1]	4	1			T295	1		T297	2		T299	1
auto[1342177280:1476395007]	auto[0]	102	1			T19	1		T219	1		T63	3
auto[1342177280:1476395007]	auto[1]	4	1			T80	1		T383	1		T450	1
auto[1476395008:1610612735]	auto[0]	95	1			T6	1		T19	1		T26	1
auto[1476395008:1610612735]	auto[1]	11	1			T104	2		T107	2		T412	1
auto[1610612736:1744830463]	auto[0]	89	1			T1	1		T91	1		T25	1
auto[1610612736:1744830463]	auto[1]	9	1			T104	2		T411	1		T445	1
auto[1744830464:1879048191]	auto[0]	83	1			T6	1		T79	1		T218	1
auto[1744830464:1879048191]	auto[1]	8	1			T116	1		T371	1		T450	1
auto[1879048192:2013265919]	auto[0]	85	1			T14	1		T36	1		T6	1
auto[1879048192:2013265919]	auto[1]	15	1			T80	1		T106	1		T107	2
auto[2013265920:2147483647]	auto[0]	92	1			T14	1		T18	1		T133	1
auto[2013265920:2147483647]	auto[1]	4	1			T107	1		T322	1		T294	1
auto[2147483648:2281701375]	auto[0]	92	1			T6	2		T91	1		T133	1
auto[2147483648:2281701375]	auto[1]	5	1			T80	1		T259	1		T401	1
auto[2281701376:2415919103]	auto[0]	92	1			T79	1		T37	1		T21	1
auto[2281701376:2415919103]	auto[1]	7	1			T80	1		T104	2		T107	1
auto[2415919104:2550136831]	auto[0]	96	1			T35	1		T19	1		T80	1
auto[2415919104:2550136831]	auto[1]	14	1			T105	1		T411	1		T389	1
auto[2550136832:2684354559]	auto[0]	94	1			T14	1		T79	1		T19	1
auto[2550136832:2684354559]	auto[1]	5	1			T389	1		T371	1		T450	1
auto[2684354560:2818572287]	auto[0]	92	1			T6	2		T91	1		T51	1
auto[2684354560:2818572287]	auto[1]	6	1			T104	1		T411	1		T412	1
auto[2818572288:2952790015]	auto[0]	89	1			T14	2		T218	1		T80	1
auto[2818572288:2952790015]	auto[1]	7	1			T106	1		T389	1		T295	1
auto[2952790016:3087007743]	auto[0]	83	1			T1	1		T6	1		T25	1
auto[2952790016:3087007743]	auto[1]	4	1			T107	1		T413	1		T444	1
auto[3087007744:3221225471]	auto[0]	90	1			T14	1		T228	1		T80	1
auto[3087007744:3221225471]	auto[1]	11	1			T79	1		T80	2		T105	1
auto[3221225472:3355443199]	auto[0]	94	1			T5	1		T51	1		T215	1
auto[3221225472:3355443199]	auto[1]	6	1			T80	1		T104	1		T446	1
auto[3355443200:3489660927]	auto[0]	94	1			T6	2		T80	1		T50	1
auto[3355443200:3489660927]	auto[1]	3	1			T401	1		T450	1		T452	1
auto[3489660928:3623878655]	auto[0]	93	1			T1	1		T35	1		T116	1
auto[3489660928:3623878655]	auto[1]	6	1			T107	1		T297	1		T325	1
auto[3623878656:3758096383]	auto[0]	102	1			T5	1		T18	1		T6	2
auto[3623878656:3758096383]	auto[1]	11	1			T389	1		T295	1		T413	1
auto[3758096384:3892314111]	auto[0]	68	1			T5	1		T151	1		T262	1
auto[3758096384:3892314111]	auto[1]	10	1			T294	1		T371	1		T450	1
auto[3892314112:4026531839]	auto[0]	87	1			T6	1		T37	1		T80	1
auto[3892314112:4026531839]	auto[1]	8	1			T412	1		T389	1		T295	1
auto[4026531840:4160749567]	auto[0]	105	1			T91	1		T24	1		T21	1
auto[4026531840:4160749567]	auto[1]	8	1			T104	1		T107	1		T411	1
auto[4160749568:4294967295]	auto[0]	99	1			T5	1		T36	1		T6	1
auto[4160749568:4294967295]	auto[1]	13	1			T389	1		T294	3		T413	1