Unified Coverage Report :: Group Instance : sealing_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1510

1

T5

3

T14

6

T18

1

auto[1]

1843

1

T1

3

T5

2

T14

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T6	2		T91	1		T19	2
auto[134217728:268435455]	79	1			T14	1		T18	1		T6	1
auto[268435456:402653183]	87	1			T263	1		T21	1		T221	1
auto[402653184:536870911]	97	1			T6	1		T79	1		T128	1
auto[536870912:671088639]	113	1			T14	2		T6	1		T228	1
auto[671088640:805306367]	99	1			T14	1		T18	1		T6	2
auto[805306368:939524095]	118	1			T14	1		T6	2		T263	1
auto[939524096:1073741823]	91	1			T1	1		T5	1		T24	1
auto[1073741824:1207959551]	98	1			T14	1		T79	1		T102	1
auto[1207959552:1342177279]	123	1			T36	1		T6	2		T24	1
auto[1342177280:1476395007]	93	1			T36	1		T124	1		T7	1
auto[1476395008:1610612735]	96	1			T18	1		T6	2		T219	1
auto[1610612736:1744830463]	120	1			T6	1		T80	1		T50	2
auto[1744830464:1879048191]	94	1			T14	1		T6	1		T93	1
auto[1879048192:2013265919]	122	1			T228	1		T80	2		T38	1
auto[2013265920:2147483647]	92	1			T79	1		T25	1		T263	1
auto[2147483648:2281701375]	108	1			T6	2		T80	1		T155	1
auto[2281701376:2415919103]	110	1			T1	1		T18	1		T6	2
auto[2415919104:2550136831]	106	1			T5	1		T6	3		T91	1
auto[2550136832:2684354559]	104	1			T25	1		T218	1		T126	1
auto[2684354560:2818572287]	112	1			T19	1		T25	1		T37	1
auto[2818572288:2952790015]	120	1			T14	1		T6	1		T133	1
auto[2952790016:3087007743]	109	1			T14	1		T91	1		T98	1
auto[3087007744:3221225471]	103	1			T5	1		T25	1		T218	1
auto[3221225472:3355443199]	123	1			T14	1		T19	1		T7	1
auto[3355443200:3489660927]	96	1			T5	1		T36	1		T19	1
auto[3489660928:3623878655]	110	1			T1	1		T35	1		T24	1
auto[3623878656:3758096383]	102	1			T5	1		T79	1		T102	1
auto[3758096384:3892314111]	109	1			T91	1		T37	1		T50	1
auto[3892314112:4026531839]	101	1			T24	1		T136	1		T38	1
auto[4026531840:4160749567]	94	1			T14	3		T35	1		T263	1
auto[4160749568:4294967295]	113	1			T6	1		T37	1		T220	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T19	1		T25	1		T219	1
auto[0:134217727]	auto[1]	60	1			T6	2		T91	1		T19	1
auto[134217728:268435455]	auto[0]	43	1			T14	1		T6	1		T136	1
auto[134217728:268435455]	auto[1]	36	1			T18	1		T39	1		T86	1
auto[268435456:402653183]	auto[0]	44	1			T21	1		T141	1		T214	1
auto[268435456:402653183]	auto[1]	43	1			T263	1		T221	1		T141	1
auto[402653184:536870911]	auto[0]	45	1			T6	1		T24	1		T262	1
auto[402653184:536870911]	auto[1]	52	1			T79	1		T128	1		T63	1
auto[536870912:671088639]	auto[0]	46	1			T14	1		T6	1		T228	1
auto[536870912:671088639]	auto[1]	67	1			T14	1		T80	1		T126	1
auto[671088640:805306367]	auto[0]	45	1			T18	1		T24	1		T21	1
auto[671088640:805306367]	auto[1]	54	1			T14	1		T6	2		T133	1
auto[805306368:939524095]	auto[0]	60	1			T6	1		T263	1		T21	1
auto[805306368:939524095]	auto[1]	58	1			T14	1		T6	1		T74	1
auto[939524096:1073741823]	auto[0]	31	1			T124	1		T63	1		T8	2
auto[939524096:1073741823]	auto[1]	60	1			T1	1		T5	1		T24	1
auto[1073741824:1207959551]	auto[0]	38	1			T14	1		T50	1		T263	1
auto[1073741824:1207959551]	auto[1]	60	1			T79	1		T102	1		T133	1
auto[1207959552:1342177279]	auto[0]	61	1			T24	1		T74	1		T229	1
auto[1207959552:1342177279]	auto[1]	62	1			T36	1		T6	2		T116	2
auto[1342177280:1476395007]	auto[0]	42	1			T124	1		T7	1		T86	1
auto[1342177280:1476395007]	auto[1]	51	1			T36	1		T214	1		T226	1
auto[1476395008:1610612735]	auto[0]	40	1			T6	1		T283	1		T29	1
auto[1476395008:1610612735]	auto[1]	56	1			T18	1		T6	1		T219	1
auto[1610612736:1744830463]	auto[0]	53	1			T223	2		T198	1		T52	1
auto[1610612736:1744830463]	auto[1]	67	1			T6	1		T80	1		T50	2
auto[1744830464:1879048191]	auto[0]	45	1			T14	1		T6	1		T93	1
auto[1744830464:1879048191]	auto[1]	49	1			T102	1		T220	1		T50	1
auto[1879048192:2013265919]	auto[0]	60	1			T228	1		T80	1		T38	1
auto[1879048192:2013265919]	auto[1]	62	1			T80	1		T23	1		T132	1
auto[2013265920:2147483647]	auto[0]	35	1			T263	1		T289	2		T269	1
auto[2013265920:2147483647]	auto[1]	57	1			T79	1		T25	1		T104	1
auto[2147483648:2281701375]	auto[0]	46	1			T6	2		T80	1		T269	1
auto[2147483648:2281701375]	auto[1]	62	1			T155	1		T87	1		T89	1
auto[2281701376:2415919103]	auto[0]	48	1			T24	1		T71	1		T219	1
auto[2281701376:2415919103]	auto[1]	62	1			T1	1		T18	1		T6	2
auto[2415919104:2550136831]	auto[0]	52	1			T5	1		T6	2		T73	1
auto[2415919104:2550136831]	auto[1]	54	1			T6	1		T91	1		T217	1
auto[2550136832:2684354559]	auto[0]	42	1			T25	1		T218	1		T151	1
auto[2550136832:2684354559]	auto[1]	62	1			T126	1		T28	1		T224	1
auto[2684354560:2818572287]	auto[0]	49	1			T25	1		T37	1		T80	1
auto[2684354560:2818572287]	auto[1]	63	1			T19	1		T51	1		T24	1
auto[2818572288:2952790015]	auto[0]	42	1			T406	1		T8	2		T192	1
auto[2818572288:2952790015]	auto[1]	78	1			T14	1		T6	1		T133	1
auto[2952790016:3087007743]	auto[0]	49	1			T14	1		T63	1		T289	1
auto[2952790016:3087007743]	auto[1]	60	1			T91	1		T98	1		T79	1
auto[3087007744:3221225471]	auto[0]	58	1			T25	1		T24	1		T38	1
auto[3087007744:3221225471]	auto[1]	45	1			T5	1		T218	1		T80	1
auto[3221225472:3355443199]	auto[0]	59	1			T19	1		T7	1		T155	1
auto[3221225472:3355443199]	auto[1]	64	1			T14	1		T221	1		T8	2
auto[3355443200:3489660927]	auto[0]	36	1			T5	1		T71	1		T219	1
auto[3355443200:3489660927]	auto[1]	60	1			T36	1		T19	1		T80	1
auto[3489660928:3623878655]	auto[0]	54	1			T136	1		T222	1		T64	1
auto[3489660928:3623878655]	auto[1]	56	1			T1	1		T35	1		T24	1
auto[3623878656:3758096383]	auto[0]	50	1			T5	1		T51	1		T219	1
auto[3623878656:3758096383]	auto[1]	52	1			T79	1		T102	1		T143	1
auto[3758096384:3892314111]	auto[0]	45	1			T37	1		T71	1		T219	1
auto[3758096384:3892314111]	auto[1]	64	1			T91	1		T50	1		T263	1
auto[3892314112:4026531839]	auto[0]	46	1			T136	1		T38	1		T129	1
auto[3892314112:4026531839]	auto[1]	55	1			T24	1		T104	1		T64	1
auto[4026531840:4160749567]	auto[0]	42	1			T14	1		T263	1		T39	1
auto[4026531840:4160749567]	auto[1]	52	1			T14	2		T35	1		T8	1
auto[4160749568:4294967295]	auto[0]	53	1			T37	1		T24	1		T222	1
auto[4160749568:4294967295]	auto[1]	60	1			T6	1		T220	1		T63	1