Unified Coverage Report :: Cond split page

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 LINE       62
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T74,T63
1	1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T17,T75

 LINE       81
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T12,T13
0	1	0	Covered	T2,T17,T75
1	0	0	Covered	T2,T17,T75

 LINE       123
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T17,T75
0	1	0	Covered	T6,T74,T63
1	0	0	Covered	T6,T74,T63

 LINE       498
 EXPRESSION (start_we & cfg_regwen_qs)
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T2,T3

 LINE       529
 EXPRESSION (control_shadowed_we & cfg_regwen_qs)
             ---------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T2,T3

 LINE       642
 EXPRESSION (sideload_clear_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T3,T4

 LINE       701
 EXPRESSION (reseed_interval_shadowed_we & reseed_interval_regwen_qs)
             -------------1-------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T157,T158,T108
1	1	Covered	T1,T2,T3

 LINE       763
 EXPRESSION (sealing_sw_binding_0_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T14
1	1	Covered	T1,T5,T14

 LINE       795
 EXPRESSION (sealing_sw_binding_1_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       827
 EXPRESSION (sealing_sw_binding_2_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       859
 EXPRESSION (sealing_sw_binding_3_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T14
1	1	Covered	T1,T5,T14

 LINE       891
 EXPRESSION (sealing_sw_binding_4_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       923
 EXPRESSION (sealing_sw_binding_5_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       955
 EXPRESSION (sealing_sw_binding_6_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       987
 EXPRESSION (sealing_sw_binding_7_we & sw_binding_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1019
 EXPRESSION (attest_sw_binding_0_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T14
1	1	Covered	T1,T5,T14

 LINE       1051
 EXPRESSION (attest_sw_binding_1_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1083
 EXPRESSION (attest_sw_binding_2_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1115
 EXPRESSION (attest_sw_binding_3_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1147
 EXPRESSION (attest_sw_binding_4_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1179
 EXPRESSION (attest_sw_binding_5_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1211
 EXPRESSION (attest_sw_binding_6_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1243
 EXPRESSION (attest_sw_binding_7_we & sw_binding_regwen_qs)
             -----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1275
 EXPRESSION (salt_0_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1307
 EXPRESSION (salt_1_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1339
 EXPRESSION (salt_2_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1371
 EXPRESSION (salt_3_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1403
 EXPRESSION (salt_4_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1435
 EXPRESSION (salt_5_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1467
 EXPRESSION (salt_6_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1499
 EXPRESSION (salt_7_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1531
 EXPRESSION (key_version_we & cfg_regwen_qs)
             -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T14,T18
1	1	Covered	T1,T5,T14

 LINE       1590
 EXPRESSION (max_creator_key_ver_shadowed_we & max_creator_key_ver_regwen_qs)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T14
1	1	Covered	T5,T14,T18

 LINE       1659
 EXPRESSION (max_owner_int_key_ver_shadowed_we & max_owner_int_key_ver_regwen_qs)
             ----------------1----------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T14
1	1	Covered	T1,T5,T14

 LINE       1728
 EXPRESSION (max_owner_key_ver_shadowed_we & max_owner_key_ver_regwen_qs)
             --------------1--------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T14
1	1	Covered	T5,T14,T18

 LINE       2944
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2945
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       2946
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       2947
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       2948
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_CFG_REGWEN_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       2949
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_START_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2950
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_CONTROL_SHADOWED_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2951
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SIDELOAD_CLEAR_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2952
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_RESEED_INTERVAL_REGWEN_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       2953
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_RESEED_INTERVAL_SHADOWED_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2954
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_BINDING_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2955
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2956
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2957
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2958
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2959
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2960
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2961
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2962
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SEALING_SW_BINDING_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2963
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_0_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2964
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_1_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2965
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_2_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2966
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_3_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2967
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_4_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2968
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_5_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2969
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_6_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2970
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ATTEST_SW_BINDING_7_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2971
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_0_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2972
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_1_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2973
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_2_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2974
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_3_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2975
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_4_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2976
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_5_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2977
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_6_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2978
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SALT_7_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2979
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_KEY_VERSION_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2980
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2981
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_MAX_CREATOR_KEY_VER_SHADOWED_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2982
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2983
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_MAX_OWNER_INT_KEY_VER_SHADOWED_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2984
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2985
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_MAX_OWNER_KEY_VER_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2986
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2987
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2988
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2989
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2990
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2991
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2992
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2993
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2994
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2995
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2996
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2997
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2998
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2999
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3000
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3001
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3002
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_WORKING_STATE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3003
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_OP_STATUS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3004
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_ERR_CODE_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3005
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_FAULT_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3006
 EXPRESSION (reg_addr == keymgr_reg_pkg::KEYMGR_DEBUG_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3009
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3009
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       3013
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T6,T75

 LINE       3013
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | 
     58  (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | 
     59  (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | 
     60  (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | 
     61  (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | 
     62  (addr_hit[61] & ((|(4'b0011 & (~reg_be))))) | 
     63  (addr_hit[62] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
63 (addr_hit[62] & ((\|(4'...	Covered	T1,T2,T3
62 (addr_hit[61] & ((\|(4'...	Covered	T1,T2,T3
61 (addr_hit[60] & ((\|(4'...	Covered	T1,T2,T3
60 (addr_hit[59] & ((\|(4'...	Covered	T2,T3,T5
59 (addr_hit[58] & ((\|(4'...	Covered	T1,T2,T3
58 (addr_hit[57] & ((\|(4'...	Covered	T1,T2,T3
57 (addr_hit[56] & ((\|(4'...	Covered	T1,T2,T3
56 (addr_hit[55] & ((\|(4'...	Covered	T1,T2,T3
55 (addr_hit[54] & ((\|(4'...	Covered	T1,T2,T3
54 (addr_hit[53] & ((\|(4'...	Covered	T1,T2,T3
53 (addr_hit[52] & ((\|(4'...	Covered	T1,T2,T3
52 (addr_hit[51] & ((\|(4'...	Covered	T2,T3,T4
51 (addr_hit[50] & ((\|(4'...	Covered	T1,T2,T3
50 (addr_hit[49] & ((\|(4'...	Covered	T1,T2,T3
49 (addr_hit[48] & ((\|(4'...	Covered	T1,T2,T3
48 (addr_hit[47] & ((\|(4'...	Covered	T1,T2,T3
47 (addr_hit[46] & ((\|(4'...	Covered	T1,T2,T3
46 (addr_hit[45] & ((\|(4'...	Covered	T1,T2,T3
45 (addr_hit[44] & ((\|(4'...	Covered	T1,T2,T3
44 (addr_hit[43] & ((\|(4'...	Covered	T1,T2,T3
43 (addr_hit[42] & ((\|(4'...	Covered	T1,T2,T3
42 (addr_hit[41] & ((\|(4'...	Covered	T2,T3,T5
41 (addr_hit[40] & ((\|(4'...	Covered	T2,T3,T5
40 (addr_hit[39] & ((\|(4'...	Covered	T2,T3,T5
39 (addr_hit[38] & ((\|(4'...	Covered	T2,T3,T5
38 (addr_hit[37] & ((\|(4'...	Covered	T2,T3,T5
37 (addr_hit[36] & ((\|(4'...	Covered	T2,T3,T5
36 (addr_hit[35] & ((\|(4'...	Covered	T2,T3,T5
35 (addr_hit[34] & ((\|(4'...	Covered	T2,T3,T5
34 (addr_hit[33] & ((\|(4'...	Covered	T2,T3,T5
33 (addr_hit[32] & ((\|(4'...	Covered	T2,T3,T5
32 (addr_hit[31] & ((\|(4'...	Covered	T2,T3,T5
31 (addr_hit[30] & ((\|(4'...	Covered	T2,T3,T5
30 (addr_hit[29] & ((\|(4'...	Covered	T2,T3,T5
29 (addr_hit[28] & ((\|(4'...	Covered	T2,T3,T5
28 (addr_hit[27] & ((\|(4'...	Covered	T2,T3,T5
27 (addr_hit[26] & ((\|(4'...	Covered	T2,T3,T5
26 (addr_hit[25] & ((\|(4'...	Covered	T2,T3,T5
25 (addr_hit[24] & ((\|(4'...	Covered	T2,T3,T5
24 (addr_hit[23] & ((\|(4'...	Covered	T2,T3,T5
23 (addr_hit[22] & ((\|(4'...	Covered	T2,T3,T5
22 (addr_hit[21] & ((\|(4'...	Covered	T2,T3,T5
21 (addr_hit[20] & ((\|(4'...	Covered	T2,T3,T5
20 (addr_hit[19] & ((\|(4'...	Covered	T2,T3,T5
19 (addr_hit[18] & ((\|(4'...	Covered	T2,T3,T5
18 (addr_hit[17] & ((\|(4'...	Covered	T2,T3,T5
17 (addr_hit[16] & ((\|(4'...	Covered	T2,T3,T5
16 (addr_hit[15] & ((\|(4'...	Covered	T2,T3,T5
15 (addr_hit[14] & ((\|(4'...	Covered	T2,T3,T5
14 (addr_hit[13] & ((\|(4'...	Covered	T2,T3,T5
13 (addr_hit[12] & ((\|(4'...	Covered	T2,T3,T5
12 (addr_hit[11] & ((\|(4'...	Covered	T2,T3,T5
11 (addr_hit[10] & ((\|(4'...	Covered	T2,T3,T5
10 (addr_hit[9] & ((\|(4'b...	Covered	T2,T3,T5
9 (addr_hit[8] & ((\|(4'b...	Covered	T2,T3,T5
8 (addr_hit[7] & ((\|(4'b...	Covered	T2,T3,T5
7 (addr_hit[6] & ((\|(4'b...	Covered	T2,T3,T5
6 (addr_hit[5] & ((\|(4'b...	Covered	T2,T3,T5
5 (addr_hit[4] & ((\|(4'b...	Covered	T2,T3,T5
4 (addr_hit[3] & ((\|(4'b...	Covered	T2,T3,T5
3 (addr_hit[2] & ((\|(4'b...	Covered	T2,T3,T5
2 (addr_hit[1] & ((\|(4'b...	Covered	T2,T3,T5
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T2,T3