| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.78 | 99.04 | 98.07 | 98.46 | 100.00 | 99.02 | 98.63 | 91.27 |
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.2480596373 | Aug 29 12:10:44 AM UTC 24 | Aug 29 12:10:46 AM UTC 24 | 13633990 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4174771464 | Aug 29 12:10:42 AM UTC 24 | Aug 29 12:10:47 AM UTC 24 | 122905871 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.2220861637 | Aug 29 12:10:40 AM UTC 24 | Aug 29 12:10:48 AM UTC 24 | 102776355 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2138309370 | Aug 29 12:10:45 AM UTC 24 | Aug 29 12:10:48 AM UTC 24 | 92355358 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.2097202373 | Aug 29 12:10:47 AM UTC 24 | Aug 29 12:10:49 AM UTC 24 | 31862753 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.4024712017 | Aug 29 12:10:47 AM UTC 24 | Aug 29 12:10:49 AM UTC 24 | 39294307 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.2840078686 | Aug 29 12:10:43 AM UTC 24 | Aug 29 12:10:49 AM UTC 24 | 130710374 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1991025165 | Aug 29 12:10:45 AM UTC 24 | Aug 29 12:10:49 AM UTC 24 | 42288067 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1233722611 | Aug 29 12:10:45 AM UTC 24 | Aug 29 12:10:50 AM UTC 24 | 331420980 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.512687512 | Aug 29 12:10:43 AM UTC 24 | Aug 29 12:10:50 AM UTC 24 | 168675742 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2163749550 | Aug 29 12:10:42 AM UTC 24 | Aug 29 12:10:50 AM UTC 24 | 1115944541 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.177465419 | Aug 29 12:10:37 AM UTC 24 | Aug 29 12:10:50 AM UTC 24 | 362509528 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3068896672 | Aug 29 12:10:45 AM UTC 24 | Aug 29 12:10:51 AM UTC 24 | 303958988 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.572915850 | Aug 29 12:10:46 AM UTC 24 | Aug 29 12:10:51 AM UTC 24 | 53360323 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4154489036 | Aug 29 12:10:48 AM UTC 24 | Aug 29 12:10:52 AM UTC 24 | 46465279 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.1433133178 | Aug 29 12:10:51 AM UTC 24 | Aug 29 12:10:53 AM UTC 24 | 22226881 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1651915019 | Aug 29 12:10:51 AM UTC 24 | Aug 29 12:10:53 AM UTC 24 | 30086618 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2895471690 | Aug 29 12:10:40 AM UTC 24 | Aug 29 12:10:53 AM UTC 24 | 2073371412 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.216917057 | Aug 29 12:10:46 AM UTC 24 | Aug 29 12:10:53 AM UTC 24 | 373282070 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.414303443 | Aug 29 12:10:48 AM UTC 24 | Aug 29 12:10:54 AM UTC 24 | 123710138 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3366300157 | Aug 29 12:10:56 AM UTC 24 | Aug 29 12:11:00 AM UTC 24 | 178991283 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1867542152 | Aug 29 12:10:49 AM UTC 24 | Aug 29 12:10:54 AM UTC 24 | 1208486656 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.839447781 | Aug 29 12:10:51 AM UTC 24 | Aug 29 12:10:54 AM UTC 24 | 120435911 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3619077821 | Aug 29 12:10:53 AM UTC 24 | Aug 29 12:10:55 AM UTC 24 | 39784539 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1227321875 | Aug 29 12:10:53 AM UTC 24 | Aug 29 12:10:55 AM UTC 24 | 20051784 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2855661458 | Aug 29 12:10:52 AM UTC 24 | Aug 29 12:10:55 AM UTC 24 | 126765936 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2803015329 | Aug 29 12:10:49 AM UTC 24 | Aug 29 12:10:56 AM UTC 24 | 123282026 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.314064593 | Aug 29 12:10:52 AM UTC 24 | Aug 29 12:10:56 AM UTC 24 | 47870513 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2469613594 | Aug 29 12:10:53 AM UTC 24 | Aug 29 12:10:56 AM UTC 24 | 241779234 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.4225071826 | Aug 29 12:10:54 AM UTC 24 | Aug 29 12:10:58 AM UTC 24 | 118039186 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2980926485 | Aug 29 12:10:49 AM UTC 24 | Aug 29 12:10:58 AM UTC 24 | 552569384 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.563150057 | Aug 29 12:10:56 AM UTC 24 | Aug 29 12:10:58 AM UTC 24 | 63366201 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2773270491 | Aug 29 12:10:54 AM UTC 24 | Aug 29 12:10:58 AM UTC 24 | 95911880 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2950384894 | Aug 29 12:10:54 AM UTC 24 | Aug 29 12:10:58 AM UTC 24 | 75951664 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.3859891801 | Aug 29 12:10:56 AM UTC 24 | Aug 29 12:10:59 AM UTC 24 | 24524767 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.671483448 | Aug 29 12:10:56 AM UTC 24 | Aug 29 12:11:01 AM UTC 24 | 34591487 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.132351847 | Aug 29 12:10:56 AM UTC 24 | Aug 29 12:11:01 AM UTC 24 | 98847250 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.786761852 | Aug 29 12:10:51 AM UTC 24 | Aug 29 12:11:01 AM UTC 24 | 318248682 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1900152882 | Aug 29 12:10:59 AM UTC 24 | Aug 29 12:11:01 AM UTC 24 | 37643111 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.639744519 | Aug 29 12:10:59 AM UTC 24 | Aug 29 12:11:02 AM UTC 24 | 19303245 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3356129195 | Aug 29 12:11:00 AM UTC 24 | Aug 29 12:11:02 AM UTC 24 | 112143644 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.2898670318 | Aug 29 12:10:58 AM UTC 24 | Aug 29 12:11:02 AM UTC 24 | 73251024 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3362850051 | Aug 29 12:11:00 AM UTC 24 | Aug 29 12:11:03 AM UTC 24 | 56873935 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1318451289 | Aug 29 12:11:00 AM UTC 24 | Aug 29 12:11:03 AM UTC 24 | 165709522 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.824437181 | Aug 29 12:11:01 AM UTC 24 | Aug 29 12:11:03 AM UTC 24 | 94448763 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1052895271 | Aug 29 12:10:54 AM UTC 24 | Aug 29 12:11:03 AM UTC 24 | 337613271 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3784358747 | Aug 29 12:10:58 AM UTC 24 | Aug 29 12:11:03 AM UTC 24 | 142283433 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2119564312 | Aug 29 12:10:56 AM UTC 24 | Aug 29 12:11:03 AM UTC 24 | 227566823 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4156043538 | Aug 29 12:10:58 AM UTC 24 | Aug 29 12:11:04 AM UTC 24 | 275551978 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.2307747848 | Aug 29 12:11:03 AM UTC 24 | Aug 29 12:11:05 AM UTC 24 | 16448557 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.1053992161 | Aug 29 12:11:03 AM UTC 24 | Aug 29 12:11:05 AM UTC 24 | 11242838 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.1485199742 | Aug 29 12:11:03 AM UTC 24 | Aug 29 12:11:05 AM UTC 24 | 26365265 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1884849913 | Aug 29 12:10:53 AM UTC 24 | Aug 29 12:11:06 AM UTC 24 | 411260845 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1650042393 | Aug 29 12:11:03 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 179857715 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.894410705 | Aug 29 12:11:01 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 356931421 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.359816682 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 10507494 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.3655532743 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 13085346 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.536653236 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 22681325 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.960926233 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 9146983 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.2778010913 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 10638250 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3025452188 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 50017565 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3374639135 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 22556378 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.590007848 | Aug 29 12:11:05 AM UTC 24 | Aug 29 12:11:07 AM UTC 24 | 46604543 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4196211372 | Aug 29 12:10:53 AM UTC 24 | Aug 29 12:11:08 AM UTC 24 | 736576299 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1131201223 | Aug 29 12:11:07 AM UTC 24 | Aug 29 12:11:09 AM UTC 24 | 13654888 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.3133498685 | Aug 29 12:11:07 AM UTC 24 | Aug 29 12:11:09 AM UTC 24 | 11453262 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1492998316 | Aug 29 12:11:07 AM UTC 24 | Aug 29 12:11:09 AM UTC 24 | 19942491 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.4179763976 | Aug 29 12:11:01 AM UTC 24 | Aug 29 12:11:09 AM UTC 24 | 1191633814 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.635083844 | Aug 29 12:11:03 AM UTC 24 | Aug 29 12:11:09 AM UTC 24 | 118476493 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2838104397 | Aug 29 12:11:00 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 2037551565 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.2383386293 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 27994308 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.3694120492 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 52346707 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2089642682 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 42665199 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.1909890535 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 13040107 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1496880211 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 34003005 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3991326089 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 49269052 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3905024338 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 48000727 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2928682978 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 16946162 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2431473918 | Aug 29 12:11:10 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 33369430 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2597282938 | Aug 29 12:11:09 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 11478293 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1789512774 | Aug 29 12:11:10 AM UTC 24 | Aug 29 12:11:11 AM UTC 24 | 38424971 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.854313773 | Aug 29 12:11:10 AM UTC 24 | Aug 29 12:11:12 AM UTC 24 | 26158325 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4210486352 | Aug 29 12:11:11 AM UTC 24 | Aug 29 12:11:13 AM UTC 24 | 18619244 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.3703153656 | Aug 29 12:11:11 AM UTC 24 | Aug 29 12:11:13 AM UTC 24 | 9073587 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.392008474 | Aug 29 12:11:11 AM UTC 24 | Aug 29 12:11:13 AM UTC 24 | 32240850 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.198724523 | Aug 29 12:11:11 AM UTC 24 | Aug 29 12:11:13 AM UTC 24 | 10579249 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3055424065 | Aug 29 12:11:11 AM UTC 24 | Aug 29 12:11:14 AM UTC 24 | 45644548 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.3945949837 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 316907061 ps |
| CPU time | 4.32 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:05 PM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945949837 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3945949837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.4178601754 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 644335110 ps |
| CPU time | 17.58 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:28 PM UTC 24 |
| Peak memory | 232288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4178601754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr _stress_all_with_rand_reset.4178601754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.401186771 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1301645815 ps |
| CPU time | 50.81 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:52:13 PM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401186771 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.401186771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.1283866509 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1042745137 ps |
| CPU time | 12.12 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:20 PM UTC 24 |
| Peak memory | 254412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283866509 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1283866509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.70292471 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 437017063 ps |
| CPU time | 21.34 seconds |
| Started | Aug 28 10:51:45 PM UTC 24 |
| Finished | Aug 28 10:52:08 PM UTC 24 |
| Peak memory | 232312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=70292471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_s tress_all_with_rand_reset.70292471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.4158754246 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5973538369 ps |
| CPU time | 26.11 seconds |
| Started | Aug 28 10:51:26 PM UTC 24 |
| Finished | Aug 28 10:51:55 PM UTC 24 |
| Peak memory | 232336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158754246 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4158754246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.3579013435 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 103012259 ps |
| CPU time | 7.39 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:18 PM UTC 24 |
| Peak memory | 226188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579013435 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3579013435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.415879286 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 54829847 ps |
| CPU time | 4.33 seconds |
| Started | Aug 28 10:51:24 PM UTC 24 |
| Finished | Aug 28 10:51:29 PM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415879286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.415879286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.3335220221 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 664070974 ps |
| CPU time | 36.85 seconds |
| Started | Aug 28 10:51:40 PM UTC 24 |
| Finished | Aug 28 10:52:19 PM UTC 24 |
| Peak memory | 232036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335220221 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3335220221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.1671675305 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 335475371 ps |
| CPU time | 3.64 seconds |
| Started | Aug 28 10:51:11 PM UTC 24 |
| Finished | Aug 28 10:51:18 PM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671675305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1671675305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.1420373782 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 187423120 ps |
| CPU time | 3.57 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:04 PM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420373782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1420373782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.232556896 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 96405828 ps |
| CPU time | 7.18 seconds |
| Started | Aug 29 12:09:43 AM UTC 24 |
| Finished | Aug 29 12:09:51 AM UTC 24 |
| Peak memory | 232680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232556896 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.232556896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.1088690952 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2244710170 ps |
| CPU time | 13.4 seconds |
| Started | Aug 28 10:52:35 PM UTC 24 |
| Finished | Aug 28 10:52:49 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088690952 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1088690952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.1033507373 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 152548416 ps |
| CPU time | 5.04 seconds |
| Started | Aug 28 10:53:15 PM UTC 24 |
| Finished | Aug 28 10:53:22 PM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033507373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1033507373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all_with_rand_reset.287624671 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 575226835 ps |
| CPU time | 16.47 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:51:39 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=287624671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_ stress_all_with_rand_reset.287624671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.3168623941 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1939095456 ps |
| CPU time | 25.48 seconds |
| Started | Aug 28 10:51:44 PM UTC 24 |
| Finished | Aug 28 10:52:11 PM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168623941 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3168623941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.1179096748 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 94130725 ps |
| CPU time | 5.38 seconds |
| Started | Aug 28 10:51:19 PM UTC 24 |
| Finished | Aug 28 10:51:25 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179096748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1179096748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.199692458 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2571469242 ps |
| CPU time | 136.63 seconds |
| Started | Aug 28 10:51:18 PM UTC 24 |
| Finished | Aug 28 10:53:38 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199692458 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.199692458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.2357360983 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 125631877 ps |
| CPU time | 7.62 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:51:38 PM UTC 24 |
| Peak memory | 226240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357360983 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2357360983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3469437219 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 266609077 ps |
| CPU time | 5.13 seconds |
| Started | Aug 29 12:09:53 AM UTC 24 |
| Finished | Aug 29 12:10:00 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469437219 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.3469437219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.36660370 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 187021039 ps |
| CPU time | 3.47 seconds |
| Started | Aug 28 10:51:24 PM UTC 24 |
| Finished | Aug 28 10:51:29 PM UTC 24 |
| Peak memory | 230736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36660370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.36660370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.409333230 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 250948379 ps |
| CPU time | 2.88 seconds |
| Started | Aug 28 10:51:36 PM UTC 24 |
| Finished | Aug 28 10:51:40 PM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409333230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.409333230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.4083579212 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 388464479 ps |
| CPU time | 9.64 seconds |
| Started | Aug 28 10:51:55 PM UTC 24 |
| Finished | Aug 28 10:52:06 PM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083579212 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4083579212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.1458985296 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2298230007 ps |
| CPU time | 117.5 seconds |
| Started | Aug 28 10:52:51 PM UTC 24 |
| Finished | Aug 28 10:54:51 PM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458985296 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1458985296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.1208884036 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 71198390 ps |
| CPU time | 3.45 seconds |
| Started | Aug 28 10:51:09 PM UTC 24 |
| Finished | Aug 28 10:51:14 PM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208884036 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1208884036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.3610374001 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 10773906641 ps |
| CPU time | 78.83 seconds |
| Started | Aug 28 10:52:09 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 228192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610374001 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3610374001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.3023139287 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 196956639 ps |
| CPU time | 10.88 seconds |
| Started | Aug 28 10:51:31 PM UTC 24 |
| Finished | Aug 28 10:51:43 PM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3023139287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr _stress_all_with_rand_reset.3023139287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.3329119777 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1321063068 ps |
| CPU time | 7.17 seconds |
| Started | Aug 28 10:51:44 PM UTC 24 |
| Finished | Aug 28 10:51:53 PM UTC 24 |
| Peak memory | 219952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329119777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3329119777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.3364741484 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 194681474 ps |
| CPU time | 4.39 seconds |
| Started | Aug 28 10:53:12 PM UTC 24 |
| Finished | Aug 28 10:53:18 PM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364741484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3364741484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.2652179739 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 31605593 ps |
| CPU time | 2.85 seconds |
| Started | Aug 28 10:52:58 PM UTC 24 |
| Finished | Aug 28 10:53:02 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652179739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2652179739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.3580152977 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 208304295 ps |
| CPU time | 8.03 seconds |
| Started | Aug 28 10:51:40 PM UTC 24 |
| Finished | Aug 28 10:51:50 PM UTC 24 |
| Peak memory | 232408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3580152977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr _stress_all_with_rand_reset.3580152977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.530880432 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1743006210 ps |
| CPU time | 89.47 seconds |
| Started | Aug 28 10:50:54 PM UTC 24 |
| Finished | Aug 28 10:52:26 PM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530880432 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.530880432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.3046811343 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 461391519 ps |
| CPU time | 4.64 seconds |
| Started | Aug 28 10:52:19 PM UTC 24 |
| Finished | Aug 28 10:52:25 PM UTC 24 |
| Peak memory | 228804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046811343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3046811343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.2714106967 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1024029928 ps |
| CPU time | 28.1 seconds |
| Started | Aug 28 10:51:52 PM UTC 24 |
| Finished | Aug 28 10:52:21 PM UTC 24 |
| Peak memory | 228200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714106967 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2714106967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.2651653821 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 58207546 ps |
| CPU time | 1.65 seconds |
| Started | Aug 28 10:51:57 PM UTC 24 |
| Finished | Aug 28 10:52:00 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651653821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2651653821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.3559256099 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 174327578 ps |
| CPU time | 3.38 seconds |
| Started | Aug 28 10:50:52 PM UTC 24 |
| Finished | Aug 28 10:51:03 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559256099 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3559256099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.3762852165 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 432428093 ps |
| CPU time | 10.69 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:55:12 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762852165 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3762852165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.1666672966 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 57131823 ps |
| CPU time | 1.4 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:12 PM UTC 24 |
| Peak memory | 212284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666672966 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1666672966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.1929628599 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 453446772 ps |
| CPU time | 4.26 seconds |
| Started | Aug 28 10:53:06 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929628599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1929628599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.283356325 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 94460195 ps |
| CPU time | 3.57 seconds |
| Started | Aug 29 12:10:02 AM UTC 24 |
| Finished | Aug 29 12:10:07 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283356325 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.283356325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.1750532781 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 166891465 ps |
| CPU time | 4.16 seconds |
| Started | Aug 28 10:50:59 PM UTC 24 |
| Finished | Aug 28 10:51:15 PM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750532781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1750532781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.2563406665 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1285279361 ps |
| CPU time | 30.25 seconds |
| Started | Aug 28 10:51:57 PM UTC 24 |
| Finished | Aug 28 10:52:29 PM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563406665 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2563406665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.216917057 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 373282070 ps |
| CPU time | 5.55 seconds |
| Started | Aug 29 12:10:46 AM UTC 24 |
| Finished | Aug 29 12:10:53 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216917057 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.216917057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.1298956048 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2068432539 ps |
| CPU time | 46.77 seconds |
| Started | Aug 28 10:52:03 PM UTC 24 |
| Finished | Aug 28 10:52:52 PM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298956048 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1298956048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.2876226817 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 119593363 ps |
| CPU time | 7.47 seconds |
| Started | Aug 28 10:52:40 PM UTC 24 |
| Finished | Aug 28 10:52:49 PM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876226817 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2876226817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.2263512702 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 293246571 ps |
| CPU time | 4.7 seconds |
| Started | Aug 28 10:50:59 PM UTC 24 |
| Finished | Aug 28 10:51:16 PM UTC 24 |
| Peak memory | 230188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263512702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2263512702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.4270574704 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 673927691 ps |
| CPU time | 19.37 seconds |
| Started | Aug 28 10:53:41 PM UTC 24 |
| Finished | Aug 28 10:54:02 PM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4270574704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymg r_stress_all_with_rand_reset.4270574704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.1093135014 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 274306663 ps |
| CPU time | 7.75 seconds |
| Started | Aug 29 12:09:44 AM UTC 24 |
| Finished | Aug 29 12:09:53 AM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093135014 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.1093135014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.1759856711 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 314315742 ps |
| CPU time | 7.35 seconds |
| Started | Aug 28 10:51:22 PM UTC 24 |
| Finished | Aug 28 10:51:30 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759856711 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1759856711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.848039651 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 155929428 ps |
| CPU time | 3.05 seconds |
| Started | Aug 28 10:53:43 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 228400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848039651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.848039651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.4289643579 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 913017418 ps |
| CPU time | 31.35 seconds |
| Started | Aug 28 10:52:53 PM UTC 24 |
| Finished | Aug 28 10:53:26 PM UTC 24 |
| Peak memory | 230988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289643579 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4289643579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.2851734110 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1979975636 ps |
| CPU time | 21.55 seconds |
| Started | Aug 28 10:53:31 PM UTC 24 |
| Finished | Aug 28 10:53:53 PM UTC 24 |
| Peak memory | 232620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851734110 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2851734110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.229651012 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 264142190 ps |
| CPU time | 6.64 seconds |
| Started | Aug 28 10:51:18 PM UTC 24 |
| Finished | Aug 28 10:51:27 PM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229651012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.229651012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.1545067796 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 404160130 ps |
| CPU time | 20.24 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:54:03 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545067796 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1545067796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.922561638 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 192361396 ps |
| CPU time | 3.61 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:53:24 PM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922561638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.922561638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.886860620 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 126324104 ps |
| CPU time | 7.71 seconds |
| Started | Aug 28 10:52:41 PM UTC 24 |
| Finished | Aug 28 10:52:50 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886860620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.886860620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.615798351 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 5313009572 ps |
| CPU time | 31.26 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:36 PM UTC 24 |
| Peak memory | 232288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615798351 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.615798351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3934180774 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 8724996870 ps |
| CPU time | 103.49 seconds |
| Started | Aug 28 10:51:35 PM UTC 24 |
| Finished | Aug 28 10:53:21 PM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934180774 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3934180774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.2740612110 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 165950467 ps |
| CPU time | 2.82 seconds |
| Started | Aug 28 10:52:20 PM UTC 24 |
| Finished | Aug 28 10:52:24 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740612110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2740612110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.3834121938 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 26848425 ps |
| CPU time | 1.59 seconds |
| Started | Aug 28 10:52:37 PM UTC 24 |
| Finished | Aug 28 10:52:40 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834121938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3834121938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3375977404 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 422088450 ps |
| CPU time | 2.85 seconds |
| Started | Aug 29 12:09:48 AM UTC 24 |
| Finished | Aug 29 12:09:51 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375977404 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.3375977404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.2567683331 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 263618134 ps |
| CPU time | 7.95 seconds |
| Started | Aug 29 12:10:26 AM UTC 24 |
| Finished | Aug 29 12:10:35 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567683331 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.2567683331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.4223431385 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 77873909 ps |
| CPU time | 3.73 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 232404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223431385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4223431385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.1734752600 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 217130894 ps |
| CPU time | 2.75 seconds |
| Started | Aug 28 10:50:54 PM UTC 24 |
| Finished | Aug 28 10:51:08 PM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734752600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1734752600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.1825298494 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 351496290 ps |
| CPU time | 5.58 seconds |
| Started | Aug 28 10:52:11 PM UTC 24 |
| Finished | Aug 28 10:52:18 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825298494 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1825298494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1618325368 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 444624494 ps |
| CPU time | 8.78 seconds |
| Started | Aug 28 10:53:01 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 232252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618325368 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1618325368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.2083499807 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 696142497 ps |
| CPU time | 6.72 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:32 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083499807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2083499807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.1549242235 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 93184461 ps |
| CPU time | 4.06 seconds |
| Started | Aug 28 10:51:18 PM UTC 24 |
| Finished | Aug 28 10:51:24 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549242235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1549242235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.177465419 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 362509528 ps |
| CPU time | 12.06 seconds |
| Started | Aug 29 12:10:37 AM UTC 24 |
| Finished | Aug 29 12:10:50 AM UTC 24 |
| Peak memory | 226348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177465419 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.177465419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.3099890095 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 131356929 ps |
| CPU time | 4.17 seconds |
| Started | Aug 28 10:53:40 PM UTC 24 |
| Finished | Aug 28 10:53:45 PM UTC 24 |
| Peak memory | 232696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099890095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3099890095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.3810217767 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 104446745 ps |
| CPU time | 4.87 seconds |
| Started | Aug 28 10:52:43 PM UTC 24 |
| Finished | Aug 28 10:52:48 PM UTC 24 |
| Peak memory | 232864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810217767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3810217767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.1200360588 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 69319040 ps |
| CPU time | 2.99 seconds |
| Started | Aug 28 10:51:13 PM UTC 24 |
| Finished | Aug 28 10:51:18 PM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200360588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1200360588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.3938697188 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 229617051 ps |
| CPU time | 3.47 seconds |
| Started | Aug 28 10:54:50 PM UTC 24 |
| Finished | Aug 28 10:55:05 PM UTC 24 |
| Peak memory | 226328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938697188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3938697188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.3751236976 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4232736296 ps |
| CPU time | 13.71 seconds |
| Started | Aug 28 10:51:58 PM UTC 24 |
| Finished | Aug 28 10:52:13 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751236976 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3751236976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.732175036 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4031311955 ps |
| CPU time | 42.53 seconds |
| Started | Aug 28 10:52:15 PM UTC 24 |
| Finished | Aug 28 10:52:59 PM UTC 24 |
| Peak memory | 232356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732175036 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.732175036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.158345318 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 626166401 ps |
| CPU time | 4.04 seconds |
| Started | Aug 28 10:52:24 PM UTC 24 |
| Finished | Aug 28 10:52:29 PM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158345318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.158345318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.366792208 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 163544705 ps |
| CPU time | 7.47 seconds |
| Started | Aug 28 10:52:58 PM UTC 24 |
| Finished | Aug 28 10:53:07 PM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366792208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.366792208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.514250218 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 62063335 ps |
| CPU time | 3.58 seconds |
| Started | Aug 28 10:53:14 PM UTC 24 |
| Finished | Aug 28 10:53:19 PM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514250218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.514250218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.401591047 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 540639525 ps |
| CPU time | 19.4 seconds |
| Started | Aug 28 10:51:16 PM UTC 24 |
| Finished | Aug 28 10:51:37 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401591047 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.401591047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.4208382749 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 312072923 ps |
| CPU time | 4.87 seconds |
| Started | Aug 28 10:53:54 PM UTC 24 |
| Finished | Aug 28 10:54:00 PM UTC 24 |
| Peak memory | 232064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208382749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4208382749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.4009622982 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 798791054 ps |
| CPU time | 16.14 seconds |
| Started | Aug 28 10:54:23 PM UTC 24 |
| Finished | Aug 28 10:54:42 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009622982 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4009622982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.2126143325 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 57182983 ps |
| CPU time | 3.84 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:10 PM UTC 24 |
| Peak memory | 220000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126143325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2126143325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.515716276 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 10498289872 ps |
| CPU time | 83.18 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:56:34 PM UTC 24 |
| Peak memory | 226208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515716276 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.515716276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.4179763976 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1191633814 ps |
| CPU time | 7.03 seconds |
| Started | Aug 29 12:11:01 AM UTC 24 |
| Finished | Aug 29 12:11:09 AM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179763976 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.4179763976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.245084426 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 333065721 ps |
| CPU time | 5.27 seconds |
| Started | Aug 29 12:10:08 AM UTC 24 |
| Finished | Aug 29 12:10:15 AM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245084426 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.245084426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.2640980646 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 198995707 ps |
| CPU time | 3.57 seconds |
| Started | Aug 29 12:10:20 AM UTC 24 |
| Finished | Aug 29 12:10:25 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640980646 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.2640980646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.1339815506 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4500441367 ps |
| CPU time | 18.81 seconds |
| Started | Aug 28 10:51:05 PM UTC 24 |
| Finished | Aug 28 10:51:25 PM UTC 24 |
| Peak memory | 254572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339815506 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1339815506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.506926322 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 139238287 ps |
| CPU time | 6.66 seconds |
| Started | Aug 28 10:53:30 PM UTC 24 |
| Finished | Aug 28 10:53:38 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506926322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.506926322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.3868213193 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 43321792 ps |
| CPU time | 2.17 seconds |
| Started | Aug 28 10:53:51 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868213193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3868213193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.2250666137 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 85655793 ps |
| CPU time | 2.92 seconds |
| Started | Aug 28 10:50:54 PM UTC 24 |
| Finished | Aug 28 10:51:08 PM UTC 24 |
| Peak memory | 230568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250666137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2250666137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.2125677901 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 377962064 ps |
| CPU time | 3.01 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:03 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125677901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2125677901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.598427710 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 479925441 ps |
| CPU time | 11.84 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:22 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598427710 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.598427710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.979933597 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 109293039 ps |
| CPU time | 4.99 seconds |
| Started | Aug 28 10:52:01 PM UTC 24 |
| Finished | Aug 28 10:52:07 PM UTC 24 |
| Peak memory | 226192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979933597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.979933597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.1901488194 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 893046850 ps |
| CPU time | 8.3 seconds |
| Started | Aug 28 10:52:07 PM UTC 24 |
| Finished | Aug 28 10:52:17 PM UTC 24 |
| Peak memory | 230244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901488194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1901488194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.2249638097 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 823081443 ps |
| CPU time | 50.79 seconds |
| Started | Aug 28 10:52:30 PM UTC 24 |
| Finished | Aug 28 10:53:23 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249638097 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2249638097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.2188648460 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 232598899 ps |
| CPU time | 4.21 seconds |
| Started | Aug 28 10:52:32 PM UTC 24 |
| Finished | Aug 28 10:52:37 PM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188648460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2188648460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.26451941 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 512720134 ps |
| CPU time | 3.39 seconds |
| Started | Aug 28 10:52:40 PM UTC 24 |
| Finished | Aug 28 10:52:45 PM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26451941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.26451941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.2512116781 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 411955600 ps |
| CPU time | 6.3 seconds |
| Started | Aug 28 10:53:02 PM UTC 24 |
| Finished | Aug 28 10:53:10 PM UTC 24 |
| Peak memory | 232536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512116781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2512116781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.1204219361 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 63218121 ps |
| CPU time | 4.7 seconds |
| Started | Aug 28 10:53:06 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204219361 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1204219361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.3681961469 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4133950607 ps |
| CPU time | 27.92 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:53:49 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681961469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3681961469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all_with_rand_reset.1108669599 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 554646791 ps |
| CPU time | 21.67 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:53:43 PM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1108669599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymg r_stress_all_with_rand_reset.1108669599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.2979358410 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 79917236 ps |
| CPU time | 4.17 seconds |
| Started | Aug 28 10:53:43 PM UTC 24 |
| Finished | Aug 28 10:53:48 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979358410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2979358410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.1914785668 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 83754585 ps |
| CPU time | 2.98 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:46 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914785668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1914785668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.458976222 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 162354680 ps |
| CPU time | 4.37 seconds |
| Started | Aug 28 10:53:46 PM UTC 24 |
| Finished | Aug 28 10:53:52 PM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458976222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.458976222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.721306883 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 107187785 ps |
| CPU time | 3.95 seconds |
| Started | Aug 28 10:54:13 PM UTC 24 |
| Finished | Aug 28 10:54:19 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721306883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.721306883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.3118515374 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 83221614 ps |
| CPU time | 3.65 seconds |
| Started | Aug 28 10:54:27 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 232848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118515374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3118515374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.2094858246 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 537547810 ps |
| CPU time | 3.32 seconds |
| Started | Aug 28 10:54:45 PM UTC 24 |
| Finished | Aug 28 10:55:07 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094858246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2094858246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.842799337 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 153892106 ps |
| CPU time | 4.15 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:10 PM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842799337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.842799337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.2756571237 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 76632207 ps |
| CPU time | 5.77 seconds |
| Started | Aug 28 10:51:49 PM UTC 24 |
| Finished | Aug 28 10:51:56 PM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756571237 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2756571237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.3316538536 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 443559801 ps |
| CPU time | 4.4 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:20 PM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316538536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3316538536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.1281349898 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 480214404 ps |
| CPU time | 5.25 seconds |
| Started | Aug 29 12:09:46 AM UTC 24 |
| Finished | Aug 29 12:09:53 AM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281349898 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1281349898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.133872799 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 320333985 ps |
| CPU time | 16.93 seconds |
| Started | Aug 29 12:09:46 AM UTC 24 |
| Finished | Aug 29 12:10:04 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133872799 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.133872799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1538446005 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 210708058 ps |
| CPU time | 1.81 seconds |
| Started | Aug 29 12:09:44 AM UTC 24 |
| Finished | Aug 29 12:09:47 AM UTC 24 |
| Peak memory | 213656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538446005 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1538446005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3997877984 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 108804446 ps |
| CPU time | 1.61 seconds |
| Started | Aug 29 12:09:47 AM UTC 24 |
| Finished | Aug 29 12:09:50 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3997877984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w ith_rand_reset.3997877984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.2267518116 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 30407928 ps |
| CPU time | 1.57 seconds |
| Started | Aug 29 12:09:46 AM UTC 24 |
| Finished | Aug 29 12:09:49 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267518116 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2267518116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.789916417 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 9236902 ps |
| CPU time | 1.16 seconds |
| Started | Aug 29 12:09:44 AM UTC 24 |
| Finished | Aug 29 12:09:46 AM UTC 24 |
| Peak memory | 214864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789916417 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.789916417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2428461468 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 45828049 ps |
| CPU time | 3.13 seconds |
| Started | Aug 29 12:09:46 AM UTC 24 |
| Finished | Aug 29 12:09:50 AM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428461468 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.2428461468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3848114291 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 713175791 ps |
| CPU time | 5.68 seconds |
| Started | Aug 29 12:09:43 AM UTC 24 |
| Finished | Aug 29 12:09:49 AM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848114291 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.3848114291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.3866281689 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 774292521 ps |
| CPU time | 3.38 seconds |
| Started | Aug 29 12:09:43 AM UTC 24 |
| Finished | Aug 29 12:09:47 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866281689 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3866281689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.2798730324 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 470383475 ps |
| CPU time | 12.01 seconds |
| Started | Aug 29 12:09:52 AM UTC 24 |
| Finished | Aug 29 12:10:05 AM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798730324 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2798730324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2455974350 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 586665846 ps |
| CPU time | 20.05 seconds |
| Started | Aug 29 12:09:52 AM UTC 24 |
| Finished | Aug 29 12:10:13 AM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455974350 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2455974350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3997676806 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 57029422 ps |
| CPU time | 1.18 seconds |
| Started | Aug 29 12:09:51 AM UTC 24 |
| Finished | Aug 29 12:09:53 AM UTC 24 |
| Peak memory | 213656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997676806 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3997676806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3503215185 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 122042987 ps |
| CPU time | 2.51 seconds |
| Started | Aug 29 12:09:53 AM UTC 24 |
| Finished | Aug 29 12:09:57 AM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3503215185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.3503215185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.1248730657 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 78326190 ps |
| CPU time | 1.52 seconds |
| Started | Aug 29 12:09:51 AM UTC 24 |
| Finished | Aug 29 12:09:53 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248730657 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1248730657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.42165026 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 14298878 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:09:50 AM UTC 24 |
| Finished | Aug 29 12:09:52 AM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42165026 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.42165026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2730206159 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 38860467 ps |
| CPU time | 2.1 seconds |
| Started | Aug 29 12:09:52 AM UTC 24 |
| Finished | Aug 29 12:09:55 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730206159 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.2730206159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4190874985 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1783588735 ps |
| CPU time | 12.05 seconds |
| Started | Aug 29 12:09:48 AM UTC 24 |
| Finished | Aug 29 12:10:01 AM UTC 24 |
| Peak memory | 232612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190874985 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.4190874985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.3752988508 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 105797028 ps |
| CPU time | 5.15 seconds |
| Started | Aug 29 12:09:48 AM UTC 24 |
| Finished | Aug 29 12:09:54 AM UTC 24 |
| Peak memory | 226524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752988508 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3752988508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.1315979956 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 453080089 ps |
| CPU time | 7.94 seconds |
| Started | Aug 29 12:09:50 AM UTC 24 |
| Finished | Aug 29 12:09:59 AM UTC 24 |
| Peak memory | 226240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315979956 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.1315979956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.894901596 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 27224024 ps |
| CPU time | 1.81 seconds |
| Started | Aug 29 12:10:36 AM UTC 24 |
| Finished | Aug 29 12:10:39 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=894901596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_w ith_rand_reset.894901596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.3351229536 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 86806400 ps |
| CPU time | 1.6 seconds |
| Started | Aug 29 12:10:35 AM UTC 24 |
| Finished | Aug 29 12:10:37 AM UTC 24 |
| Peak memory | 213184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351229536 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3351229536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.2198627357 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 7629750 ps |
| CPU time | 1.12 seconds |
| Started | Aug 29 12:10:35 AM UTC 24 |
| Finished | Aug 29 12:10:37 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198627357 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2198627357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2550254045 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 123903634 ps |
| CPU time | 1.53 seconds |
| Started | Aug 29 12:10:35 AM UTC 24 |
| Finished | Aug 29 12:10:37 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550254045 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.2550254045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.21533412 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 105227435 ps |
| CPU time | 3 seconds |
| Started | Aug 29 12:10:32 AM UTC 24 |
| Finished | Aug 29 12:10:36 AM UTC 24 |
| Peak memory | 226576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21533412 -assert nopostproc +UVM_T ESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.21533412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3815494272 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 116443299 ps |
| CPU time | 6.59 seconds |
| Started | Aug 29 12:10:32 AM UTC 24 |
| Finished | Aug 29 12:10:40 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815494272 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.3815494272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.3271505827 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 444985281 ps |
| CPU time | 5.36 seconds |
| Started | Aug 29 12:10:34 AM UTC 24 |
| Finished | Aug 29 12:10:41 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271505827 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3271505827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1157491439 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 112622005 ps |
| CPU time | 4.54 seconds |
| Started | Aug 29 12:10:34 AM UTC 24 |
| Finished | Aug 29 12:10:40 AM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157491439 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.1157491439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2758876442 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 30391784 ps |
| CPU time | 1.97 seconds |
| Started | Aug 29 12:10:39 AM UTC 24 |
| Finished | Aug 29 12:10:42 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2758876442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_ with_rand_reset.2758876442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.2201881832 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 23268311 ps |
| CPU time | 1.44 seconds |
| Started | Aug 29 12:10:37 AM UTC 24 |
| Finished | Aug 29 12:10:40 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201881832 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2201881832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.157001667 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 30122217 ps |
| CPU time | 0.93 seconds |
| Started | Aug 29 12:10:37 AM UTC 24 |
| Finished | Aug 29 12:10:39 AM UTC 24 |
| Peak memory | 212372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157001667 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.157001667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.14457556 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 24759279 ps |
| CPU time | 2.18 seconds |
| Started | Aug 29 12:10:39 AM UTC 24 |
| Finished | Aug 29 12:10:42 AM UTC 24 |
| Peak memory | 216236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14457556 -assert nopostproc +UV M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.14457556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1542265682 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 59066357 ps |
| CPU time | 1.7 seconds |
| Started | Aug 29 12:10:36 AM UTC 24 |
| Finished | Aug 29 12:10:39 AM UTC 24 |
| Peak memory | 223956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542265682 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.1542265682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.698933372 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 145438560 ps |
| CPU time | 4.96 seconds |
| Started | Aug 29 12:10:37 AM UTC 24 |
| Finished | Aug 29 12:10:43 AM UTC 24 |
| Peak memory | 232556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698933372 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.698933372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.1845778703 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 65767049 ps |
| CPU time | 4.34 seconds |
| Started | Aug 29 12:10:37 AM UTC 24 |
| Finished | Aug 29 12:10:43 AM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845778703 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1845778703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4174771464 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 122905871 ps |
| CPU time | 3.73 seconds |
| Started | Aug 29 12:10:42 AM UTC 24 |
| Finished | Aug 29 12:10:47 AM UTC 24 |
| Peak memory | 232780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4174771464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_ with_rand_reset.4174771464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.3804010926 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 168250258 ps |
| CPU time | 1.45 seconds |
| Started | Aug 29 12:10:41 AM UTC 24 |
| Finished | Aug 29 12:10:43 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804010926 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3804010926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.3928909092 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 11244070 ps |
| CPU time | 1.16 seconds |
| Started | Aug 29 12:10:40 AM UTC 24 |
| Finished | Aug 29 12:10:43 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928909092 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3928909092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3101340869 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 175510113 ps |
| CPU time | 3.4 seconds |
| Started | Aug 29 12:10:41 AM UTC 24 |
| Finished | Aug 29 12:10:45 AM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101340869 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.3101340869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3774405175 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 572783211 ps |
| CPU time | 5.68 seconds |
| Started | Aug 29 12:10:39 AM UTC 24 |
| Finished | Aug 29 12:10:46 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774405175 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.3774405175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2895471690 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2073371412 ps |
| CPU time | 11.61 seconds |
| Started | Aug 29 12:10:40 AM UTC 24 |
| Finished | Aug 29 12:10:53 AM UTC 24 |
| Peak memory | 232652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895471690 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.2895471690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.3425881219 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 160009149 ps |
| CPU time | 2.88 seconds |
| Started | Aug 29 12:10:40 AM UTC 24 |
| Finished | Aug 29 12:10:44 AM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425881219 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3425881219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.2220861637 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 102776355 ps |
| CPU time | 6.37 seconds |
| Started | Aug 29 12:10:40 AM UTC 24 |
| Finished | Aug 29 12:10:48 AM UTC 24 |
| Peak memory | 226348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220861637 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.2220861637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2138309370 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 92355358 ps |
| CPU time | 1.85 seconds |
| Started | Aug 29 12:10:45 AM UTC 24 |
| Finished | Aug 29 12:10:48 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2138309370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.2138309370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.2480596373 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 13633990 ps |
| CPU time | 1.46 seconds |
| Started | Aug 29 12:10:44 AM UTC 24 |
| Finished | Aug 29 12:10:46 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480596373 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2480596373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.58929367 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 27633936 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 12:10:43 AM UTC 24 |
| Finished | Aug 29 12:10:46 AM UTC 24 |
| Peak memory | 213532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58929367 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.58929367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1991025165 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 42288067 ps |
| CPU time | 2.92 seconds |
| Started | Aug 29 12:10:45 AM UTC 24 |
| Finished | Aug 29 12:10:49 AM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991025165 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.1991025165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1653216540 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 83138659 ps |
| CPU time | 2.23 seconds |
| Started | Aug 29 12:10:42 AM UTC 24 |
| Finished | Aug 29 12:10:45 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653216540 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.1653216540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2163749550 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 1115944541 ps |
| CPU time | 7.49 seconds |
| Started | Aug 29 12:10:42 AM UTC 24 |
| Finished | Aug 29 12:10:50 AM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163749550 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.2163749550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.2840078686 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 130710374 ps |
| CPU time | 4.33 seconds |
| Started | Aug 29 12:10:43 AM UTC 24 |
| Finished | Aug 29 12:10:49 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840078686 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2840078686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.512687512 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 168675742 ps |
| CPU time | 5.51 seconds |
| Started | Aug 29 12:10:43 AM UTC 24 |
| Finished | Aug 29 12:10:50 AM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512687512 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.512687512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4154489036 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 46465279 ps |
| CPU time | 2.8 seconds |
| Started | Aug 29 12:10:48 AM UTC 24 |
| Finished | Aug 29 12:10:52 AM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4154489036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_ with_rand_reset.4154489036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.4024712017 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 39294307 ps |
| CPU time | 1.22 seconds |
| Started | Aug 29 12:10:47 AM UTC 24 |
| Finished | Aug 29 12:10:49 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024712017 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4024712017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.2097202373 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 31862753 ps |
| CPU time | 0.96 seconds |
| Started | Aug 29 12:10:47 AM UTC 24 |
| Finished | Aug 29 12:10:49 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097202373 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2097202373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.414303443 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 123710138 ps |
| CPU time | 5.24 seconds |
| Started | Aug 29 12:10:48 AM UTC 24 |
| Finished | Aug 29 12:10:54 AM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414303443 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.414303443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1233722611 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 331420980 ps |
| CPU time | 3.3 seconds |
| Started | Aug 29 12:10:45 AM UTC 24 |
| Finished | Aug 29 12:10:50 AM UTC 24 |
| Peak memory | 226684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233722611 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.1233722611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3068896672 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 303958988 ps |
| CPU time | 4.74 seconds |
| Started | Aug 29 12:10:45 AM UTC 24 |
| Finished | Aug 29 12:10:51 AM UTC 24 |
| Peak memory | 226540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068896672 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.3068896672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.572915850 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 53360323 ps |
| CPU time | 3.57 seconds |
| Started | Aug 29 12:10:46 AM UTC 24 |
| Finished | Aug 29 12:10:51 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572915850 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.572915850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2855661458 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 126765936 ps |
| CPU time | 1.88 seconds |
| Started | Aug 29 12:10:52 AM UTC 24 |
| Finished | Aug 29 12:10:55 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2855661458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_ with_rand_reset.2855661458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1651915019 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 30086618 ps |
| CPU time | 1.22 seconds |
| Started | Aug 29 12:10:51 AM UTC 24 |
| Finished | Aug 29 12:10:53 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651915019 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1651915019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.1433133178 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 22226881 ps |
| CPU time | 1.23 seconds |
| Started | Aug 29 12:10:51 AM UTC 24 |
| Finished | Aug 29 12:10:53 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433133178 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1433133178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.839447781 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 120435911 ps |
| CPU time | 2.58 seconds |
| Started | Aug 29 12:10:51 AM UTC 24 |
| Finished | Aug 29 12:10:54 AM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839447781 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.839447781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2803015329 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 123282026 ps |
| CPU time | 5.14 seconds |
| Started | Aug 29 12:10:49 AM UTC 24 |
| Finished | Aug 29 12:10:56 AM UTC 24 |
| Peak memory | 226680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803015329 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.2803015329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2980926485 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 552569384 ps |
| CPU time | 7.78 seconds |
| Started | Aug 29 12:10:49 AM UTC 24 |
| Finished | Aug 29 12:10:58 AM UTC 24 |
| Peak memory | 232620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980926485 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.2980926485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.1867542152 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 1208486656 ps |
| CPU time | 3.86 seconds |
| Started | Aug 29 12:10:49 AM UTC 24 |
| Finished | Aug 29 12:10:54 AM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867542152 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1867542152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.786761852 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 318248682 ps |
| CPU time | 9.68 seconds |
| Started | Aug 29 12:10:51 AM UTC 24 |
| Finished | Aug 29 12:11:01 AM UTC 24 |
| Peak memory | 226348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786761852 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.786761852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2773270491 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 95911880 ps |
| CPU time | 3.14 seconds |
| Started | Aug 29 12:10:54 AM UTC 24 |
| Finished | Aug 29 12:10:58 AM UTC 24 |
| Peak memory | 226296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2773270491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.2773270491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1227321875 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 20051784 ps |
| CPU time | 1.15 seconds |
| Started | Aug 29 12:10:53 AM UTC 24 |
| Finished | Aug 29 12:10:55 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227321875 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1227321875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.3619077821 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 39784539 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 12:10:53 AM UTC 24 |
| Finished | Aug 29 12:10:55 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619077821 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3619077821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2950384894 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 75951664 ps |
| CPU time | 3.19 seconds |
| Started | Aug 29 12:10:54 AM UTC 24 |
| Finished | Aug 29 12:10:58 AM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950384894 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.2950384894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.314064593 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 47870513 ps |
| CPU time | 2.26 seconds |
| Started | Aug 29 12:10:52 AM UTC 24 |
| Finished | Aug 29 12:10:56 AM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314064593 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.314064593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4196211372 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 736576299 ps |
| CPU time | 13.82 seconds |
| Started | Aug 29 12:10:53 AM UTC 24 |
| Finished | Aug 29 12:11:08 AM UTC 24 |
| Peak memory | 232676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196211372 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.4196211372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.2469613594 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 241779234 ps |
| CPU time | 2.25 seconds |
| Started | Aug 29 12:10:53 AM UTC 24 |
| Finished | Aug 29 12:10:56 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469613594 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2469613594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1884849913 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 411260845 ps |
| CPU time | 12.49 seconds |
| Started | Aug 29 12:10:53 AM UTC 24 |
| Finished | Aug 29 12:11:06 AM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884849913 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.1884849913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3366300157 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 178991283 ps |
| CPU time | 2.45 seconds |
| Started | Aug 29 12:10:56 AM UTC 24 |
| Finished | Aug 29 12:11:00 AM UTC 24 |
| Peak memory | 226336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3366300157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_ with_rand_reset.3366300157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.3859891801 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 24524767 ps |
| CPU time | 1.51 seconds |
| Started | Aug 29 12:10:56 AM UTC 24 |
| Finished | Aug 29 12:10:59 AM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859891801 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3859891801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.563150057 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 63366201 ps |
| CPU time | 1.1 seconds |
| Started | Aug 29 12:10:56 AM UTC 24 |
| Finished | Aug 29 12:10:58 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563150057 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.563150057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.671483448 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 34591487 ps |
| CPU time | 3.29 seconds |
| Started | Aug 29 12:10:56 AM UTC 24 |
| Finished | Aug 29 12:11:01 AM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671483448 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.671483448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.437938374 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 1049978819 ps |
| CPU time | 4.51 seconds |
| Started | Aug 29 12:10:54 AM UTC 24 |
| Finished | Aug 29 12:11:00 AM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437938374 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.437938374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1052895271 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 337613271 ps |
| CPU time | 7.96 seconds |
| Started | Aug 29 12:10:54 AM UTC 24 |
| Finished | Aug 29 12:11:03 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052895271 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.1052895271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.4225071826 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 118039186 ps |
| CPU time | 2.62 seconds |
| Started | Aug 29 12:10:54 AM UTC 24 |
| Finished | Aug 29 12:10:58 AM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225071826 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4225071826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.132351847 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 98847250 ps |
| CPU time | 3.51 seconds |
| Started | Aug 29 12:10:56 AM UTC 24 |
| Finished | Aug 29 12:11:01 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132351847 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.132351847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3356129195 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 112143644 ps |
| CPU time | 1.58 seconds |
| Started | Aug 29 12:11:00 AM UTC 24 |
| Finished | Aug 29 12:11:02 AM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3356129195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.3356129195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.639744519 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 19303245 ps |
| CPU time | 1.52 seconds |
| Started | Aug 29 12:10:59 AM UTC 24 |
| Finished | Aug 29 12:11:02 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639744519 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.639744519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.1900152882 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 37643111 ps |
| CPU time | 1.01 seconds |
| Started | Aug 29 12:10:59 AM UTC 24 |
| Finished | Aug 29 12:11:01 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900152882 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1900152882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3362850051 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 56873935 ps |
| CPU time | 2.06 seconds |
| Started | Aug 29 12:11:00 AM UTC 24 |
| Finished | Aug 29 12:11:03 AM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362850051 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.3362850051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2119564312 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 227566823 ps |
| CPU time | 6.05 seconds |
| Started | Aug 29 12:10:56 AM UTC 24 |
| Finished | Aug 29 12:11:03 AM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119564312 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.2119564312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4156043538 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 275551978 ps |
| CPU time | 4.83 seconds |
| Started | Aug 29 12:10:58 AM UTC 24 |
| Finished | Aug 29 12:11:04 AM UTC 24 |
| Peak memory | 232920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156043538 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.4156043538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.2898670318 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 73251024 ps |
| CPU time | 3.41 seconds |
| Started | Aug 29 12:10:58 AM UTC 24 |
| Finished | Aug 29 12:11:02 AM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898670318 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2898670318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.3784358747 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 142283433 ps |
| CPU time | 4.66 seconds |
| Started | Aug 29 12:10:58 AM UTC 24 |
| Finished | Aug 29 12:11:03 AM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784358747 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.3784358747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1650042393 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 179857715 ps |
| CPU time | 2.74 seconds |
| Started | Aug 29 12:11:03 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1650042393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.1650042393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.1485199742 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 26365265 ps |
| CPU time | 1.57 seconds |
| Started | Aug 29 12:11:03 AM UTC 24 |
| Finished | Aug 29 12:11:05 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485199742 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1485199742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.824437181 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 94448763 ps |
| CPU time | 1.24 seconds |
| Started | Aug 29 12:11:01 AM UTC 24 |
| Finished | Aug 29 12:11:03 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824437181 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.824437181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.635083844 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 118476493 ps |
| CPU time | 5.51 seconds |
| Started | Aug 29 12:11:03 AM UTC 24 |
| Finished | Aug 29 12:11:09 AM UTC 24 |
| Peak memory | 216012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635083844 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.635083844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1318451289 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 165709522 ps |
| CPU time | 2.52 seconds |
| Started | Aug 29 12:11:00 AM UTC 24 |
| Finished | Aug 29 12:11:03 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318451289 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.1318451289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2838104397 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2037551565 ps |
| CPU time | 9.98 seconds |
| Started | Aug 29 12:11:00 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 226676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838104397 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.2838104397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.894410705 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 356931421 ps |
| CPU time | 4.75 seconds |
| Started | Aug 29 12:11:01 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 228324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894410705 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.894410705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.1471711306 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 770324541 ps |
| CPU time | 8.8 seconds |
| Started | Aug 29 12:09:58 AM UTC 24 |
| Finished | Aug 29 12:10:08 AM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471711306 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1471711306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.734633760 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2653491864 ps |
| CPU time | 21.54 seconds |
| Started | Aug 29 12:09:58 AM UTC 24 |
| Finished | Aug 29 12:10:21 AM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734633760 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.734633760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3936093046 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 103588249 ps |
| CPU time | 1.44 seconds |
| Started | Aug 29 12:09:56 AM UTC 24 |
| Finished | Aug 29 12:09:58 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936093046 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3936093046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4057185389 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 15803324 ps |
| CPU time | 1.46 seconds |
| Started | Aug 29 12:09:59 AM UTC 24 |
| Finished | Aug 29 12:10:02 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4057185389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w ith_rand_reset.4057185389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.1344501799 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 92800089 ps |
| CPU time | 1.89 seconds |
| Started | Aug 29 12:09:58 AM UTC 24 |
| Finished | Aug 29 12:10:01 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344501799 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1344501799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.2644844732 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 15042810 ps |
| CPU time | 1.08 seconds |
| Started | Aug 29 12:09:55 AM UTC 24 |
| Finished | Aug 29 12:09:57 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644844732 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2644844732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.923865331 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 118299968 ps |
| CPU time | 3.93 seconds |
| Started | Aug 29 12:09:59 AM UTC 24 |
| Finished | Aug 29 12:10:04 AM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923865331 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.923865331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2504691284 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 1602234516 ps |
| CPU time | 18.42 seconds |
| Started | Aug 29 12:09:53 AM UTC 24 |
| Finished | Aug 29 12:10:13 AM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504691284 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.2504691284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.3945547564 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 130820162 ps |
| CPU time | 2.58 seconds |
| Started | Aug 29 12:09:54 AM UTC 24 |
| Finished | Aug 29 12:09:57 AM UTC 24 |
| Peak memory | 226340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945547564 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3945547564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.231176958 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1025870469 ps |
| CPU time | 6.66 seconds |
| Started | Aug 29 12:09:55 AM UTC 24 |
| Finished | Aug 29 12:10:02 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231176958 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.231176958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.2307747848 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 16448557 ps |
| CPU time | 0.96 seconds |
| Started | Aug 29 12:11:03 AM UTC 24 |
| Finished | Aug 29 12:11:05 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307747848 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2307747848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.1053992161 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 11242838 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:11:03 AM UTC 24 |
| Finished | Aug 29 12:11:05 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053992161 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1053992161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.536653236 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 22681325 ps |
| CPU time | 1.16 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536653236 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.536653236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.359816682 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 10507494 ps |
| CPU time | 1.08 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 213344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359816682 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.359816682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.3655532743 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 13085346 ps |
| CPU time | 1.08 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655532743 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3655532743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.960926233 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 9146983 ps |
| CPU time | 1.14 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960926233 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.960926233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.2778010913 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 10638250 ps |
| CPU time | 1.14 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778010913 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2778010913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.3025452188 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 50017565 ps |
| CPU time | 1.12 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025452188 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3025452188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.590007848 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 46604543 ps |
| CPU time | 1.24 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 213564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590007848 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.590007848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.3374639135 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 22556378 ps |
| CPU time | 1.14 seconds |
| Started | Aug 29 12:11:05 AM UTC 24 |
| Finished | Aug 29 12:11:07 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374639135 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3374639135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.2189185097 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 732724195 ps |
| CPU time | 7.05 seconds |
| Started | Aug 29 12:10:06 AM UTC 24 |
| Finished | Aug 29 12:10:14 AM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189185097 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2189185097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2003102567 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 903814352 ps |
| CPU time | 9.61 seconds |
| Started | Aug 29 12:10:05 AM UTC 24 |
| Finished | Aug 29 12:10:15 AM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003102567 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2003102567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4162307157 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 33054716 ps |
| CPU time | 1.73 seconds |
| Started | Aug 29 12:10:04 AM UTC 24 |
| Finished | Aug 29 12:10:06 AM UTC 24 |
| Peak memory | 213656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162307157 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4162307157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2869842777 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 45252046 ps |
| CPU time | 1.79 seconds |
| Started | Aug 29 12:10:07 AM UTC 24 |
| Finished | Aug 29 12:10:10 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2869842777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w ith_rand_reset.2869842777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.4093599844 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 61765569 ps |
| CPU time | 1.66 seconds |
| Started | Aug 29 12:10:05 AM UTC 24 |
| Finished | Aug 29 12:10:07 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093599844 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4093599844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.166141901 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 37052870 ps |
| CPU time | 1.17 seconds |
| Started | Aug 29 12:10:04 AM UTC 24 |
| Finished | Aug 29 12:10:06 AM UTC 24 |
| Peak memory | 213576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166141901 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.166141901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1333455971 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 47547439 ps |
| CPU time | 1.95 seconds |
| Started | Aug 29 12:10:06 AM UTC 24 |
| Finished | Aug 29 12:10:09 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333455971 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.1333455971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2110143010 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 58721345 ps |
| CPU time | 1.78 seconds |
| Started | Aug 29 12:10:00 AM UTC 24 |
| Finished | Aug 29 12:10:03 AM UTC 24 |
| Peak memory | 226736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110143010 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.2110143010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.936381753 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 89230634 ps |
| CPU time | 6.18 seconds |
| Started | Aug 29 12:10:01 AM UTC 24 |
| Finished | Aug 29 12:10:09 AM UTC 24 |
| Peak memory | 226288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936381753 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.936381753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.1382920481 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 55617312 ps |
| CPU time | 3.03 seconds |
| Started | Aug 29 12:10:01 AM UTC 24 |
| Finished | Aug 29 12:10:05 AM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382920481 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1382920481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.3133498685 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 11453262 ps |
| CPU time | 1.21 seconds |
| Started | Aug 29 12:11:07 AM UTC 24 |
| Finished | Aug 29 12:11:09 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133498685 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3133498685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1131201223 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 13654888 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:11:07 AM UTC 24 |
| Finished | Aug 29 12:11:09 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131201223 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1131201223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1492998316 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 19942491 ps |
| CPU time | 1.09 seconds |
| Started | Aug 29 12:11:07 AM UTC 24 |
| Finished | Aug 29 12:11:09 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492998316 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1492998316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.3694120492 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 52346707 ps |
| CPU time | 0.98 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694120492 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3694120492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.2383386293 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 27994308 ps |
| CPU time | 0.93 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383386293 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2383386293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.2089642682 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 42665199 ps |
| CPU time | 1.21 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089642682 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2089642682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.1909890535 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 13040107 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909890535 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1909890535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.3905024338 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 48000727 ps |
| CPU time | 1.21 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905024338 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3905024338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.2928682978 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 16946162 ps |
| CPU time | 1.13 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928682978 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2928682978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.3991326089 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 49269052 ps |
| CPU time | 1 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991326089 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3991326089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.14593833 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 1823141860 ps |
| CPU time | 9.98 seconds |
| Started | Aug 29 12:10:12 AM UTC 24 |
| Finished | Aug 29 12:10:23 AM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14593833 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.14593833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3212302543 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 453171615 ps |
| CPU time | 11.75 seconds |
| Started | Aug 29 12:10:11 AM UTC 24 |
| Finished | Aug 29 12:10:24 AM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212302543 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3212302543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1829467719 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 115994648 ps |
| CPU time | 1.5 seconds |
| Started | Aug 29 12:10:10 AM UTC 24 |
| Finished | Aug 29 12:10:12 AM UTC 24 |
| Peak memory | 213656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829467719 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1829467719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2854171229 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 102564102 ps |
| CPU time | 2.43 seconds |
| Started | Aug 29 12:10:13 AM UTC 24 |
| Finished | Aug 29 12:10:16 AM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2854171229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w ith_rand_reset.2854171229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.3833275632 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 71299067 ps |
| CPU time | 1.61 seconds |
| Started | Aug 29 12:10:10 AM UTC 24 |
| Finished | Aug 29 12:10:12 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833275632 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3833275632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.3979941943 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 10906700 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 12:10:08 AM UTC 24 |
| Finished | Aug 29 12:10:10 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979941943 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3979941943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.327492154 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 56408830 ps |
| CPU time | 2.07 seconds |
| Started | Aug 29 12:10:13 AM UTC 24 |
| Finished | Aug 29 12:10:16 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327492154 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.327492154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.575756701 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 217212675 ps |
| CPU time | 6.27 seconds |
| Started | Aug 29 12:10:07 AM UTC 24 |
| Finished | Aug 29 12:10:14 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575756701 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.575756701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.393080874 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 319773776 ps |
| CPU time | 9.54 seconds |
| Started | Aug 29 12:10:08 AM UTC 24 |
| Finished | Aug 29 12:10:19 AM UTC 24 |
| Peak memory | 226796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393080874 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.393080874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.337113297 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 327389594 ps |
| CPU time | 7.5 seconds |
| Started | Aug 29 12:10:08 AM UTC 24 |
| Finished | Aug 29 12:10:17 AM UTC 24 |
| Peak memory | 228316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337113297 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.337113297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1496880211 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 34003005 ps |
| CPU time | 1 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496880211 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1496880211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.2597282938 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 11478293 ps |
| CPU time | 0.99 seconds |
| Started | Aug 29 12:11:09 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597282938 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2597282938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.1789512774 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 38424971 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:11:10 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789512774 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1789512774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.2431473918 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 33369430 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 12:11:10 AM UTC 24 |
| Finished | Aug 29 12:11:11 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431473918 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2431473918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.854313773 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 26158325 ps |
| CPU time | 1.17 seconds |
| Started | Aug 29 12:11:10 AM UTC 24 |
| Finished | Aug 29 12:11:12 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854313773 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.854313773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.4210486352 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 18619244 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:11:11 AM UTC 24 |
| Finished | Aug 29 12:11:13 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210486352 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4210486352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.3703153656 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 9073587 ps |
| CPU time | 1.06 seconds |
| Started | Aug 29 12:11:11 AM UTC 24 |
| Finished | Aug 29 12:11:13 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703153656 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3703153656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.198724523 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 10579249 ps |
| CPU time | 1.1 seconds |
| Started | Aug 29 12:11:11 AM UTC 24 |
| Finished | Aug 29 12:11:13 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198724523 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.198724523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.392008474 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 32240850 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:11:11 AM UTC 24 |
| Finished | Aug 29 12:11:13 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392008474 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.392008474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3055424065 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 45644548 ps |
| CPU time | 1.15 seconds |
| Started | Aug 29 12:11:11 AM UTC 24 |
| Finished | Aug 29 12:11:14 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055424065 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3055424065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1043032229 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 127611431 ps |
| CPU time | 2.09 seconds |
| Started | Aug 29 12:10:18 AM UTC 24 |
| Finished | Aug 29 12:10:21 AM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1043032229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w ith_rand_reset.1043032229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.2668351961 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 47261565 ps |
| CPU time | 1.47 seconds |
| Started | Aug 29 12:10:16 AM UTC 24 |
| Finished | Aug 29 12:10:19 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668351961 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2668351961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.2352477033 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 14234233 ps |
| CPU time | 1.11 seconds |
| Started | Aug 29 12:10:15 AM UTC 24 |
| Finished | Aug 29 12:10:17 AM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352477033 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2352477033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3732042279 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 21999702 ps |
| CPU time | 2.36 seconds |
| Started | Aug 29 12:10:17 AM UTC 24 |
| Finished | Aug 29 12:10:20 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732042279 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.3732042279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.460663951 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 99052116 ps |
| CPU time | 3.76 seconds |
| Started | Aug 29 12:10:14 AM UTC 24 |
| Finished | Aug 29 12:10:19 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460663951 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.460663951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3318904917 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 468703253 ps |
| CPU time | 18.26 seconds |
| Started | Aug 29 12:10:14 AM UTC 24 |
| Finished | Aug 29 12:10:34 AM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318904917 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.3318904917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.261769672 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 165533883 ps |
| CPU time | 7.5 seconds |
| Started | Aug 29 12:10:15 AM UTC 24 |
| Finished | Aug 29 12:10:24 AM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261769672 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.261769672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.2272124663 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 340517842 ps |
| CPU time | 4.42 seconds |
| Started | Aug 29 12:10:15 AM UTC 24 |
| Finished | Aug 29 12:10:21 AM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272124663 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.2272124663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2910909539 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 86980704 ps |
| CPU time | 1.41 seconds |
| Started | Aug 29 12:10:21 AM UTC 24 |
| Finished | Aug 29 12:10:24 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2910909539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w ith_rand_reset.2910909539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.3145779575 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 95547969 ps |
| CPU time | 1.92 seconds |
| Started | Aug 29 12:10:21 AM UTC 24 |
| Finished | Aug 29 12:10:24 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145779575 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3145779575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.1639692130 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 11393519 ps |
| CPU time | 1.16 seconds |
| Started | Aug 29 12:10:20 AM UTC 24 |
| Finished | Aug 29 12:10:22 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639692130 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1639692130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.27072744 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 20732798 ps |
| CPU time | 2.2 seconds |
| Started | Aug 29 12:10:21 AM UTC 24 |
| Finished | Aug 29 12:10:25 AM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27072744 -assert nopostproc +UV M_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.27072744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3833331959 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1019085347 ps |
| CPU time | 3.58 seconds |
| Started | Aug 29 12:10:18 AM UTC 24 |
| Finished | Aug 29 12:10:22 AM UTC 24 |
| Peak memory | 226768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833331959 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.3833331959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3115560330 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 91759836 ps |
| CPU time | 4.57 seconds |
| Started | Aug 29 12:10:19 AM UTC 24 |
| Finished | Aug 29 12:10:24 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115560330 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.3115560330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.1168957070 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 125582815 ps |
| CPU time | 5.14 seconds |
| Started | Aug 29 12:10:20 AM UTC 24 |
| Finished | Aug 29 12:10:26 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168957070 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1168957070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3813179922 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 734874486 ps |
| CPU time | 2.01 seconds |
| Started | Aug 29 12:10:25 AM UTC 24 |
| Finished | Aug 29 12:10:29 AM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3813179922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w ith_rand_reset.3813179922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.4052326101 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 62313204 ps |
| CPU time | 1.19 seconds |
| Started | Aug 29 12:10:25 AM UTC 24 |
| Finished | Aug 29 12:10:28 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052326101 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4052326101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.2146785126 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 18189656 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:10:25 AM UTC 24 |
| Finished | Aug 29 12:10:28 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146785126 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2146785126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.897685515 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 78411027 ps |
| CPU time | 1.92 seconds |
| Started | Aug 29 12:10:25 AM UTC 24 |
| Finished | Aug 29 12:10:29 AM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897685515 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.897685515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3191742240 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 443401604 ps |
| CPU time | 3.44 seconds |
| Started | Aug 29 12:10:21 AM UTC 24 |
| Finished | Aug 29 12:10:26 AM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191742240 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.3191742240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2021160249 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 78807308 ps |
| CPU time | 4.4 seconds |
| Started | Aug 29 12:10:23 AM UTC 24 |
| Finished | Aug 29 12:10:28 AM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021160249 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.2021160249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.2285579846 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 223040274 ps |
| CPU time | 2.6 seconds |
| Started | Aug 29 12:10:24 AM UTC 24 |
| Finished | Aug 29 12:10:28 AM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285579846 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2285579846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.653587593 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 74859517 ps |
| CPU time | 4.94 seconds |
| Started | Aug 29 12:10:24 AM UTC 24 |
| Finished | Aug 29 12:10:30 AM UTC 24 |
| Peak memory | 226204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653587593 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.653587593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.446514722 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 147821208 ps |
| CPU time | 3.73 seconds |
| Started | Aug 29 12:10:28 AM UTC 24 |
| Finished | Aug 29 12:10:33 AM UTC 24 |
| Peak memory | 226216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=446514722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_wi th_rand_reset.446514722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.408278635 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 15762280 ps |
| CPU time | 1.27 seconds |
| Started | Aug 29 12:10:27 AM UTC 24 |
| Finished | Aug 29 12:10:29 AM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408278635 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.408278635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.2349749919 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 120875165 ps |
| CPU time | 1.2 seconds |
| Started | Aug 29 12:10:27 AM UTC 24 |
| Finished | Aug 29 12:10:29 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349749919 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2349749919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1779317285 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 23559848 ps |
| CPU time | 2.19 seconds |
| Started | Aug 29 12:10:28 AM UTC 24 |
| Finished | Aug 29 12:10:31 AM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779317285 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.1779317285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.260571787 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 318958101 ps |
| CPU time | 4.57 seconds |
| Started | Aug 29 12:10:25 AM UTC 24 |
| Finished | Aug 29 12:10:31 AM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260571787 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.260571787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.645919017 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 1305025099 ps |
| CPU time | 11.83 seconds |
| Started | Aug 29 12:10:25 AM UTC 24 |
| Finished | Aug 29 12:10:39 AM UTC 24 |
| Peak memory | 226544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645919017 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.645919017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.958218046 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 56379725 ps |
| CPU time | 4.34 seconds |
| Started | Aug 29 12:10:26 AM UTC 24 |
| Finished | Aug 29 12:10:31 AM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958218046 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.958218046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4051956032 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 40764762 ps |
| CPU time | 2.52 seconds |
| Started | Aug 29 12:10:32 AM UTC 24 |
| Finished | Aug 29 12:10:36 AM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4051956032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w ith_rand_reset.4051956032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.4064652586 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 47252042 ps |
| CPU time | 1.57 seconds |
| Started | Aug 29 12:10:31 AM UTC 24 |
| Finished | Aug 29 12:10:33 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064652586 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4064652586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.3800298861 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 9095198 ps |
| CPU time | 1.07 seconds |
| Started | Aug 29 12:10:31 AM UTC 24 |
| Finished | Aug 29 12:10:33 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800298861 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3800298861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1883556 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 339153667 ps |
| CPU time | 4.64 seconds |
| Started | Aug 29 12:10:31 AM UTC 24 |
| Finished | Aug 29 12:10:37 AM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883556 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.1883556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3616010832 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 74339537 ps |
| CPU time | 3.09 seconds |
| Started | Aug 29 12:10:29 AM UTC 24 |
| Finished | Aug 29 12:10:34 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616010832 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.3616010832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1225961550 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 813745295 ps |
| CPU time | 6.15 seconds |
| Started | Aug 29 12:10:29 AM UTC 24 |
| Finished | Aug 29 12:10:37 AM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225961550 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.1225961550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.2388535628 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 565818574 ps |
| CPU time | 3.05 seconds |
| Started | Aug 29 12:10:29 AM UTC 24 |
| Finished | Aug 29 12:10:34 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388535628 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2388535628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.690924402 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 480282627 ps |
| CPU time | 7.58 seconds |
| Started | Aug 29 12:10:29 AM UTC 24 |
| Finished | Aug 29 12:10:39 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690924402 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.690924402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.468369156 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 962303272 ps |
| CPU time | 21.79 seconds |
| Started | Aug 28 10:50:54 PM UTC 24 |
| Finished | Aug 28 10:51:28 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468369156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.468369156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.2134722555 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 114484846 ps |
| CPU time | 2.91 seconds |
| Started | Aug 28 10:50:54 PM UTC 24 |
| Finished | Aug 28 10:51:09 PM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134722555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2134722555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_random.3613215667 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 378392950 ps |
| CPU time | 3.84 seconds |
| Started | Aug 28 10:50:53 PM UTC 24 |
| Finished | Aug 28 10:50:59 PM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613215667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3613215667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.1988275113 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 186941926 ps |
| CPU time | 5.39 seconds |
| Started | Aug 28 10:50:52 PM UTC 24 |
| Finished | Aug 28 10:51:05 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988275113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1988275113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.283474125 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 279588231 ps |
| CPU time | 3.45 seconds |
| Started | Aug 28 10:50:52 PM UTC 24 |
| Finished | Aug 28 10:51:04 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283474125 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.283474125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.2160725590 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 74185722 ps |
| CPU time | 3.3 seconds |
| Started | Aug 28 10:50:53 PM UTC 24 |
| Finished | Aug 28 10:51:09 PM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160725590 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2160725590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.2700230334 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 363925502 ps |
| CPU time | 2.74 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:10 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700230334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2700230334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.2297063942 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1292759886 ps |
| CPU time | 9.62 seconds |
| Started | Aug 28 10:50:52 PM UTC 24 |
| Finished | Aug 28 10:51:10 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297063942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2297063942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.254531572 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1490157029 ps |
| CPU time | 37.38 seconds |
| Started | Aug 28 10:50:54 PM UTC 24 |
| Finished | Aug 28 10:51:44 PM UTC 24 |
| Peak memory | 217940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254531572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.254531572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.3229469795 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 42602366 ps |
| CPU time | 1.01 seconds |
| Started | Aug 28 10:51:05 PM UTC 24 |
| Finished | Aug 28 10:51:07 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229469795 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3229469795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.3739288842 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 141598870 ps |
| CPU time | 4.72 seconds |
| Started | Aug 28 10:51:00 PM UTC 24 |
| Finished | Aug 28 10:51:16 PM UTC 24 |
| Peak memory | 231480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739288842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3739288842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.1945843262 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 992685227 ps |
| CPU time | 2.89 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:14 PM UTC 24 |
| Peak memory | 215932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945843262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1945843262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.3680282336 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7684881450 ps |
| CPU time | 41.32 seconds |
| Started | Aug 28 10:50:59 PM UTC 24 |
| Finished | Aug 28 10:51:52 PM UTC 24 |
| Peak memory | 230188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680282336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3680282336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.3654361891 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 91028411 ps |
| CPU time | 4.56 seconds |
| Started | Aug 28 10:50:59 PM UTC 24 |
| Finished | Aug 28 10:51:15 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654361891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3654361891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_random.3420654915 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1368569687 ps |
| CPU time | 14.07 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:25 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420654915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3420654915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.3118577455 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 221583773 ps |
| CPU time | 3.77 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:14 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118577455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3118577455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.2764872562 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 271561736 ps |
| CPU time | 9.21 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:20 PM UTC 24 |
| Peak memory | 217872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764872562 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2764872562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.475067137 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 619304817 ps |
| CPU time | 6.08 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:17 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475067137 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.475067137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.2981020683 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 71715106 ps |
| CPU time | 2.56 seconds |
| Started | Aug 28 10:51:00 PM UTC 24 |
| Finished | Aug 28 10:51:14 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981020683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2981020683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.2065585166 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 334060889 ps |
| CPU time | 5.95 seconds |
| Started | Aug 28 10:50:58 PM UTC 24 |
| Finished | Aug 28 10:51:13 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065585166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2065585166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.2640588112 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 169937822 ps |
| CPU time | 3.76 seconds |
| Started | Aug 28 10:51:04 PM UTC 24 |
| Finished | Aug 28 10:51:10 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640588112 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2640588112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.3487575922 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 183933699 ps |
| CPU time | 1.86 seconds |
| Started | Aug 28 10:51:04 PM UTC 24 |
| Finished | Aug 28 10:51:08 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487575922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3487575922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.3267605228 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 14867319 ps |
| CPU time | 1.21 seconds |
| Started | Aug 28 10:52:04 PM UTC 24 |
| Finished | Aug 28 10:52:06 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267605228 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3267605228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.241635586 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 53818797 ps |
| CPU time | 4.18 seconds |
| Started | Aug 28 10:52:01 PM UTC 24 |
| Finished | Aug 28 10:52:06 PM UTC 24 |
| Peak memory | 224352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241635586 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.241635586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.2317343949 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 76742326 ps |
| CPU time | 3.59 seconds |
| Started | Aug 28 10:52:02 PM UTC 24 |
| Finished | Aug 28 10:52:07 PM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317343949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2317343949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.1713588416 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 22908529 ps |
| CPU time | 2.48 seconds |
| Started | Aug 28 10:52:01 PM UTC 24 |
| Finished | Aug 28 10:52:04 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713588416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1713588416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.1257444578 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 401546998 ps |
| CPU time | 7.34 seconds |
| Started | Aug 28 10:52:02 PM UTC 24 |
| Finished | Aug 28 10:52:10 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257444578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1257444578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.1331772324 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1393700316 ps |
| CPU time | 3.44 seconds |
| Started | Aug 28 10:52:01 PM UTC 24 |
| Finished | Aug 28 10:52:05 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331772324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1331772324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_random.1298417031 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 122188635 ps |
| CPU time | 6.62 seconds |
| Started | Aug 28 10:52:00 PM UTC 24 |
| Finished | Aug 28 10:52:07 PM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298417031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1298417031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.652076673 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 719798722 ps |
| CPU time | 8.53 seconds |
| Started | Aug 28 10:51:57 PM UTC 24 |
| Finished | Aug 28 10:52:07 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652076673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.652076673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.1436239902 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 243160304 ps |
| CPU time | 7.67 seconds |
| Started | Aug 28 10:51:58 PM UTC 24 |
| Finished | Aug 28 10:52:07 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436239902 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1436239902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.270689719 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 188421304 ps |
| CPU time | 4 seconds |
| Started | Aug 28 10:51:58 PM UTC 24 |
| Finished | Aug 28 10:52:03 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270689719 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.270689719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.495312024 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 69821693 ps |
| CPU time | 3.9 seconds |
| Started | Aug 28 10:52:02 PM UTC 24 |
| Finished | Aug 28 10:52:07 PM UTC 24 |
| Peak memory | 228264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495312024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.495312024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.1215992338 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 254973054 ps |
| CPU time | 3.27 seconds |
| Started | Aug 28 10:51:57 PM UTC 24 |
| Finished | Aug 28 10:52:01 PM UTC 24 |
| Peak memory | 215748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215992338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1215992338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.739920670 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1126851445 ps |
| CPU time | 13.16 seconds |
| Started | Aug 28 10:52:01 PM UTC 24 |
| Finished | Aug 28 10:52:15 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739920670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.739920670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.2888412454 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 128710330 ps |
| CPU time | 2.8 seconds |
| Started | Aug 28 10:52:02 PM UTC 24 |
| Finished | Aug 28 10:52:06 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888412454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2888412454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.1889292602 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 43128987 ps |
| CPU time | 1.15 seconds |
| Started | Aug 28 10:52:09 PM UTC 24 |
| Finished | Aug 28 10:52:11 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889292602 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1889292602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.3587705502 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 86592934 ps |
| CPU time | 6.68 seconds |
| Started | Aug 28 10:52:07 PM UTC 24 |
| Finished | Aug 28 10:52:15 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587705502 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3587705502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.600793042 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 327922612 ps |
| CPU time | 4.16 seconds |
| Started | Aug 28 10:52:09 PM UTC 24 |
| Finished | Aug 28 10:52:14 PM UTC 24 |
| Peak memory | 220112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600793042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.600793042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.3027511882 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 26944303 ps |
| CPU time | 2.21 seconds |
| Started | Aug 28 10:52:07 PM UTC 24 |
| Finished | Aug 28 10:52:10 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027511882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3027511882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.166766929 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 841489771 ps |
| CPU time | 19.01 seconds |
| Started | Aug 28 10:52:07 PM UTC 24 |
| Finished | Aug 28 10:52:28 PM UTC 24 |
| Peak memory | 226352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166766929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.166766929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_random.2707943975 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 62518597 ps |
| CPU time | 3.24 seconds |
| Started | Aug 28 10:52:07 PM UTC 24 |
| Finished | Aug 28 10:52:11 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707943975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2707943975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.3559231353 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 136288215 ps |
| CPU time | 3.61 seconds |
| Started | Aug 28 10:52:05 PM UTC 24 |
| Finished | Aug 28 10:52:09 PM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559231353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3559231353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.1114479015 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 384931656 ps |
| CPU time | 4.19 seconds |
| Started | Aug 28 10:52:05 PM UTC 24 |
| Finished | Aug 28 10:52:10 PM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114479015 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1114479015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.3444363355 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 253360065 ps |
| CPU time | 4.7 seconds |
| Started | Aug 28 10:52:05 PM UTC 24 |
| Finished | Aug 28 10:52:11 PM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444363355 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3444363355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.3351348462 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 192299950 ps |
| CPU time | 8 seconds |
| Started | Aug 28 10:52:06 PM UTC 24 |
| Finished | Aug 28 10:52:15 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351348462 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3351348462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.2066621135 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 433296435 ps |
| CPU time | 5.12 seconds |
| Started | Aug 28 10:52:09 PM UTC 24 |
| Finished | Aug 28 10:52:15 PM UTC 24 |
| Peak memory | 230664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066621135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2066621135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.2645988472 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 77958801 ps |
| CPU time | 3.56 seconds |
| Started | Aug 28 10:52:05 PM UTC 24 |
| Finished | Aug 28 10:52:09 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645988472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2645988472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.1129725278 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 147376405 ps |
| CPU time | 10.47 seconds |
| Started | Aug 28 10:52:09 PM UTC 24 |
| Finished | Aug 28 10:52:20 PM UTC 24 |
| Peak memory | 231012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1129725278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg r_stress_all_with_rand_reset.1129725278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.3819683650 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 116021685 ps |
| CPU time | 7.57 seconds |
| Started | Aug 28 10:52:07 PM UTC 24 |
| Finished | Aug 28 10:52:16 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819683650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3819683650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.4240958221 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 146578441 ps |
| CPU time | 2.97 seconds |
| Started | Aug 28 10:52:09 PM UTC 24 |
| Finished | Aug 28 10:52:13 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240958221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4240958221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.272260145 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 29402625 ps |
| CPU time | 1.33 seconds |
| Started | Aug 28 10:52:16 PM UTC 24 |
| Finished | Aug 28 10:52:19 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272260145 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.272260145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.139410561 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 116821331 ps |
| CPU time | 5.25 seconds |
| Started | Aug 28 10:52:14 PM UTC 24 |
| Finished | Aug 28 10:52:20 PM UTC 24 |
| Peak memory | 231544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139410561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.139410561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.447990388 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 222919562 ps |
| CPU time | 5.87 seconds |
| Started | Aug 28 10:52:11 PM UTC 24 |
| Finished | Aug 28 10:52:18 PM UTC 24 |
| Peak memory | 228032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447990388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.447990388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.1041132107 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 116606318 ps |
| CPU time | 5.21 seconds |
| Started | Aug 28 10:52:13 PM UTC 24 |
| Finished | Aug 28 10:52:19 PM UTC 24 |
| Peak memory | 231012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041132107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1041132107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.2001016549 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 76406538 ps |
| CPU time | 4.18 seconds |
| Started | Aug 28 10:52:13 PM UTC 24 |
| Finished | Aug 28 10:52:18 PM UTC 24 |
| Peak memory | 230188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001016549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2001016549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.3953616605 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 249388578 ps |
| CPU time | 4.4 seconds |
| Started | Aug 28 10:52:11 PM UTC 24 |
| Finished | Aug 28 10:52:17 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953616605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3953616605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_random.496194774 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 683057369 ps |
| CPU time | 8.44 seconds |
| Started | Aug 28 10:52:11 PM UTC 24 |
| Finished | Aug 28 10:52:21 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496194774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.496194774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.3712729410 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1967577217 ps |
| CPU time | 20.66 seconds |
| Started | Aug 28 10:52:10 PM UTC 24 |
| Finished | Aug 28 10:52:32 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712729410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3712729410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.954589640 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1085669905 ps |
| CPU time | 29.09 seconds |
| Started | Aug 28 10:52:11 PM UTC 24 |
| Finished | Aug 28 10:52:42 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954589640 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.954589640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.3031331582 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 6455262773 ps |
| CPU time | 19.43 seconds |
| Started | Aug 28 10:52:10 PM UTC 24 |
| Finished | Aug 28 10:52:31 PM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031331582 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3031331582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.2436654810 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 573974520 ps |
| CPU time | 5.67 seconds |
| Started | Aug 28 10:52:11 PM UTC 24 |
| Finished | Aug 28 10:52:18 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436654810 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2436654810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.2323695085 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1501787764 ps |
| CPU time | 3.08 seconds |
| Started | Aug 28 10:52:14 PM UTC 24 |
| Finished | Aug 28 10:52:18 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323695085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2323695085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.1513374440 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 5336366050 ps |
| CPU time | 17.84 seconds |
| Started | Aug 28 10:52:10 PM UTC 24 |
| Finished | Aug 28 10:52:29 PM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513374440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1513374440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.2513910729 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 208133882 ps |
| CPU time | 6.46 seconds |
| Started | Aug 28 10:52:13 PM UTC 24 |
| Finished | Aug 28 10:52:20 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513910729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2513910729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.4115744161 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 202804003 ps |
| CPU time | 2.29 seconds |
| Started | Aug 28 10:52:14 PM UTC 24 |
| Finished | Aug 28 10:52:17 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115744161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4115744161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.2488103777 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 39879271 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 10:52:20 PM UTC 24 |
| Finished | Aug 28 10:52:22 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488103777 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2488103777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.3909971090 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 61521931 ps |
| CPU time | 5.64 seconds |
| Started | Aug 28 10:52:18 PM UTC 24 |
| Finished | Aug 28 10:52:25 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909971090 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3909971090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.3165722804 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 58602947 ps |
| CPU time | 3.68 seconds |
| Started | Aug 28 10:52:18 PM UTC 24 |
| Finished | Aug 28 10:52:23 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165722804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3165722804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.2727212400 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1053478895 ps |
| CPU time | 7.41 seconds |
| Started | Aug 28 10:52:19 PM UTC 24 |
| Finished | Aug 28 10:52:27 PM UTC 24 |
| Peak memory | 231124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727212400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2727212400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.3070622697 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 200247277 ps |
| CPU time | 3.33 seconds |
| Started | Aug 28 10:52:19 PM UTC 24 |
| Finished | Aug 28 10:52:23 PM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070622697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3070622697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.2317422907 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 875020184 ps |
| CPU time | 4.21 seconds |
| Started | Aug 28 10:52:19 PM UTC 24 |
| Finished | Aug 28 10:52:24 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317422907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2317422907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_random.2384068973 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 104574219 ps |
| CPU time | 4.69 seconds |
| Started | Aug 28 10:52:18 PM UTC 24 |
| Finished | Aug 28 10:52:23 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384068973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2384068973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.1437905636 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 139397825 ps |
| CPU time | 5.72 seconds |
| Started | Aug 28 10:52:16 PM UTC 24 |
| Finished | Aug 28 10:52:23 PM UTC 24 |
| Peak memory | 216008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437905636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1437905636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.3311594401 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 33390994 ps |
| CPU time | 2.42 seconds |
| Started | Aug 28 10:52:17 PM UTC 24 |
| Finished | Aug 28 10:52:20 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311594401 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3311594401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.1851045641 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 971045278 ps |
| CPU time | 25.13 seconds |
| Started | Aug 28 10:52:16 PM UTC 24 |
| Finished | Aug 28 10:52:43 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851045641 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1851045641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.3856727953 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1969066714 ps |
| CPU time | 25.42 seconds |
| Started | Aug 28 10:52:18 PM UTC 24 |
| Finished | Aug 28 10:52:44 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856727953 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3856727953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.122791107 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 111666782 ps |
| CPU time | 2.26 seconds |
| Started | Aug 28 10:52:19 PM UTC 24 |
| Finished | Aug 28 10:52:22 PM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122791107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.122791107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.842585770 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 79571558 ps |
| CPU time | 3.63 seconds |
| Started | Aug 28 10:52:16 PM UTC 24 |
| Finished | Aug 28 10:52:21 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842585770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.842585770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all_with_rand_reset.3999277878 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1761501473 ps |
| CPU time | 11.35 seconds |
| Started | Aug 28 10:52:20 PM UTC 24 |
| Finished | Aug 28 10:52:33 PM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3999277878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymg r_stress_all_with_rand_reset.3999277878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.3314946504 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1229109524 ps |
| CPU time | 34.82 seconds |
| Started | Aug 28 10:52:19 PM UTC 24 |
| Finished | Aug 28 10:52:55 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314946504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3314946504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.1194059875 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 14254086 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:52:28 PM UTC 24 |
| Finished | Aug 28 10:52:30 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194059875 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1194059875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.1466857204 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 192497369 ps |
| CPU time | 13.18 seconds |
| Started | Aug 28 10:52:23 PM UTC 24 |
| Finished | Aug 28 10:52:37 PM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466857204 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1466857204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.1539004021 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 469953271 ps |
| CPU time | 7.27 seconds |
| Started | Aug 28 10:52:26 PM UTC 24 |
| Finished | Aug 28 10:52:34 PM UTC 24 |
| Peak memory | 218568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539004021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1539004021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.3690845035 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 141259653 ps |
| CPU time | 4.27 seconds |
| Started | Aug 28 10:52:23 PM UTC 24 |
| Finished | Aug 28 10:52:28 PM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690845035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3690845035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.1806994122 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 211186783 ps |
| CPU time | 5.78 seconds |
| Started | Aug 28 10:52:24 PM UTC 24 |
| Finished | Aug 28 10:52:31 PM UTC 24 |
| Peak memory | 230496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806994122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1806994122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.2922321752 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 479296057 ps |
| CPU time | 7.64 seconds |
| Started | Aug 28 10:52:23 PM UTC 24 |
| Finished | Aug 28 10:52:32 PM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922321752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2922321752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_random.123298322 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 688853321 ps |
| CPU time | 12.07 seconds |
| Started | Aug 28 10:52:22 PM UTC 24 |
| Finished | Aug 28 10:52:35 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123298322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.123298322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.1375533825 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3402876620 ps |
| CPU time | 7.81 seconds |
| Started | Aug 28 10:52:22 PM UTC 24 |
| Finished | Aug 28 10:52:31 PM UTC 24 |
| Peak memory | 218100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375533825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1375533825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.3062432884 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 300763813 ps |
| CPU time | 3.86 seconds |
| Started | Aug 28 10:52:22 PM UTC 24 |
| Finished | Aug 28 10:52:27 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062432884 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3062432884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.4271848450 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 161099137 ps |
| CPU time | 5.95 seconds |
| Started | Aug 28 10:52:22 PM UTC 24 |
| Finished | Aug 28 10:52:29 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271848450 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4271848450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.3784372043 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 240042822 ps |
| CPU time | 7.91 seconds |
| Started | Aug 28 10:52:22 PM UTC 24 |
| Finished | Aug 28 10:52:31 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784372043 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3784372043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.2587649232 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 106332403 ps |
| CPU time | 2.52 seconds |
| Started | Aug 28 10:52:26 PM UTC 24 |
| Finished | Aug 28 10:52:29 PM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587649232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2587649232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.2395274419 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 121922784 ps |
| CPU time | 4.18 seconds |
| Started | Aug 28 10:52:22 PM UTC 24 |
| Finished | Aug 28 10:52:27 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395274419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2395274419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.1392582685 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2810494448 ps |
| CPU time | 36.43 seconds |
| Started | Aug 28 10:52:26 PM UTC 24 |
| Finished | Aug 28 10:53:04 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392582685 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1392582685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.3681834285 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 767421269 ps |
| CPU time | 17.65 seconds |
| Started | Aug 28 10:52:27 PM UTC 24 |
| Finished | Aug 28 10:52:46 PM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3681834285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymg r_stress_all_with_rand_reset.3681834285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.2869213793 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 37716948 ps |
| CPU time | 4.11 seconds |
| Started | Aug 28 10:52:24 PM UTC 24 |
| Finished | Aug 28 10:52:30 PM UTC 24 |
| Peak memory | 220260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869213793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2869213793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.1707283748 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1134179092 ps |
| CPU time | 7.5 seconds |
| Started | Aug 28 10:52:26 PM UTC 24 |
| Finished | Aug 28 10:52:34 PM UTC 24 |
| Peak memory | 220328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707283748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1707283748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.2014275036 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 22647718 ps |
| CPU time | 1.24 seconds |
| Started | Aug 28 10:52:33 PM UTC 24 |
| Finished | Aug 28 10:52:36 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014275036 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2014275036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.2418159066 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 465370482 ps |
| CPU time | 5.79 seconds |
| Started | Aug 28 10:52:32 PM UTC 24 |
| Finished | Aug 28 10:52:39 PM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418159066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2418159066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.1294266584 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 38042112 ps |
| CPU time | 2.79 seconds |
| Started | Aug 28 10:52:30 PM UTC 24 |
| Finished | Aug 28 10:52:34 PM UTC 24 |
| Peak memory | 220224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294266584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1294266584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.218808384 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1482697541 ps |
| CPU time | 10.02 seconds |
| Started | Aug 28 10:52:32 PM UTC 24 |
| Finished | Aug 28 10:52:43 PM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218808384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.218808384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.2495539773 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 116278214 ps |
| CPU time | 4.23 seconds |
| Started | Aug 28 10:52:31 PM UTC 24 |
| Finished | Aug 28 10:52:36 PM UTC 24 |
| Peak memory | 224476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495539773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2495539773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_random.562858322 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 50773016 ps |
| CPU time | 4.3 seconds |
| Started | Aug 28 10:52:30 PM UTC 24 |
| Finished | Aug 28 10:52:36 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562858322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.562858322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.2382773193 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 64371156 ps |
| CPU time | 3.75 seconds |
| Started | Aug 28 10:52:28 PM UTC 24 |
| Finished | Aug 28 10:52:33 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382773193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2382773193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.2220984530 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 78992988 ps |
| CPU time | 1.89 seconds |
| Started | Aug 28 10:52:29 PM UTC 24 |
| Finished | Aug 28 10:52:32 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220984530 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2220984530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.609917879 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 683267620 ps |
| CPU time | 6.86 seconds |
| Started | Aug 28 10:52:29 PM UTC 24 |
| Finished | Aug 28 10:52:37 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609917879 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.609917879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.1893342091 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 178126282 ps |
| CPU time | 5.5 seconds |
| Started | Aug 28 10:52:29 PM UTC 24 |
| Finished | Aug 28 10:52:36 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893342091 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1893342091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.556242772 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 22931138 ps |
| CPU time | 2.11 seconds |
| Started | Aug 28 10:52:32 PM UTC 24 |
| Finished | Aug 28 10:52:35 PM UTC 24 |
| Peak memory | 228264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556242772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.556242772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.50407666 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 358371786 ps |
| CPU time | 7.8 seconds |
| Started | Aug 28 10:52:28 PM UTC 24 |
| Finished | Aug 28 10:52:37 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50407666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.50407666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.4214054762 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 290733181 ps |
| CPU time | 14.96 seconds |
| Started | Aug 28 10:52:32 PM UTC 24 |
| Finished | Aug 28 10:52:48 PM UTC 24 |
| Peak memory | 231484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214054762 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4214054762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.3770061229 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3307803711 ps |
| CPU time | 57.91 seconds |
| Started | Aug 28 10:52:31 PM UTC 24 |
| Finished | Aug 28 10:53:30 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770061229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3770061229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.3242739801 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 231487668 ps |
| CPU time | 3.73 seconds |
| Started | Aug 28 10:52:32 PM UTC 24 |
| Finished | Aug 28 10:52:37 PM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242739801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3242739801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.531753224 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 15828136 ps |
| CPU time | 1.23 seconds |
| Started | Aug 28 10:52:38 PM UTC 24 |
| Finished | Aug 28 10:52:40 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531753224 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.531753224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.819117822 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 402037833 ps |
| CPU time | 5.65 seconds |
| Started | Aug 28 10:52:36 PM UTC 24 |
| Finished | Aug 28 10:52:43 PM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819117822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.819117822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.1482427998 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 665211079 ps |
| CPU time | 21.99 seconds |
| Started | Aug 28 10:52:35 PM UTC 24 |
| Finished | Aug 28 10:52:58 PM UTC 24 |
| Peak memory | 224452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482427998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1482427998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.647973340 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 303137246 ps |
| CPU time | 3.35 seconds |
| Started | Aug 28 10:52:36 PM UTC 24 |
| Finished | Aug 28 10:52:40 PM UTC 24 |
| Peak memory | 224200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647973340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.647973340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.1932616819 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 72543096 ps |
| CPU time | 5.39 seconds |
| Started | Aug 28 10:52:36 PM UTC 24 |
| Finished | Aug 28 10:52:43 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932616819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1932616819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.4090690072 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 248453296 ps |
| CPU time | 5.91 seconds |
| Started | Aug 28 10:52:36 PM UTC 24 |
| Finished | Aug 28 10:52:43 PM UTC 24 |
| Peak memory | 219936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090690072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4090690072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_random.2064953630 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 68439923 ps |
| CPU time | 4.46 seconds |
| Started | Aug 28 10:52:35 PM UTC 24 |
| Finished | Aug 28 10:52:40 PM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064953630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2064953630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.2754302474 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5898714045 ps |
| CPU time | 55.92 seconds |
| Started | Aug 28 10:52:33 PM UTC 24 |
| Finished | Aug 28 10:53:31 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754302474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2754302474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.549816258 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 138855996 ps |
| CPU time | 5.42 seconds |
| Started | Aug 28 10:52:35 PM UTC 24 |
| Finished | Aug 28 10:52:41 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549816258 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.549816258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.3402739489 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 35209391 ps |
| CPU time | 3.35 seconds |
| Started | Aug 28 10:52:35 PM UTC 24 |
| Finished | Aug 28 10:52:39 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402739489 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3402739489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.653679051 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 170819006 ps |
| CPU time | 3.08 seconds |
| Started | Aug 28 10:52:35 PM UTC 24 |
| Finished | Aug 28 10:52:39 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653679051 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.653679051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.1305607043 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 246614883 ps |
| CPU time | 4.18 seconds |
| Started | Aug 28 10:52:36 PM UTC 24 |
| Finished | Aug 28 10:52:41 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305607043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1305607043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.3461357366 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3591980650 ps |
| CPU time | 28.66 seconds |
| Started | Aug 28 10:52:33 PM UTC 24 |
| Finished | Aug 28 10:53:03 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461357366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3461357366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.2749462517 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 24817562831 ps |
| CPU time | 32.53 seconds |
| Started | Aug 28 10:52:37 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749462517 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2749462517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.2068539318 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 253539942 ps |
| CPU time | 4.02 seconds |
| Started | Aug 28 10:52:36 PM UTC 24 |
| Finished | Aug 28 10:52:41 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068539318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2068539318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.2921942922 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 55255960 ps |
| CPU time | 1.14 seconds |
| Started | Aug 28 10:52:44 PM UTC 24 |
| Finished | Aug 28 10:52:46 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921942922 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2921942922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.3297667882 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 235714978 ps |
| CPU time | 7.76 seconds |
| Started | Aug 28 10:52:41 PM UTC 24 |
| Finished | Aug 28 10:52:50 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297667882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3297667882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.947657611 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 557257105 ps |
| CPU time | 4.76 seconds |
| Started | Aug 28 10:52:41 PM UTC 24 |
| Finished | Aug 28 10:52:47 PM UTC 24 |
| Peak memory | 224116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947657611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.947657611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_random.2397596953 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 257691216 ps |
| CPU time | 5.57 seconds |
| Started | Aug 28 10:52:40 PM UTC 24 |
| Finished | Aug 28 10:52:47 PM UTC 24 |
| Peak memory | 224144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397596953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2397596953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.1956972945 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1068875384 ps |
| CPU time | 4.27 seconds |
| Started | Aug 28 10:52:39 PM UTC 24 |
| Finished | Aug 28 10:52:44 PM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956972945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1956972945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.2551419451 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 507307315 ps |
| CPU time | 4.9 seconds |
| Started | Aug 28 10:52:39 PM UTC 24 |
| Finished | Aug 28 10:52:45 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551419451 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2551419451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.2268844731 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1588395427 ps |
| CPU time | 7.17 seconds |
| Started | Aug 28 10:52:39 PM UTC 24 |
| Finished | Aug 28 10:52:47 PM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268844731 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2268844731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.1674262427 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1470163943 ps |
| CPU time | 13.96 seconds |
| Started | Aug 28 10:52:39 PM UTC 24 |
| Finished | Aug 28 10:52:54 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674262427 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1674262427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.1438134989 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 196473449 ps |
| CPU time | 3.01 seconds |
| Started | Aug 28 10:52:43 PM UTC 24 |
| Finished | Aug 28 10:52:47 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438134989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1438134989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.2356204620 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 171985324 ps |
| CPU time | 3.97 seconds |
| Started | Aug 28 10:52:38 PM UTC 24 |
| Finished | Aug 28 10:52:43 PM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356204620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2356204620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.1474661088 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 464745042 ps |
| CPU time | 18.39 seconds |
| Started | Aug 28 10:52:43 PM UTC 24 |
| Finished | Aug 28 10:53:02 PM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474661088 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1474661088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all_with_rand_reset.154327725 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1231799868 ps |
| CPU time | 26.59 seconds |
| Started | Aug 28 10:52:43 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 232384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=154327725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr _stress_all_with_rand_reset.154327725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.1793119865 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 53549175 ps |
| CPU time | 2.66 seconds |
| Started | Aug 28 10:52:41 PM UTC 24 |
| Finished | Aug 28 10:52:45 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793119865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1793119865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.4191592367 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 834951928 ps |
| CPU time | 5 seconds |
| Started | Aug 28 10:52:43 PM UTC 24 |
| Finished | Aug 28 10:52:49 PM UTC 24 |
| Peak memory | 219936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191592367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4191592367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.2808911254 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 136616479 ps |
| CPU time | 1.17 seconds |
| Started | Aug 28 10:52:49 PM UTC 24 |
| Finished | Aug 28 10:52:51 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808911254 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2808911254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.2461977269 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 382100412 ps |
| CPU time | 6.37 seconds |
| Started | Aug 28 10:52:45 PM UTC 24 |
| Finished | Aug 28 10:52:53 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461977269 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2461977269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.3344902862 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 228745909 ps |
| CPU time | 3.92 seconds |
| Started | Aug 28 10:52:47 PM UTC 24 |
| Finished | Aug 28 10:52:52 PM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344902862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3344902862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.2290766720 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 295501860 ps |
| CPU time | 10.04 seconds |
| Started | Aug 28 10:52:45 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290766720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2290766720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.384912989 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1496843528 ps |
| CPU time | 4.66 seconds |
| Started | Aug 28 10:52:47 PM UTC 24 |
| Finished | Aug 28 10:52:53 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384912989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.384912989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.3257166185 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 951023689 ps |
| CPU time | 10.52 seconds |
| Started | Aug 28 10:52:47 PM UTC 24 |
| Finished | Aug 28 10:52:59 PM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257166185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3257166185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.565770199 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 76605332 ps |
| CPU time | 4.01 seconds |
| Started | Aug 28 10:52:45 PM UTC 24 |
| Finished | Aug 28 10:52:51 PM UTC 24 |
| Peak memory | 220372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565770199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.565770199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_random.3789177665 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2969053569 ps |
| CPU time | 15.61 seconds |
| Started | Aug 28 10:52:45 PM UTC 24 |
| Finished | Aug 28 10:53:02 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789177665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3789177665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.409048970 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 804473491 ps |
| CPU time | 19.33 seconds |
| Started | Aug 28 10:52:44 PM UTC 24 |
| Finished | Aug 28 10:53:04 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409048970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.409048970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.3781295749 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 101696558 ps |
| CPU time | 3.7 seconds |
| Started | Aug 28 10:52:44 PM UTC 24 |
| Finished | Aug 28 10:52:49 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781295749 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3781295749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.1343106025 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 480669378 ps |
| CPU time | 9.84 seconds |
| Started | Aug 28 10:52:44 PM UTC 24 |
| Finished | Aug 28 10:52:55 PM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343106025 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1343106025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.538360489 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 36375100 ps |
| CPU time | 2.44 seconds |
| Started | Aug 28 10:52:44 PM UTC 24 |
| Finished | Aug 28 10:52:48 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538360489 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.538360489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.1431712803 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2830390815 ps |
| CPU time | 5.49 seconds |
| Started | Aug 28 10:52:48 PM UTC 24 |
| Finished | Aug 28 10:52:55 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431712803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1431712803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.3123324808 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 165278691 ps |
| CPU time | 5.17 seconds |
| Started | Aug 28 10:52:44 PM UTC 24 |
| Finished | Aug 28 10:52:50 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123324808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3123324808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.2819381803 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 149232805 ps |
| CPU time | 7.87 seconds |
| Started | Aug 28 10:52:48 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819381803 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2819381803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.3312820884 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2275218897 ps |
| CPU time | 22.92 seconds |
| Started | Aug 28 10:52:48 PM UTC 24 |
| Finished | Aug 28 10:53:12 PM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3312820884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymg r_stress_all_with_rand_reset.3312820884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.1011824968 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 279088150 ps |
| CPU time | 8.81 seconds |
| Started | Aug 28 10:52:46 PM UTC 24 |
| Finished | Aug 28 10:52:55 PM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011824968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1011824968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.341937819 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 154595939 ps |
| CPU time | 2.73 seconds |
| Started | Aug 28 10:52:48 PM UTC 24 |
| Finished | Aug 28 10:52:52 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341937819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.341937819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.873924324 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 31263569 ps |
| CPU time | 1.03 seconds |
| Started | Aug 28 10:52:55 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873924324 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.873924324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.3591817846 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 38560044 ps |
| CPU time | 3.21 seconds |
| Started | Aug 28 10:52:53 PM UTC 24 |
| Finished | Aug 28 10:52:58 PM UTC 24 |
| Peak memory | 226576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591817846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3591817846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.329461622 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 745247594 ps |
| CPU time | 5.03 seconds |
| Started | Aug 28 10:52:51 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329461622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.329461622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.974096935 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 88943095 ps |
| CPU time | 2.49 seconds |
| Started | Aug 28 10:52:52 PM UTC 24 |
| Finished | Aug 28 10:52:56 PM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974096935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.974096935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.3819767064 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 66749403 ps |
| CPU time | 4.4 seconds |
| Started | Aug 28 10:52:52 PM UTC 24 |
| Finished | Aug 28 10:52:58 PM UTC 24 |
| Peak memory | 220204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819767064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3819767064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.4151387894 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 107691467 ps |
| CPU time | 2.25 seconds |
| Started | Aug 28 10:52:51 PM UTC 24 |
| Finished | Aug 28 10:52:55 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151387894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4151387894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_random.4280595274 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 451534164 ps |
| CPU time | 4.96 seconds |
| Started | Aug 28 10:52:51 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280595274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4280595274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.3088920650 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 303191419 ps |
| CPU time | 2.34 seconds |
| Started | Aug 28 10:52:49 PM UTC 24 |
| Finished | Aug 28 10:52:53 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088920650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3088920650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.2456287914 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 184519834 ps |
| CPU time | 6.91 seconds |
| Started | Aug 28 10:52:50 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456287914 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2456287914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.169901307 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 308203086 ps |
| CPU time | 4.12 seconds |
| Started | Aug 28 10:52:49 PM UTC 24 |
| Finished | Aug 28 10:52:55 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169901307 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.169901307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.64505234 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 126485377 ps |
| CPU time | 4.93 seconds |
| Started | Aug 28 10:52:50 PM UTC 24 |
| Finished | Aug 28 10:52:56 PM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64505234 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.64505234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.2517522935 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 30106060 ps |
| CPU time | 1.92 seconds |
| Started | Aug 28 10:52:53 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517522935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2517522935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.2752265002 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 353773232 ps |
| CPU time | 7.95 seconds |
| Started | Aug 28 10:52:49 PM UTC 24 |
| Finished | Aug 28 10:52:58 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752265002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2752265002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.543909446 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 276981021 ps |
| CPU time | 6.35 seconds |
| Started | Aug 28 10:52:52 PM UTC 24 |
| Finished | Aug 28 10:53:00 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543909446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.543909446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.1444977769 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 112087303 ps |
| CPU time | 2.56 seconds |
| Started | Aug 28 10:52:53 PM UTC 24 |
| Finished | Aug 28 10:52:57 PM UTC 24 |
| Peak memory | 220264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444977769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1444977769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.1167350433 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 43937686 ps |
| CPU time | 1.08 seconds |
| Started | Aug 28 10:51:16 PM UTC 24 |
| Finished | Aug 28 10:51:18 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167350433 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1167350433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.1769798378 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 693863734 ps |
| CPU time | 5.06 seconds |
| Started | Aug 28 10:51:11 PM UTC 24 |
| Finished | Aug 28 10:51:17 PM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769798378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1769798378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.2032673999 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 57340508 ps |
| CPU time | 2.75 seconds |
| Started | Aug 28 10:51:12 PM UTC 24 |
| Finished | Aug 28 10:51:19 PM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032673999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2032673999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.3355109915 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 227208746 ps |
| CPU time | 3.94 seconds |
| Started | Aug 28 10:51:11 PM UTC 24 |
| Finished | Aug 28 10:51:19 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355109915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3355109915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_random.3287764586 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 205384797 ps |
| CPU time | 7.22 seconds |
| Started | Aug 28 10:51:09 PM UTC 24 |
| Finished | Aug 28 10:51:18 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287764586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3287764586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.28864659 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 810935544 ps |
| CPU time | 5.41 seconds |
| Started | Aug 28 10:51:16 PM UTC 24 |
| Finished | Aug 28 10:51:22 PM UTC 24 |
| Peak memory | 256684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28864659 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.28864659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.2465332486 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 92588835 ps |
| CPU time | 2.67 seconds |
| Started | Aug 28 10:51:08 PM UTC 24 |
| Finished | Aug 28 10:51:13 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465332486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2465332486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.1212565227 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1525901635 ps |
| CPU time | 5.27 seconds |
| Started | Aug 28 10:51:09 PM UTC 24 |
| Finished | Aug 28 10:51:16 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212565227 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1212565227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.3305372317 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 124082036 ps |
| CPU time | 2.59 seconds |
| Started | Aug 28 10:51:08 PM UTC 24 |
| Finished | Aug 28 10:51:13 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305372317 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3305372317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.1618439514 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 292003164 ps |
| CPU time | 5.83 seconds |
| Started | Aug 28 10:51:09 PM UTC 24 |
| Finished | Aug 28 10:51:16 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618439514 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1618439514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.2992303540 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 28731941 ps |
| CPU time | 2.4 seconds |
| Started | Aug 28 10:51:14 PM UTC 24 |
| Finished | Aug 28 10:51:18 PM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992303540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2992303540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.166960715 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 158448026 ps |
| CPU time | 3.73 seconds |
| Started | Aug 28 10:51:06 PM UTC 24 |
| Finished | Aug 28 10:51:11 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166960715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.166960715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.4206302080 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 22044728914 ps |
| CPU time | 141.38 seconds |
| Started | Aug 28 10:51:15 PM UTC 24 |
| Finished | Aug 28 10:53:39 PM UTC 24 |
| Peak memory | 228264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206302080 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.4206302080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.520983813 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 573480576 ps |
| CPU time | 10.11 seconds |
| Started | Aug 28 10:51:15 PM UTC 24 |
| Finished | Aug 28 10:51:26 PM UTC 24 |
| Peak memory | 232284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=520983813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_ stress_all_with_rand_reset.520983813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.3993122933 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 488253388 ps |
| CPU time | 7.11 seconds |
| Started | Aug 28 10:51:11 PM UTC 24 |
| Finished | Aug 28 10:51:19 PM UTC 24 |
| Peak memory | 230500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993122933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3993122933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.2913202115 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 243830401 ps |
| CPU time | 3.59 seconds |
| Started | Aug 28 10:51:14 PM UTC 24 |
| Finished | Aug 28 10:51:19 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913202115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2913202115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.3682190059 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 52964656 ps |
| CPU time | 0.93 seconds |
| Started | Aug 28 10:52:59 PM UTC 24 |
| Finished | Aug 28 10:53:00 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682190059 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3682190059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.1257835693 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 244804827 ps |
| CPU time | 5.63 seconds |
| Started | Aug 28 10:52:57 PM UTC 24 |
| Finished | Aug 28 10:53:04 PM UTC 24 |
| Peak memory | 226164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257835693 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1257835693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.2900030085 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 265689642 ps |
| CPU time | 4.96 seconds |
| Started | Aug 28 10:52:58 PM UTC 24 |
| Finished | Aug 28 10:53:04 PM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900030085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2900030085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.3226027862 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 278081574 ps |
| CPU time | 3.16 seconds |
| Started | Aug 28 10:52:57 PM UTC 24 |
| Finished | Aug 28 10:53:01 PM UTC 24 |
| Peak memory | 220296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226027862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3226027862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.2931848037 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 548927241 ps |
| CPU time | 3.68 seconds |
| Started | Aug 28 10:52:57 PM UTC 24 |
| Finished | Aug 28 10:53:02 PM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931848037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2931848037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_random.3383534086 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 32047533 ps |
| CPU time | 3.33 seconds |
| Started | Aug 28 10:52:56 PM UTC 24 |
| Finished | Aug 28 10:53:00 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383534086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3383534086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.1616340054 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1551003701 ps |
| CPU time | 37.01 seconds |
| Started | Aug 28 10:52:56 PM UTC 24 |
| Finished | Aug 28 10:53:34 PM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616340054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1616340054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.151211705 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 144200799 ps |
| CPU time | 3.21 seconds |
| Started | Aug 28 10:52:56 PM UTC 24 |
| Finished | Aug 28 10:53:00 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151211705 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.151211705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.365214218 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 62579679 ps |
| CPU time | 3.89 seconds |
| Started | Aug 28 10:52:56 PM UTC 24 |
| Finished | Aug 28 10:53:01 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365214218 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.365214218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.2139576074 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 153580035 ps |
| CPU time | 4.62 seconds |
| Started | Aug 28 10:52:56 PM UTC 24 |
| Finished | Aug 28 10:53:02 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139576074 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2139576074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.1657947681 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1317415142 ps |
| CPU time | 22.62 seconds |
| Started | Aug 28 10:52:58 PM UTC 24 |
| Finished | Aug 28 10:53:22 PM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657947681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1657947681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.2205967419 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 139300054 ps |
| CPU time | 3.81 seconds |
| Started | Aug 28 10:52:55 PM UTC 24 |
| Finished | Aug 28 10:53:00 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205967419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2205967419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.1115288559 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 103469162 ps |
| CPU time | 7.15 seconds |
| Started | Aug 28 10:52:58 PM UTC 24 |
| Finished | Aug 28 10:53:07 PM UTC 24 |
| Peak memory | 228160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115288559 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1115288559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.3823994615 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 4136065571 ps |
| CPU time | 9.21 seconds |
| Started | Aug 28 10:52:58 PM UTC 24 |
| Finished | Aug 28 10:53:09 PM UTC 24 |
| Peak memory | 230644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3823994615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg r_stress_all_with_rand_reset.3823994615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.3298632393 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 205342754 ps |
| CPU time | 4.4 seconds |
| Started | Aug 28 10:52:57 PM UTC 24 |
| Finished | Aug 28 10:53:03 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298632393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3298632393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.404658272 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 231787779 ps |
| CPU time | 3.16 seconds |
| Started | Aug 28 10:52:58 PM UTC 24 |
| Finished | Aug 28 10:53:03 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404658272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.404658272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.3328172117 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 12937585 ps |
| CPU time | 1.17 seconds |
| Started | Aug 28 10:53:04 PM UTC 24 |
| Finished | Aug 28 10:53:06 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328172117 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3328172117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.4184895891 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 85767516 ps |
| CPU time | 3.69 seconds |
| Started | Aug 28 10:53:02 PM UTC 24 |
| Finished | Aug 28 10:53:07 PM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184895891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.4184895891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.2806427311 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 49389959 ps |
| CPU time | 2.64 seconds |
| Started | Aug 28 10:53:01 PM UTC 24 |
| Finished | Aug 28 10:53:05 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806427311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2806427311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.1428423369 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 147938079 ps |
| CPU time | 2.43 seconds |
| Started | Aug 28 10:53:01 PM UTC 24 |
| Finished | Aug 28 10:53:05 PM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428423369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1428423369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.324068039 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 148910735 ps |
| CPU time | 3.62 seconds |
| Started | Aug 28 10:53:01 PM UTC 24 |
| Finished | Aug 28 10:53:06 PM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324068039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.324068039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_random.3277768087 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 999817116 ps |
| CPU time | 4.56 seconds |
| Started | Aug 28 10:53:01 PM UTC 24 |
| Finished | Aug 28 10:53:07 PM UTC 24 |
| Peak memory | 220104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277768087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3277768087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.1921490593 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 65982446 ps |
| CPU time | 3.5 seconds |
| Started | Aug 28 10:53:00 PM UTC 24 |
| Finished | Aug 28 10:53:04 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921490593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1921490593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.464720808 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 403930748 ps |
| CPU time | 4.29 seconds |
| Started | Aug 28 10:53:00 PM UTC 24 |
| Finished | Aug 28 10:53:05 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464720808 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.464720808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.891422258 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 186044764 ps |
| CPU time | 4.49 seconds |
| Started | Aug 28 10:53:00 PM UTC 24 |
| Finished | Aug 28 10:53:05 PM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891422258 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.891422258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.4075782271 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 85924144 ps |
| CPU time | 4.1 seconds |
| Started | Aug 28 10:53:00 PM UTC 24 |
| Finished | Aug 28 10:53:05 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075782271 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4075782271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.2148352908 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1035807968 ps |
| CPU time | 16.74 seconds |
| Started | Aug 28 10:53:03 PM UTC 24 |
| Finished | Aug 28 10:53:21 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148352908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2148352908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.553903782 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 76527900 ps |
| CPU time | 3.84 seconds |
| Started | Aug 28 10:53:00 PM UTC 24 |
| Finished | Aug 28 10:53:05 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553903782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.553903782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.1463194052 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2140797832 ps |
| CPU time | 44.97 seconds |
| Started | Aug 28 10:53:03 PM UTC 24 |
| Finished | Aug 28 10:53:49 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463194052 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1463194052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.585798004 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 540641343 ps |
| CPU time | 4.73 seconds |
| Started | Aug 28 10:53:01 PM UTC 24 |
| Finished | Aug 28 10:53:07 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585798004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.585798004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.2634853024 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1021743289 ps |
| CPU time | 14.91 seconds |
| Started | Aug 28 10:53:03 PM UTC 24 |
| Finished | Aug 28 10:53:19 PM UTC 24 |
| Peak memory | 220264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634853024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2634853024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.1787167459 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 31075546 ps |
| CPU time | 1.54 seconds |
| Started | Aug 28 10:53:07 PM UTC 24 |
| Finished | Aug 28 10:53:10 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787167459 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1787167459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.2936110294 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 902813802 ps |
| CPU time | 8 seconds |
| Started | Aug 28 10:53:07 PM UTC 24 |
| Finished | Aug 28 10:53:16 PM UTC 24 |
| Peak memory | 231284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936110294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2936110294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.1417037727 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 163316748 ps |
| CPU time | 4.69 seconds |
| Started | Aug 28 10:53:06 PM UTC 24 |
| Finished | Aug 28 10:53:12 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417037727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1417037727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.766697645 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 33571094 ps |
| CPU time | 2.19 seconds |
| Started | Aug 28 10:53:06 PM UTC 24 |
| Finished | Aug 28 10:53:09 PM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766697645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.766697645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.1423112274 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 173816095 ps |
| CPU time | 4.87 seconds |
| Started | Aug 28 10:53:06 PM UTC 24 |
| Finished | Aug 28 10:53:12 PM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423112274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1423112274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_random.3020092549 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 547870860 ps |
| CPU time | 6.3 seconds |
| Started | Aug 28 10:53:05 PM UTC 24 |
| Finished | Aug 28 10:53:13 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020092549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3020092549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.671454047 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 638680053 ps |
| CPU time | 7.5 seconds |
| Started | Aug 28 10:53:04 PM UTC 24 |
| Finished | Aug 28 10:53:13 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671454047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.671454047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.1250642429 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 59195808 ps |
| CPU time | 2.73 seconds |
| Started | Aug 28 10:53:04 PM UTC 24 |
| Finished | Aug 28 10:53:08 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250642429 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1250642429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.446365839 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1486151274 ps |
| CPU time | 39.86 seconds |
| Started | Aug 28 10:53:04 PM UTC 24 |
| Finished | Aug 28 10:53:46 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446365839 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.446365839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.3100732550 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1285655776 ps |
| CPU time | 33.63 seconds |
| Started | Aug 28 10:53:05 PM UTC 24 |
| Finished | Aug 28 10:53:41 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100732550 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3100732550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.545929139 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 136866933 ps |
| CPU time | 2.77 seconds |
| Started | Aug 28 10:53:07 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545929139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.545929139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.3799988826 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 374942334 ps |
| CPU time | 3.83 seconds |
| Started | Aug 28 10:53:04 PM UTC 24 |
| Finished | Aug 28 10:53:09 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799988826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3799988826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.3400793234 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 493409580 ps |
| CPU time | 13.66 seconds |
| Started | Aug 28 10:53:07 PM UTC 24 |
| Finished | Aug 28 10:53:22 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400793234 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3400793234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.3748971869 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 980743574 ps |
| CPU time | 7.49 seconds |
| Started | Aug 28 10:53:06 PM UTC 24 |
| Finished | Aug 28 10:53:14 PM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748971869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3748971869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.1539018959 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 32453500 ps |
| CPU time | 2.59 seconds |
| Started | Aug 28 10:53:07 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539018959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1539018959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.3129744274 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 26680190 ps |
| CPU time | 1.09 seconds |
| Started | Aug 28 10:53:12 PM UTC 24 |
| Finished | Aug 28 10:53:15 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129744274 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3129744274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.1057088883 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 43613531 ps |
| CPU time | 3.35 seconds |
| Started | Aug 28 10:53:10 PM UTC 24 |
| Finished | Aug 28 10:53:14 PM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057088883 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1057088883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.1039299878 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 347602629 ps |
| CPU time | 7.82 seconds |
| Started | Aug 28 10:53:10 PM UTC 24 |
| Finished | Aug 28 10:53:19 PM UTC 24 |
| Peak memory | 220372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039299878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1039299878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.1116812537 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1213165343 ps |
| CPU time | 4.07 seconds |
| Started | Aug 28 10:53:11 PM UTC 24 |
| Finished | Aug 28 10:53:17 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116812537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1116812537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.1591816091 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 52334325 ps |
| CPU time | 3.7 seconds |
| Started | Aug 28 10:53:11 PM UTC 24 |
| Finished | Aug 28 10:53:16 PM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591816091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1591816091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.1479331275 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 112904385 ps |
| CPU time | 3.56 seconds |
| Started | Aug 28 10:53:10 PM UTC 24 |
| Finished | Aug 28 10:53:15 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479331275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1479331275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_random.1354359424 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 319301141 ps |
| CPU time | 7.18 seconds |
| Started | Aug 28 10:53:10 PM UTC 24 |
| Finished | Aug 28 10:53:18 PM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354359424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1354359424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.2086109533 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 23329530 ps |
| CPU time | 1.8 seconds |
| Started | Aug 28 10:53:08 PM UTC 24 |
| Finished | Aug 28 10:53:11 PM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086109533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2086109533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.1562865130 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 41995158 ps |
| CPU time | 2.2 seconds |
| Started | Aug 28 10:53:09 PM UTC 24 |
| Finished | Aug 28 10:53:12 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562865130 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1562865130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.3946803079 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 97939961 ps |
| CPU time | 3.59 seconds |
| Started | Aug 28 10:53:08 PM UTC 24 |
| Finished | Aug 28 10:53:13 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946803079 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3946803079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.4003637101 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 144299171 ps |
| CPU time | 2.89 seconds |
| Started | Aug 28 10:53:09 PM UTC 24 |
| Finished | Aug 28 10:53:13 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003637101 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4003637101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.373235481 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 443740163 ps |
| CPU time | 5.32 seconds |
| Started | Aug 28 10:53:12 PM UTC 24 |
| Finished | Aug 28 10:53:19 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373235481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.373235481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2767155833 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 93660812 ps |
| CPU time | 4.19 seconds |
| Started | Aug 28 10:53:08 PM UTC 24 |
| Finished | Aug 28 10:53:14 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767155833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2767155833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.1671173960 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 478573642 ps |
| CPU time | 13.21 seconds |
| Started | Aug 28 10:53:12 PM UTC 24 |
| Finished | Aug 28 10:53:27 PM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671173960 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1671173960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.885312489 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 132956492 ps |
| CPU time | 4.21 seconds |
| Started | Aug 28 10:53:10 PM UTC 24 |
| Finished | Aug 28 10:53:15 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885312489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.885312489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.3086617271 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 255032601 ps |
| CPU time | 2.53 seconds |
| Started | Aug 28 10:53:12 PM UTC 24 |
| Finished | Aug 28 10:53:16 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086617271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3086617271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.583731071 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 18403367 ps |
| CPU time | 1.1 seconds |
| Started | Aug 28 10:53:17 PM UTC 24 |
| Finished | Aug 28 10:53:19 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583731071 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.583731071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.1074042701 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 527733728 ps |
| CPU time | 8.07 seconds |
| Started | Aug 28 10:53:14 PM UTC 24 |
| Finished | Aug 28 10:53:23 PM UTC 24 |
| Peak memory | 232052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074042701 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1074042701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.1199710276 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 118226896 ps |
| CPU time | 3.05 seconds |
| Started | Aug 28 10:53:14 PM UTC 24 |
| Finished | Aug 28 10:53:18 PM UTC 24 |
| Peak memory | 216116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199710276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1199710276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.3951474454 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 141692284 ps |
| CPU time | 5.93 seconds |
| Started | Aug 28 10:53:15 PM UTC 24 |
| Finished | Aug 28 10:53:22 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951474454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3951474454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.4247598672 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 96379716 ps |
| CPU time | 2.93 seconds |
| Started | Aug 28 10:53:14 PM UTC 24 |
| Finished | Aug 28 10:53:18 PM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247598672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4247598672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_random.3948411833 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 475409820 ps |
| CPU time | 14.11 seconds |
| Started | Aug 28 10:53:14 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 219892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948411833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3948411833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.3729423809 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 200882942 ps |
| CPU time | 2.94 seconds |
| Started | Aug 28 10:53:13 PM UTC 24 |
| Finished | Aug 28 10:53:17 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729423809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3729423809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.137456101 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 38102925 ps |
| CPU time | 2.74 seconds |
| Started | Aug 28 10:53:13 PM UTC 24 |
| Finished | Aug 28 10:53:16 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137456101 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.137456101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.3841219887 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 3327769690 ps |
| CPU time | 32.86 seconds |
| Started | Aug 28 10:53:13 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841219887 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3841219887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.285542747 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 345922242 ps |
| CPU time | 11.39 seconds |
| Started | Aug 28 10:53:14 PM UTC 24 |
| Finished | Aug 28 10:53:26 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285542747 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.285542747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.2839008330 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 32585286 ps |
| CPU time | 2.55 seconds |
| Started | Aug 28 10:53:15 PM UTC 24 |
| Finished | Aug 28 10:53:19 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839008330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2839008330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.1957569748 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 330471649 ps |
| CPU time | 3.64 seconds |
| Started | Aug 28 10:53:13 PM UTC 24 |
| Finished | Aug 28 10:53:17 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957569748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1957569748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.4032999179 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1709171645 ps |
| CPU time | 31.56 seconds |
| Started | Aug 28 10:53:16 PM UTC 24 |
| Finished | Aug 28 10:53:48 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032999179 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4032999179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.2908857809 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 142382682 ps |
| CPU time | 5.5 seconds |
| Started | Aug 28 10:53:14 PM UTC 24 |
| Finished | Aug 28 10:53:21 PM UTC 24 |
| Peak memory | 230500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908857809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2908857809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.934131078 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 86760721 ps |
| CPU time | 2.88 seconds |
| Started | Aug 28 10:53:16 PM UTC 24 |
| Finished | Aug 28 10:53:19 PM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934131078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.934131078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.2548872330 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 22883532 ps |
| CPU time | 1.24 seconds |
| Started | Aug 28 10:53:21 PM UTC 24 |
| Finished | Aug 28 10:53:23 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548872330 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2548872330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.3567557835 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 147269414 ps |
| CPU time | 7.61 seconds |
| Started | Aug 28 10:53:18 PM UTC 24 |
| Finished | Aug 28 10:53:27 PM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567557835 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3567557835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.3871027516 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1165672722 ps |
| CPU time | 40.89 seconds |
| Started | Aug 28 10:53:18 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871027516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3871027516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.4091808599 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 152342751 ps |
| CPU time | 4.92 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:53:26 PM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091808599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4091808599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.3580395273 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 202031835 ps |
| CPU time | 6.49 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:53:27 PM UTC 24 |
| Peak memory | 226396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580395273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3580395273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.2646325575 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 326900051 ps |
| CPU time | 4.96 seconds |
| Started | Aug 28 10:53:19 PM UTC 24 |
| Finished | Aug 28 10:53:26 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646325575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2646325575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_random.4264950368 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 176669410 ps |
| CPU time | 3.98 seconds |
| Started | Aug 28 10:53:18 PM UTC 24 |
| Finished | Aug 28 10:53:23 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264950368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4264950368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.4070450170 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3229379856 ps |
| CPU time | 21.9 seconds |
| Started | Aug 28 10:53:17 PM UTC 24 |
| Finished | Aug 28 10:53:40 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070450170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4070450170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.1469340233 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 110175450 ps |
| CPU time | 4.01 seconds |
| Started | Aug 28 10:53:18 PM UTC 24 |
| Finished | Aug 28 10:53:23 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469340233 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1469340233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.4083414507 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 163739456 ps |
| CPU time | 2.67 seconds |
| Started | Aug 28 10:53:18 PM UTC 24 |
| Finished | Aug 28 10:53:22 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083414507 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4083414507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.886901966 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 806187165 ps |
| CPU time | 21.65 seconds |
| Started | Aug 28 10:53:18 PM UTC 24 |
| Finished | Aug 28 10:53:41 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886901966 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.886901966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.3120249057 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 138279852 ps |
| CPU time | 4.23 seconds |
| Started | Aug 28 10:53:17 PM UTC 24 |
| Finished | Aug 28 10:53:22 PM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120249057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3120249057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.4082135638 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2985873294 ps |
| CPU time | 38.5 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:54:00 PM UTC 24 |
| Peak memory | 232344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082135638 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4082135638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.2596973838 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 996467089 ps |
| CPU time | 7.48 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:53:28 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596973838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2596973838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.1347475776 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1470394390 ps |
| CPU time | 5.63 seconds |
| Started | Aug 28 10:53:20 PM UTC 24 |
| Finished | Aug 28 10:53:27 PM UTC 24 |
| Peak memory | 219840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347475776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1347475776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.3038736603 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 53836045 ps |
| CPU time | 1.33 seconds |
| Started | Aug 28 10:53:26 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038736603 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3038736603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.796651052 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 260363296 ps |
| CPU time | 4.41 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796651052 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.796651052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.3407481938 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 173748200 ps |
| CPU time | 4.1 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 232616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407481938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3407481938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.2479517463 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 236644782 ps |
| CPU time | 4.37 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479517463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2479517463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2654423593 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 97153078 ps |
| CPU time | 3.91 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654423593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2654423593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.1003437512 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1182363631 ps |
| CPU time | 4.98 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:30 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003437512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1003437512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_random.1517998500 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 154783622 ps |
| CPU time | 6.94 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:32 PM UTC 24 |
| Peak memory | 230260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517998500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1517998500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.1257853761 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 408462643 ps |
| CPU time | 4.84 seconds |
| Started | Aug 28 10:53:21 PM UTC 24 |
| Finished | Aug 28 10:53:27 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257853761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1257853761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.4005353507 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 57113695 ps |
| CPU time | 4.06 seconds |
| Started | Aug 28 10:53:22 PM UTC 24 |
| Finished | Aug 28 10:53:27 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005353507 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4005353507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.3696760930 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1208484853 ps |
| CPU time | 7.88 seconds |
| Started | Aug 28 10:53:22 PM UTC 24 |
| Finished | Aug 28 10:53:31 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696760930 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3696760930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.3993870036 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 174218547 ps |
| CPU time | 6.09 seconds |
| Started | Aug 28 10:53:22 PM UTC 24 |
| Finished | Aug 28 10:53:29 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993870036 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3993870036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.4033372614 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 80744499 ps |
| CPU time | 2.68 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:28 PM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033372614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4033372614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.2391194610 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 174071227 ps |
| CPU time | 3.23 seconds |
| Started | Aug 28 10:53:21 PM UTC 24 |
| Finished | Aug 28 10:53:25 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391194610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2391194610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.626986111 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3882658267 ps |
| CPU time | 49.62 seconds |
| Started | Aug 28 10:53:25 PM UTC 24 |
| Finished | Aug 28 10:54:16 PM UTC 24 |
| Peak memory | 231568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626986111 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.626986111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all_with_rand_reset.490446925 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1463343528 ps |
| CPU time | 12.24 seconds |
| Started | Aug 28 10:53:26 PM UTC 24 |
| Finished | Aug 28 10:53:39 PM UTC 24 |
| Peak memory | 232380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=490446925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr _stress_all_with_rand_reset.490446925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.3530174154 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 11328349317 ps |
| CPU time | 29.08 seconds |
| Started | Aug 28 10:53:24 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 230672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530174154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3530174154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.672841559 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1155937227 ps |
| CPU time | 7.02 seconds |
| Started | Aug 28 10:53:25 PM UTC 24 |
| Finished | Aug 28 10:53:33 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672841559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.672841559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.1747623961 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 14235439 ps |
| CPU time | 1.18 seconds |
| Started | Aug 28 10:53:31 PM UTC 24 |
| Finished | Aug 28 10:53:33 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747623961 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1747623961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.1699606707 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 97684667 ps |
| CPU time | 2.58 seconds |
| Started | Aug 28 10:53:28 PM UTC 24 |
| Finished | Aug 28 10:53:31 PM UTC 24 |
| Peak memory | 224360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699606707 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1699606707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.400871991 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 116351149 ps |
| CPU time | 4.51 seconds |
| Started | Aug 28 10:53:30 PM UTC 24 |
| Finished | Aug 28 10:53:36 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400871991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.400871991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.3110955403 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 349755312 ps |
| CPU time | 4.07 seconds |
| Started | Aug 28 10:53:29 PM UTC 24 |
| Finished | Aug 28 10:53:34 PM UTC 24 |
| Peak memory | 217916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110955403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3110955403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.3606666551 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1037300936 ps |
| CPU time | 8.07 seconds |
| Started | Aug 28 10:53:29 PM UTC 24 |
| Finished | Aug 28 10:53:38 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606666551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3606666551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.2769843734 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 539144007 ps |
| CPU time | 4.39 seconds |
| Started | Aug 28 10:53:29 PM UTC 24 |
| Finished | Aug 28 10:53:35 PM UTC 24 |
| Peak memory | 224300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769843734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2769843734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.2873443052 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2443521515 ps |
| CPU time | 7.68 seconds |
| Started | Aug 28 10:53:29 PM UTC 24 |
| Finished | Aug 28 10:53:38 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873443052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2873443052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_random.1130222598 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 60701769 ps |
| CPU time | 3.29 seconds |
| Started | Aug 28 10:53:28 PM UTC 24 |
| Finished | Aug 28 10:53:32 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130222598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1130222598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.344212302 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 109818451 ps |
| CPU time | 5.72 seconds |
| Started | Aug 28 10:53:28 PM UTC 24 |
| Finished | Aug 28 10:53:34 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344212302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.344212302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.2949218121 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2723953812 ps |
| CPU time | 7.2 seconds |
| Started | Aug 28 10:53:28 PM UTC 24 |
| Finished | Aug 28 10:53:36 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949218121 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2949218121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.3964636669 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 82462459 ps |
| CPU time | 3.9 seconds |
| Started | Aug 28 10:53:28 PM UTC 24 |
| Finished | Aug 28 10:53:32 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964636669 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3964636669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.1636741091 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 700714480 ps |
| CPU time | 21.17 seconds |
| Started | Aug 28 10:53:28 PM UTC 24 |
| Finished | Aug 28 10:53:50 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636741091 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1636741091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.385255941 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 87623959 ps |
| CPU time | 3.98 seconds |
| Started | Aug 28 10:53:30 PM UTC 24 |
| Finished | Aug 28 10:53:35 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385255941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.385255941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.4052401356 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 19701424 ps |
| CPU time | 2.42 seconds |
| Started | Aug 28 10:53:26 PM UTC 24 |
| Finished | Aug 28 10:53:30 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052401356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.4052401356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.597835983 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1319648324 ps |
| CPU time | 10.56 seconds |
| Started | Aug 28 10:53:29 PM UTC 24 |
| Finished | Aug 28 10:53:41 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597835983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.597835983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.1448970308 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 46780282 ps |
| CPU time | 1.44 seconds |
| Started | Aug 28 10:53:36 PM UTC 24 |
| Finished | Aug 28 10:53:38 PM UTC 24 |
| Peak memory | 213660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448970308 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1448970308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.1482885412 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 115087829 ps |
| CPU time | 3.14 seconds |
| Started | Aug 28 10:53:32 PM UTC 24 |
| Finished | Aug 28 10:53:36 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482885412 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1482885412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.1131346728 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 82099146 ps |
| CPU time | 5.11 seconds |
| Started | Aug 28 10:53:35 PM UTC 24 |
| Finished | Aug 28 10:53:41 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131346728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1131346728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.4155233336 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 887759556 ps |
| CPU time | 11.15 seconds |
| Started | Aug 28 10:53:32 PM UTC 24 |
| Finished | Aug 28 10:53:44 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155233336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4155233336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.2716400715 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 141622228 ps |
| CPU time | 3.34 seconds |
| Started | Aug 28 10:53:33 PM UTC 24 |
| Finished | Aug 28 10:53:38 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716400715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2716400715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.1430413174 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 129824992 ps |
| CPU time | 4.69 seconds |
| Started | Aug 28 10:53:33 PM UTC 24 |
| Finished | Aug 28 10:53:39 PM UTC 24 |
| Peak memory | 232104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430413174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1430413174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.903322519 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1309063718 ps |
| CPU time | 6.08 seconds |
| Started | Aug 28 10:53:33 PM UTC 24 |
| Finished | Aug 28 10:53:40 PM UTC 24 |
| Peak memory | 220132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903322519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.903322519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_random.2823115903 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 488690770 ps |
| CPU time | 13.94 seconds |
| Started | Aug 28 10:53:32 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 219968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823115903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2823115903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.2928478293 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 177213095 ps |
| CPU time | 7.01 seconds |
| Started | Aug 28 10:53:31 PM UTC 24 |
| Finished | Aug 28 10:53:39 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928478293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2928478293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.3839696883 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 256631591 ps |
| CPU time | 6.53 seconds |
| Started | Aug 28 10:53:32 PM UTC 24 |
| Finished | Aug 28 10:53:40 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839696883 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3839696883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.3131322738 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 105380242 ps |
| CPU time | 3.63 seconds |
| Started | Aug 28 10:53:31 PM UTC 24 |
| Finished | Aug 28 10:53:36 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131322738 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3131322738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.646537130 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 261457770 ps |
| CPU time | 7.26 seconds |
| Started | Aug 28 10:53:32 PM UTC 24 |
| Finished | Aug 28 10:53:40 PM UTC 24 |
| Peak memory | 217812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646537130 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.646537130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.2857331860 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 63805254 ps |
| CPU time | 4.05 seconds |
| Started | Aug 28 10:53:35 PM UTC 24 |
| Finished | Aug 28 10:53:40 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857331860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2857331860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.737061992 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 977192815 ps |
| CPU time | 4.26 seconds |
| Started | Aug 28 10:53:31 PM UTC 24 |
| Finished | Aug 28 10:53:36 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737061992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.737061992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.645511711 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 22793138754 ps |
| CPU time | 315.21 seconds |
| Started | Aug 28 10:53:36 PM UTC 24 |
| Finished | Aug 28 10:58:55 PM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645511711 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.645511711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.900825408 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 513257242 ps |
| CPU time | 5.55 seconds |
| Started | Aug 28 10:53:33 PM UTC 24 |
| Finished | Aug 28 10:53:40 PM UTC 24 |
| Peak memory | 224116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900825408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.900825408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.3453548771 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 218173839 ps |
| CPU time | 3.11 seconds |
| Started | Aug 28 10:53:36 PM UTC 24 |
| Finished | Aug 28 10:53:40 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453548771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3453548771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.1828067660 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 34125110 ps |
| CPU time | 1.31 seconds |
| Started | Aug 28 10:53:41 PM UTC 24 |
| Finished | Aug 28 10:53:44 PM UTC 24 |
| Peak memory | 213660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828067660 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1828067660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.701296136 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 53114531 ps |
| CPU time | 3.15 seconds |
| Started | Aug 28 10:53:38 PM UTC 24 |
| Finished | Aug 28 10:53:42 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701296136 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.701296136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.172555931 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 521999666 ps |
| CPU time | 5.52 seconds |
| Started | Aug 28 10:53:38 PM UTC 24 |
| Finished | Aug 28 10:53:45 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172555931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.172555931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.3231249649 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 52914058 ps |
| CPU time | 4.42 seconds |
| Started | Aug 28 10:53:40 PM UTC 24 |
| Finished | Aug 28 10:53:45 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231249649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3231249649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.3309259757 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 287006324 ps |
| CPU time | 2.78 seconds |
| Started | Aug 28 10:53:40 PM UTC 24 |
| Finished | Aug 28 10:53:44 PM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309259757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3309259757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.2801785428 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 41526939 ps |
| CPU time | 2.47 seconds |
| Started | Aug 28 10:53:40 PM UTC 24 |
| Finished | Aug 28 10:53:43 PM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801785428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2801785428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_random.1010016399 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 434148233 ps |
| CPU time | 5.58 seconds |
| Started | Aug 28 10:53:37 PM UTC 24 |
| Finished | Aug 28 10:53:44 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010016399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1010016399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.1459002167 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 8611145624 ps |
| CPU time | 22.61 seconds |
| Started | Aug 28 10:53:37 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 218012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459002167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1459002167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.88621153 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 795919430 ps |
| CPU time | 5.12 seconds |
| Started | Aug 28 10:53:37 PM UTC 24 |
| Finished | Aug 28 10:53:43 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88621153 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.88621153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.2590497534 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 121175380 ps |
| CPU time | 3.18 seconds |
| Started | Aug 28 10:53:37 PM UTC 24 |
| Finished | Aug 28 10:53:41 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590497534 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2590497534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.4001748424 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 68679078 ps |
| CPU time | 3.52 seconds |
| Started | Aug 28 10:53:37 PM UTC 24 |
| Finished | Aug 28 10:53:42 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001748424 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4001748424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.2237320599 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 36280288 ps |
| CPU time | 1.93 seconds |
| Started | Aug 28 10:53:40 PM UTC 24 |
| Finished | Aug 28 10:53:43 PM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237320599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2237320599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.3748564734 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 59972336 ps |
| CPU time | 3.51 seconds |
| Started | Aug 28 10:53:37 PM UTC 24 |
| Finished | Aug 28 10:53:42 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748564734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3748564734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.2437703463 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3012513269 ps |
| CPU time | 30.97 seconds |
| Started | Aug 28 10:53:41 PM UTC 24 |
| Finished | Aug 28 10:54:14 PM UTC 24 |
| Peak memory | 231128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437703463 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2437703463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.678325451 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 330306274 ps |
| CPU time | 8.09 seconds |
| Started | Aug 28 10:53:40 PM UTC 24 |
| Finished | Aug 28 10:53:49 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678325451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.678325451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.821091160 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 47805853 ps |
| CPU time | 2.23 seconds |
| Started | Aug 28 10:53:40 PM UTC 24 |
| Finished | Aug 28 10:53:43 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821091160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.821091160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.2592186786 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 14255812 ps |
| CPU time | 1.42 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:51:24 PM UTC 24 |
| Peak memory | 213720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592186786 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2592186786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.1906080102 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 204839936 ps |
| CPU time | 7.5 seconds |
| Started | Aug 28 10:51:19 PM UTC 24 |
| Finished | Aug 28 10:51:27 PM UTC 24 |
| Peak memory | 218388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906080102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1906080102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.2366085882 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 116174238 ps |
| CPU time | 2.32 seconds |
| Started | Aug 28 10:51:18 PM UTC 24 |
| Finished | Aug 28 10:51:23 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366085882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2366085882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.3414289856 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 84744083 ps |
| CPU time | 2.72 seconds |
| Started | Aug 28 10:51:19 PM UTC 24 |
| Finished | Aug 28 10:51:22 PM UTC 24 |
| Peak memory | 232288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414289856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3414289856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_random.1891748941 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 296228781 ps |
| CPU time | 7.03 seconds |
| Started | Aug 28 10:51:18 PM UTC 24 |
| Finished | Aug 28 10:51:27 PM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891748941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1891748941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.838185691 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1562839371 ps |
| CPU time | 9.57 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:51:32 PM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838185691 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.838185691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.3180766445 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 91749057 ps |
| CPU time | 3.4 seconds |
| Started | Aug 28 10:51:16 PM UTC 24 |
| Finished | Aug 28 10:51:20 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180766445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3180766445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.2314983010 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 24367201 ps |
| CPU time | 2.29 seconds |
| Started | Aug 28 10:51:16 PM UTC 24 |
| Finished | Aug 28 10:51:19 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314983010 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2314983010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.3639232762 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 76134358 ps |
| CPU time | 4.02 seconds |
| Started | Aug 28 10:51:16 PM UTC 24 |
| Finished | Aug 28 10:51:21 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639232762 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3639232762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.4264869648 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 33186887 ps |
| CPU time | 1.85 seconds |
| Started | Aug 28 10:51:19 PM UTC 24 |
| Finished | Aug 28 10:51:23 PM UTC 24 |
| Peak memory | 214296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264869648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4264869648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.3145391540 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 243932516 ps |
| CPU time | 2.96 seconds |
| Started | Aug 28 10:51:16 PM UTC 24 |
| Finished | Aug 28 10:51:20 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145391540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3145391540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.1025207365 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 142602358 ps |
| CPU time | 4.82 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:51:27 PM UTC 24 |
| Peak memory | 219904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025207365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1025207365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.2305772898 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 11186472 ps |
| CPU time | 1.07 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305772898 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2305772898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.503591529 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 390223029 ps |
| CPU time | 3.66 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 219992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503591529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.503591529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.167271321 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 49422739 ps |
| CPU time | 2.41 seconds |
| Started | Aug 28 10:53:43 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167271321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.167271321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_random.9031368 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 197385366 ps |
| CPU time | 8.32 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:51 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9031368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.9031368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.256209337 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 23497958 ps |
| CPU time | 1.98 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:45 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256209337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.256209337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.3305522235 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 495584953 ps |
| CPU time | 4.68 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305522235 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3305522235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.2456201282 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 935034592 ps |
| CPU time | 9.86 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:53 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456201282 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2456201282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.1976169775 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 114277399 ps |
| CPU time | 3.91 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976169775 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1976169775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.4257015216 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 123519758 ps |
| CPU time | 3.67 seconds |
| Started | Aug 28 10:53:43 PM UTC 24 |
| Finished | Aug 28 10:53:48 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257015216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4257015216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.2593310511 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 708284728 ps |
| CPU time | 4.22 seconds |
| Started | Aug 28 10:53:41 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593310511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2593310511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.3327827657 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6931224060 ps |
| CPU time | 50.87 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:54:37 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327827657 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3327827657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.744944569 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 58492523 ps |
| CPU time | 4.35 seconds |
| Started | Aug 28 10:53:42 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744944569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.744944569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.2711444700 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 71729373 ps |
| CPU time | 2.82 seconds |
| Started | Aug 28 10:53:43 PM UTC 24 |
| Finished | Aug 28 10:53:47 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711444700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2711444700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.671684373 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 21785426 ps |
| CPU time | 1.17 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:50 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671684373 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.671684373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.459588762 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 166856906 ps |
| CPU time | 3.5 seconds |
| Started | Aug 28 10:53:46 PM UTC 24 |
| Finished | Aug 28 10:53:51 PM UTC 24 |
| Peak memory | 226072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459588762 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.459588762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.776924383 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 150325472 ps |
| CPU time | 4.88 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776924383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.776924383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.3234757706 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 183223242 ps |
| CPU time | 3.32 seconds |
| Started | Aug 28 10:53:46 PM UTC 24 |
| Finished | Aug 28 10:53:51 PM UTC 24 |
| Peak memory | 224292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234757706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3234757706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.807630921 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 364010213 ps |
| CPU time | 6.03 seconds |
| Started | Aug 28 10:53:46 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807630921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.807630921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.2197545768 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 579213395 ps |
| CPU time | 7.72 seconds |
| Started | Aug 28 10:53:46 PM UTC 24 |
| Finished | Aug 28 10:53:55 PM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197545768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2197545768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_random.331306438 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 816258714 ps |
| CPU time | 6.26 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:53:52 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331306438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.331306438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.641995688 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 388481903 ps |
| CPU time | 5.72 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:53:52 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641995688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.641995688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.156158479 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 71837201 ps |
| CPU time | 3.81 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:53:50 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156158479 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.156158479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.2733715377 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 291105535 ps |
| CPU time | 4.12 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:53:50 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733715377 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2733715377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.3631154664 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 171945772 ps |
| CPU time | 2.56 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:53:49 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631154664 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3631154664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.3351764772 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 47702666 ps |
| CPU time | 3.15 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:52 PM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351764772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3351764772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.810008196 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 231371584 ps |
| CPU time | 5.59 seconds |
| Started | Aug 28 10:53:45 PM UTC 24 |
| Finished | Aug 28 10:53:51 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810008196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.810008196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.2319179611 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 25280771961 ps |
| CPU time | 312.49 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:59:05 PM UTC 24 |
| Peak memory | 230568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319179611 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2319179611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all_with_rand_reset.3569444176 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 271009331 ps |
| CPU time | 11.09 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:54:00 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3569444176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymg r_stress_all_with_rand_reset.3569444176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.143105064 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1796314737 ps |
| CPU time | 6.24 seconds |
| Started | Aug 28 10:53:46 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143105064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.143105064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.88556785 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 355801742 ps |
| CPU time | 3.91 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:53 PM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88556785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.88556785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.85670099 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 39317383 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:53:52 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85670099 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.85670099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.542768763 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 211768546 ps |
| CPU time | 3.93 seconds |
| Started | Aug 28 10:53:49 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542768763 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.542768763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.685448669 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 76313694 ps |
| CPU time | 4.1 seconds |
| Started | Aug 28 10:53:51 PM UTC 24 |
| Finished | Aug 28 10:53:56 PM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685448669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.685448669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.4052942815 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 68225472 ps |
| CPU time | 3.54 seconds |
| Started | Aug 28 10:53:50 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052942815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4052942815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.3607966508 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 904873614 ps |
| CPU time | 3.31 seconds |
| Started | Aug 28 10:53:50 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607966508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3607966508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.1750595484 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 203480923 ps |
| CPU time | 4.13 seconds |
| Started | Aug 28 10:53:51 PM UTC 24 |
| Finished | Aug 28 10:53:56 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750595484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1750595484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.4256830984 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 139809871 ps |
| CPU time | 7.19 seconds |
| Started | Aug 28 10:53:50 PM UTC 24 |
| Finished | Aug 28 10:53:58 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256830984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.4256830984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_random.1539188310 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 669339755 ps |
| CPU time | 7.09 seconds |
| Started | Aug 28 10:53:49 PM UTC 24 |
| Finished | Aug 28 10:53:58 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539188310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1539188310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.1241596209 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 765303604 ps |
| CPU time | 6.83 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:56 PM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241596209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1241596209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.451284130 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 226047324 ps |
| CPU time | 4.93 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:54 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451284130 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.451284130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.1068681315 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 111815034 ps |
| CPU time | 3.06 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:52 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068681315 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1068681315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.3714456916 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1049738252 ps |
| CPU time | 16.05 seconds |
| Started | Aug 28 10:53:49 PM UTC 24 |
| Finished | Aug 28 10:54:07 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714456916 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3714456916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.358981930 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 33564413 ps |
| CPU time | 2.81 seconds |
| Started | Aug 28 10:53:51 PM UTC 24 |
| Finished | Aug 28 10:53:55 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358981930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.358981930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.4141994695 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 405665370 ps |
| CPU time | 7.41 seconds |
| Started | Aug 28 10:53:48 PM UTC 24 |
| Finished | Aug 28 10:53:57 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141994695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4141994695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.1977814365 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 916332888 ps |
| CPU time | 20.95 seconds |
| Started | Aug 28 10:53:51 PM UTC 24 |
| Finished | Aug 28 10:54:13 PM UTC 24 |
| Peak memory | 226200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977814365 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1977814365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all_with_rand_reset.3495179682 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 114115759 ps |
| CPU time | 11.29 seconds |
| Started | Aug 28 10:53:51 PM UTC 24 |
| Finished | Aug 28 10:54:04 PM UTC 24 |
| Peak memory | 232632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3495179682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymg r_stress_all_with_rand_reset.3495179682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1977930164 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 48829749 ps |
| CPU time | 2.1 seconds |
| Started | Aug 28 10:53:50 PM UTC 24 |
| Finished | Aug 28 10:53:53 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977930164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1977930164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.4127043505 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 9019030 ps |
| CPU time | 1.14 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:53:58 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127043505 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4127043505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.2458605114 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 68561351 ps |
| CPU time | 4.48 seconds |
| Started | Aug 28 10:53:54 PM UTC 24 |
| Finished | Aug 28 10:53:59 PM UTC 24 |
| Peak memory | 226520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458605114 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2458605114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.348251566 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 282130585 ps |
| CPU time | 5.68 seconds |
| Started | Aug 28 10:53:55 PM UTC 24 |
| Finished | Aug 28 10:54:02 PM UTC 24 |
| Peak memory | 232964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348251566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.348251566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.1530361605 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4858684000 ps |
| CPU time | 30.31 seconds |
| Started | Aug 28 10:53:54 PM UTC 24 |
| Finished | Aug 28 10:54:25 PM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530361605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1530361605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.1716472303 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1087691449 ps |
| CPU time | 25.88 seconds |
| Started | Aug 28 10:53:54 PM UTC 24 |
| Finished | Aug 28 10:54:21 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716472303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1716472303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.3227863234 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 116580251 ps |
| CPU time | 5.98 seconds |
| Started | Aug 28 10:53:54 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 230192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227863234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3227863234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_random.1687750085 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4153584240 ps |
| CPU time | 28 seconds |
| Started | Aug 28 10:53:53 PM UTC 24 |
| Finished | Aug 28 10:54:22 PM UTC 24 |
| Peak memory | 224188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687750085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1687750085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.2989477668 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 247095893 ps |
| CPU time | 3.39 seconds |
| Started | Aug 28 10:53:52 PM UTC 24 |
| Finished | Aug 28 10:53:57 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989477668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2989477668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.730363262 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 33925633 ps |
| CPU time | 2.67 seconds |
| Started | Aug 28 10:53:53 PM UTC 24 |
| Finished | Aug 28 10:53:56 PM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730363262 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.730363262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.918319894 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 467256261 ps |
| CPU time | 7.48 seconds |
| Started | Aug 28 10:53:52 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918319894 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.918319894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.902835939 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 293752967 ps |
| CPU time | 5.93 seconds |
| Started | Aug 28 10:53:53 PM UTC 24 |
| Finished | Aug 28 10:54:00 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902835939 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.902835939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.16987071 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 503762582 ps |
| CPU time | 3.74 seconds |
| Started | Aug 28 10:53:55 PM UTC 24 |
| Finished | Aug 28 10:54:00 PM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16987071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.16987071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.651494542 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 75464003 ps |
| CPU time | 3.18 seconds |
| Started | Aug 28 10:53:52 PM UTC 24 |
| Finished | Aug 28 10:53:57 PM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651494542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.651494542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.1030174845 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1682626133 ps |
| CPU time | 42.62 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030174845 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1030174845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.191231556 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 508609337 ps |
| CPU time | 24 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:54:21 PM UTC 24 |
| Peak memory | 232712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=191231556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr _stress_all_with_rand_reset.191231556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.69269847 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1574041361 ps |
| CPU time | 57.29 seconds |
| Started | Aug 28 10:53:54 PM UTC 24 |
| Finished | Aug 28 10:54:53 PM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69269847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.69269847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.488545813 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 246430663 ps |
| CPU time | 3.96 seconds |
| Started | Aug 28 10:53:55 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 219944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488545813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.488545813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.1452659054 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 9498455 ps |
| CPU time | 1.07 seconds |
| Started | Aug 28 10:54:00 PM UTC 24 |
| Finished | Aug 28 10:54:02 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452659054 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1452659054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.2506882236 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 47498917 ps |
| CPU time | 3.94 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:02 PM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506882236 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2506882236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.3775077876 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 110261915 ps |
| CPU time | 2.76 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 224144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775077876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3775077876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.726233499 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 97237672 ps |
| CPU time | 3.47 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:02 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726233499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.726233499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.2184735966 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 291092554 ps |
| CPU time | 5.02 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:03 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184735966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2184735966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.76278623 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 99925755 ps |
| CPU time | 4.41 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:03 PM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76278623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.76278623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.3657891881 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 556654215 ps |
| CPU time | 3.01 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657891881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3657891881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_random.3556313846 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 96626445 ps |
| CPU time | 3.51 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556313846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3556313846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.2225659846 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1559917221 ps |
| CPU time | 5.85 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:54:03 PM UTC 24 |
| Peak memory | 218240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225659846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2225659846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.676420120 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 64124436 ps |
| CPU time | 4.15 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:54:01 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676420120 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.676420120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.2361847252 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 262437118 ps |
| CPU time | 5.02 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:54:02 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361847252 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2361847252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.3744633439 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 87686282 ps |
| CPU time | 2.11 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:53:59 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744633439 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3744633439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.1686599419 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 147041534 ps |
| CPU time | 4.41 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:03 PM UTC 24 |
| Peak memory | 230236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686599419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1686599419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.1796021633 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 678208871 ps |
| CPU time | 11.22 seconds |
| Started | Aug 28 10:53:56 PM UTC 24 |
| Finished | Aug 28 10:54:08 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796021633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1796021633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.478523676 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 888773546 ps |
| CPU time | 31.18 seconds |
| Started | Aug 28 10:53:59 PM UTC 24 |
| Finished | Aug 28 10:54:31 PM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478523676 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.478523676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.2269318040 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 228765178 ps |
| CPU time | 8.41 seconds |
| Started | Aug 28 10:53:59 PM UTC 24 |
| Finished | Aug 28 10:54:08 PM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2269318040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymg r_stress_all_with_rand_reset.2269318040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.10689093 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2457214420 ps |
| CPU time | 5.35 seconds |
| Started | Aug 28 10:53:57 PM UTC 24 |
| Finished | Aug 28 10:54:04 PM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10689093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.10689093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.3185500289 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 446135292 ps |
| CPU time | 3.42 seconds |
| Started | Aug 28 10:53:59 PM UTC 24 |
| Finished | Aug 28 10:54:03 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185500289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3185500289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.1322739571 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 25668279 ps |
| CPU time | 1.38 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:05 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322739571 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1322739571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.1364093406 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 121566106 ps |
| CPU time | 7.91 seconds |
| Started | Aug 28 10:54:01 PM UTC 24 |
| Finished | Aug 28 10:54:10 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364093406 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1364093406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.3703624109 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 303957515 ps |
| CPU time | 3.17 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:07 PM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703624109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3703624109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.1450939911 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 137157478 ps |
| CPU time | 4.17 seconds |
| Started | Aug 28 10:54:01 PM UTC 24 |
| Finished | Aug 28 10:54:07 PM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450939911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1450939911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.2098523063 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 255465648 ps |
| CPU time | 4.45 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:08 PM UTC 24 |
| Peak memory | 223784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098523063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2098523063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.2121753104 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 151054589 ps |
| CPU time | 5.62 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:10 PM UTC 24 |
| Peak memory | 232448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121753104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2121753104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.2855626860 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 52961685 ps |
| CPU time | 3.87 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:08 PM UTC 24 |
| Peak memory | 228572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855626860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2855626860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_random.3594904682 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 61359864 ps |
| CPU time | 3.55 seconds |
| Started | Aug 28 10:54:01 PM UTC 24 |
| Finished | Aug 28 10:54:06 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594904682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3594904682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.1276003837 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 504480083 ps |
| CPU time | 3.11 seconds |
| Started | Aug 28 10:54:01 PM UTC 24 |
| Finished | Aug 28 10:54:05 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276003837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1276003837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.1830316871 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 59459478 ps |
| CPU time | 3.92 seconds |
| Started | Aug 28 10:54:01 PM UTC 24 |
| Finished | Aug 28 10:54:06 PM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830316871 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1830316871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.207046632 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 154574188 ps |
| CPU time | 2.79 seconds |
| Started | Aug 28 10:54:01 PM UTC 24 |
| Finished | Aug 28 10:54:05 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207046632 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.207046632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.3931158819 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 127026582 ps |
| CPU time | 4.52 seconds |
| Started | Aug 28 10:54:01 PM UTC 24 |
| Finished | Aug 28 10:54:07 PM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931158819 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3931158819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.4059939051 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 328283911 ps |
| CPU time | 3.29 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:07 PM UTC 24 |
| Peak memory | 216088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059939051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4059939051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.650467408 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 536198246 ps |
| CPU time | 3.11 seconds |
| Started | Aug 28 10:54:00 PM UTC 24 |
| Finished | Aug 28 10:54:04 PM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650467408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.650467408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.778996206 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 268931556 ps |
| CPU time | 14.84 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:19 PM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=778996206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr _stress_all_with_rand_reset.778996206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.1521140525 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 131130207 ps |
| CPU time | 4.06 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:08 PM UTC 24 |
| Peak memory | 223812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521140525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1521140525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.4113415564 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 387849720 ps |
| CPU time | 3.09 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:07 PM UTC 24 |
| Peak memory | 220264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113415564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4113415564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.3584828967 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 13146336 ps |
| CPU time | 1.1 seconds |
| Started | Aug 28 10:54:07 PM UTC 24 |
| Finished | Aug 28 10:54:10 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584828967 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3584828967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.4027790267 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 142297451 ps |
| CPU time | 3.49 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:09 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027790267 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.4027790267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.1233832056 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 50486504 ps |
| CPU time | 3.78 seconds |
| Started | Aug 28 10:54:06 PM UTC 24 |
| Finished | Aug 28 10:54:11 PM UTC 24 |
| Peak memory | 231360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233832056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1233832056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.1882924788 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 427042993 ps |
| CPU time | 2.28 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:08 PM UTC 24 |
| Peak memory | 216052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882924788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1882924788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.1225765061 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 155214957 ps |
| CPU time | 3.36 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:09 PM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225765061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1225765061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.2619208351 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 195535887 ps |
| CPU time | 9.89 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:16 PM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619208351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2619208351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.561910393 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 487323806 ps |
| CPU time | 6.04 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:12 PM UTC 24 |
| Peak memory | 230260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561910393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.561910393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_random.1199694308 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 460326533 ps |
| CPU time | 9.37 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:15 PM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199694308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1199694308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.1000064547 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 221190477 ps |
| CPU time | 3.54 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:08 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000064547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1000064547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.4183617353 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 144845503 ps |
| CPU time | 3.05 seconds |
| Started | Aug 28 10:54:04 PM UTC 24 |
| Finished | Aug 28 10:54:09 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183617353 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4183617353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.3022545625 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 160670891 ps |
| CPU time | 5.04 seconds |
| Started | Aug 28 10:54:03 PM UTC 24 |
| Finished | Aug 28 10:54:09 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022545625 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3022545625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.783946850 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 34621229 ps |
| CPU time | 3.09 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:09 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783946850 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.783946850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.2971160799 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 100973973 ps |
| CPU time | 2.47 seconds |
| Started | Aug 28 10:54:06 PM UTC 24 |
| Finished | Aug 28 10:54:09 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971160799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2971160799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.1972135596 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1860933886 ps |
| CPU time | 11.55 seconds |
| Started | Aug 28 10:54:06 PM UTC 24 |
| Finished | Aug 28 10:54:19 PM UTC 24 |
| Peak memory | 230292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972135596 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1972135596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all_with_rand_reset.1882835755 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 387719432 ps |
| CPU time | 8.48 seconds |
| Started | Aug 28 10:54:07 PM UTC 24 |
| Finished | Aug 28 10:54:17 PM UTC 24 |
| Peak memory | 232504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1882835755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymg r_stress_all_with_rand_reset.1882835755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.127780389 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 163722899 ps |
| CPU time | 4.2 seconds |
| Started | Aug 28 10:54:05 PM UTC 24 |
| Finished | Aug 28 10:54:10 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127780389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.127780389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.734176705 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 91999094 ps |
| CPU time | 3.13 seconds |
| Started | Aug 28 10:54:06 PM UTC 24 |
| Finished | Aug 28 10:54:10 PM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734176705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.734176705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.879283890 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 85197078 ps |
| CPU time | 1.32 seconds |
| Started | Aug 28 10:54:11 PM UTC 24 |
| Finished | Aug 28 10:54:14 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879283890 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.879283890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.1156157072 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 66406281 ps |
| CPU time | 4.47 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:15 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156157072 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1156157072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.3971173340 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 964570074 ps |
| CPU time | 3.87 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:14 PM UTC 24 |
| Peak memory | 232628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971173340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3971173340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.1216845875 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 27271693 ps |
| CPU time | 2.31 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:12 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216845875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1216845875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.795222949 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 106081826 ps |
| CPU time | 4.74 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:15 PM UTC 24 |
| Peak memory | 223804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795222949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.795222949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.1662267071 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 60737280 ps |
| CPU time | 3.73 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:14 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662267071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1662267071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.3716743292 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 692211320 ps |
| CPU time | 3.83 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:14 PM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716743292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3716743292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_random.915182924 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 104290767 ps |
| CPU time | 6.38 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:16 PM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915182924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.915182924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.1053650916 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 62219374 ps |
| CPU time | 3.8 seconds |
| Started | Aug 28 10:54:07 PM UTC 24 |
| Finished | Aug 28 10:54:12 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053650916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1053650916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.3169545879 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 278198030 ps |
| CPU time | 6.35 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:16 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169545879 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3169545879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.1299956529 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 867301746 ps |
| CPU time | 17.61 seconds |
| Started | Aug 28 10:54:08 PM UTC 24 |
| Finished | Aug 28 10:54:26 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299956529 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1299956529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.1606138862 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 93937811 ps |
| CPU time | 3.62 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:13 PM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606138862 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1606138862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.85729911 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 858175929 ps |
| CPU time | 4.32 seconds |
| Started | Aug 28 10:54:10 PM UTC 24 |
| Finished | Aug 28 10:54:16 PM UTC 24 |
| Peak memory | 228528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85729911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.85729911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.3424329153 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 70160483 ps |
| CPU time | 2.98 seconds |
| Started | Aug 28 10:54:07 PM UTC 24 |
| Finished | Aug 28 10:54:11 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424329153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3424329153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.2764218379 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 424441036 ps |
| CPU time | 18.74 seconds |
| Started | Aug 28 10:54:11 PM UTC 24 |
| Finished | Aug 28 10:54:31 PM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2764218379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymg r_stress_all_with_rand_reset.2764218379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.1502476097 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2873768469 ps |
| CPU time | 14.16 seconds |
| Started | Aug 28 10:54:09 PM UTC 24 |
| Finished | Aug 28 10:54:25 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502476097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1502476097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.1338468004 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 117184653 ps |
| CPU time | 2.13 seconds |
| Started | Aug 28 10:54:10 PM UTC 24 |
| Finished | Aug 28 10:54:14 PM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338468004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1338468004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.1653433553 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 44486337 ps |
| CPU time | 1.02 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:18 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653433553 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1653433553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.313921751 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1870740343 ps |
| CPU time | 7.19 seconds |
| Started | Aug 28 10:54:12 PM UTC 24 |
| Finished | Aug 28 10:54:20 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313921751 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.313921751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.3358823291 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2266675349 ps |
| CPU time | 13.31 seconds |
| Started | Aug 28 10:54:12 PM UTC 24 |
| Finished | Aug 28 10:54:27 PM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358823291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3358823291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.2295559702 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 299161885 ps |
| CPU time | 3.56 seconds |
| Started | Aug 28 10:54:13 PM UTC 24 |
| Finished | Aug 28 10:54:18 PM UTC 24 |
| Peak memory | 224108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295559702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2295559702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.2019857168 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 106377766 ps |
| CPU time | 2.85 seconds |
| Started | Aug 28 10:54:13 PM UTC 24 |
| Finished | Aug 28 10:54:17 PM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019857168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2019857168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_random.2008629787 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1081051504 ps |
| CPU time | 8.73 seconds |
| Started | Aug 28 10:54:12 PM UTC 24 |
| Finished | Aug 28 10:54:22 PM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008629787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2008629787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.2263748437 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 615969682 ps |
| CPU time | 17.57 seconds |
| Started | Aug 28 10:54:11 PM UTC 24 |
| Finished | Aug 28 10:54:30 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263748437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2263748437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.1388893015 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 118948427 ps |
| CPU time | 3.71 seconds |
| Started | Aug 28 10:54:11 PM UTC 24 |
| Finished | Aug 28 10:54:16 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388893015 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1388893015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.347897251 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 43293971 ps |
| CPU time | 2.83 seconds |
| Started | Aug 28 10:54:11 PM UTC 24 |
| Finished | Aug 28 10:54:15 PM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347897251 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.347897251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.2451099337 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 188690567 ps |
| CPU time | 3.17 seconds |
| Started | Aug 28 10:54:12 PM UTC 24 |
| Finished | Aug 28 10:54:16 PM UTC 24 |
| Peak memory | 216032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451099337 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2451099337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.1778529700 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 252308000 ps |
| CPU time | 4.44 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:21 PM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778529700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1778529700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.3183574099 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 284023151 ps |
| CPU time | 4.82 seconds |
| Started | Aug 28 10:54:11 PM UTC 24 |
| Finished | Aug 28 10:54:17 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183574099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3183574099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.2893452790 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 953684781 ps |
| CPU time | 28.56 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893452790 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2893452790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.1652679926 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 259267804 ps |
| CPU time | 10.2 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:27 PM UTC 24 |
| Peak memory | 230640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1652679926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg r_stress_all_with_rand_reset.1652679926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.1217136743 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 235836099 ps |
| CPU time | 4.99 seconds |
| Started | Aug 28 10:54:13 PM UTC 24 |
| Finished | Aug 28 10:54:20 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217136743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1217136743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.2997429510 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 702260303 ps |
| CPU time | 7.53 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:24 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997429510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2997429510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.3422012100 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 29862800 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 10:54:19 PM UTC 24 |
| Finished | Aug 28 10:54:21 PM UTC 24 |
| Peak memory | 213516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422012100 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3422012100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.2478284061 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 427772539 ps |
| CPU time | 10.15 seconds |
| Started | Aug 28 10:54:17 PM UTC 24 |
| Finished | Aug 28 10:54:30 PM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478284061 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2478284061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.2329467577 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 115773082 ps |
| CPU time | 1.96 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:22 PM UTC 24 |
| Peak memory | 219520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329467577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2329467577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.24164179 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 20956357 ps |
| CPU time | 1.85 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:22 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24164179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.24164179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.1853171733 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 199276658 ps |
| CPU time | 4.62 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:25 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853171733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1853171733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.2631034194 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 42467937 ps |
| CPU time | 2.94 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:23 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631034194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2631034194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.212402693 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 93173441 ps |
| CPU time | 3.36 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:23 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212402693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.212402693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_random.2348417733 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 271862093 ps |
| CPU time | 7.56 seconds |
| Started | Aug 28 10:54:16 PM UTC 24 |
| Finished | Aug 28 10:54:25 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348417733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2348417733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.3840073730 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 517928215 ps |
| CPU time | 6.65 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:23 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840073730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3840073730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.1265694241 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 171733644 ps |
| CPU time | 3.41 seconds |
| Started | Aug 28 10:54:16 PM UTC 24 |
| Finished | Aug 28 10:54:21 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265694241 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1265694241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.2427486076 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 23954271 ps |
| CPU time | 2.54 seconds |
| Started | Aug 28 10:54:16 PM UTC 24 |
| Finished | Aug 28 10:54:20 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427486076 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2427486076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.3131077167 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 102220472 ps |
| CPU time | 3.83 seconds |
| Started | Aug 28 10:54:16 PM UTC 24 |
| Finished | Aug 28 10:54:22 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131077167 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3131077167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.3693243676 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 127678766 ps |
| CPU time | 3.81 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:24 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693243676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3693243676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.2535890851 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 247236995 ps |
| CPU time | 2.71 seconds |
| Started | Aug 28 10:54:15 PM UTC 24 |
| Finished | Aug 28 10:54:19 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535890851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2535890851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.1286484435 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2182405592 ps |
| CPU time | 27.1 seconds |
| Started | Aug 28 10:54:19 PM UTC 24 |
| Finished | Aug 28 10:54:48 PM UTC 24 |
| Peak memory | 226216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286484435 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1286484435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all_with_rand_reset.4204975128 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1659257587 ps |
| CPU time | 15.43 seconds |
| Started | Aug 28 10:54:19 PM UTC 24 |
| Finished | Aug 28 10:54:36 PM UTC 24 |
| Peak memory | 232608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4204975128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymg r_stress_all_with_rand_reset.4204975128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.835105696 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 143824021 ps |
| CPU time | 7.44 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:28 PM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835105696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.835105696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.1945762253 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 665366350 ps |
| CPU time | 5.22 seconds |
| Started | Aug 28 10:54:18 PM UTC 24 |
| Finished | Aug 28 10:54:26 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945762253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1945762253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.469775501 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 30773963 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 10:51:27 PM UTC 24 |
| Finished | Aug 28 10:51:30 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469775501 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.469775501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.4090316800 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 154891931 ps |
| CPU time | 4.16 seconds |
| Started | Aug 28 10:51:22 PM UTC 24 |
| Finished | Aug 28 10:51:27 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090316800 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4090316800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.1208510473 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 30269834 ps |
| CPU time | 2.4 seconds |
| Started | Aug 28 10:51:24 PM UTC 24 |
| Finished | Aug 28 10:51:27 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208510473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1208510473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.1179391324 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 224945880 ps |
| CPU time | 3.11 seconds |
| Started | Aug 28 10:51:24 PM UTC 24 |
| Finished | Aug 28 10:51:28 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179391324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1179391324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.3412043454 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 83336304 ps |
| CPU time | 3.38 seconds |
| Started | Aug 28 10:51:24 PM UTC 24 |
| Finished | Aug 28 10:51:28 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412043454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3412043454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_random.96658140 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 232084582 ps |
| CPU time | 7.37 seconds |
| Started | Aug 28 10:51:22 PM UTC 24 |
| Finished | Aug 28 10:51:31 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96658140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.96658140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.1090332937 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2265956113 ps |
| CPU time | 9.57 seconds |
| Started | Aug 28 10:51:27 PM UTC 24 |
| Finished | Aug 28 10:51:38 PM UTC 24 |
| Peak memory | 254712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090332937 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1090332937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.3126215331 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 77116712 ps |
| CPU time | 3.79 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:51:27 PM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126215331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3126215331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.3880646066 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 116375918 ps |
| CPU time | 3.01 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:51:26 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880646066 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3880646066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.2733139972 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3620053259 ps |
| CPU time | 39.29 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:52:03 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733139972 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2733139972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.557062068 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 287360831 ps |
| CPU time | 3.39 seconds |
| Started | Aug 28 10:51:24 PM UTC 24 |
| Finished | Aug 28 10:51:29 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557062068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.557062068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.105818073 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 907382382 ps |
| CPU time | 9.2 seconds |
| Started | Aug 28 10:51:21 PM UTC 24 |
| Finished | Aug 28 10:51:32 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105818073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.105818073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all_with_rand_reset.3877692096 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2083326565 ps |
| CPU time | 30.49 seconds |
| Started | Aug 28 10:51:26 PM UTC 24 |
| Finished | Aug 28 10:51:59 PM UTC 24 |
| Peak memory | 232572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3877692096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr _stress_all_with_rand_reset.3877692096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.609581745 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 48772193 ps |
| CPU time | 3.25 seconds |
| Started | Aug 28 10:51:24 PM UTC 24 |
| Finished | Aug 28 10:51:28 PM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609581745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.609581745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.3716614288 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 50687232 ps |
| CPU time | 3.25 seconds |
| Started | Aug 28 10:51:26 PM UTC 24 |
| Finished | Aug 28 10:51:32 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716614288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3716614288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.1274131272 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 143864876 ps |
| CPU time | 1.25 seconds |
| Started | Aug 28 10:54:23 PM UTC 24 |
| Finished | Aug 28 10:54:27 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274131272 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1274131272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.112059732 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 328985917 ps |
| CPU time | 6.22 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:32 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112059732 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.112059732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.15038666 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 549656983 ps |
| CPU time | 13.84 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15038666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.15038666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.1947715761 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 81841765 ps |
| CPU time | 3.97 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 231156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947715761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1947715761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.1737120178 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 88619783 ps |
| CPU time | 4.97 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:42 PM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737120178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1737120178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.4242332300 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 85146667 ps |
| CPU time | 3.9 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:37 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242332300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.4242332300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_random.3275239502 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 977552357 ps |
| CPU time | 9.96 seconds |
| Started | Aug 28 10:54:21 PM UTC 24 |
| Finished | Aug 28 10:54:32 PM UTC 24 |
| Peak memory | 220340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275239502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3275239502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.2491778029 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 402126378 ps |
| CPU time | 5.5 seconds |
| Started | Aug 28 10:54:19 PM UTC 24 |
| Finished | Aug 28 10:54:26 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491778029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2491778029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.4269160163 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 190005551 ps |
| CPU time | 7.31 seconds |
| Started | Aug 28 10:54:20 PM UTC 24 |
| Finished | Aug 28 10:54:29 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269160163 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4269160163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.1143445200 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 183432252 ps |
| CPU time | 4.87 seconds |
| Started | Aug 28 10:54:20 PM UTC 24 |
| Finished | Aug 28 10:54:27 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143445200 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1143445200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.2164737540 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 41365408 ps |
| CPU time | 2.68 seconds |
| Started | Aug 28 10:54:21 PM UTC 24 |
| Finished | Aug 28 10:54:24 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164737540 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2164737540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.2934485065 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 132790096 ps |
| CPU time | 2.59 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:32 PM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934485065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2934485065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.2060634686 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 451484437 ps |
| CPU time | 9.01 seconds |
| Started | Aug 28 10:54:19 PM UTC 24 |
| Finished | Aug 28 10:54:29 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060634686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2060634686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.3036311178 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 524353559 ps |
| CPU time | 18.29 seconds |
| Started | Aug 28 10:54:23 PM UTC 24 |
| Finished | Aug 28 10:54:44 PM UTC 24 |
| Peak memory | 232416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3036311178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.3036311178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.1724961791 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 812389137 ps |
| CPU time | 6.06 seconds |
| Started | Aug 28 10:54:22 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724961791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1724961791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.1243991390 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 87722587 ps |
| CPU time | 2.73 seconds |
| Started | Aug 28 10:54:23 PM UTC 24 |
| Finished | Aug 28 10:54:28 PM UTC 24 |
| Peak memory | 220200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243991390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1243991390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.601437790 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 16213715 ps |
| CPU time | 1 seconds |
| Started | Aug 28 10:54:28 PM UTC 24 |
| Finished | Aug 28 10:54:33 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601437790 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.601437790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.2847124846 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 134066037 ps |
| CPU time | 2.37 seconds |
| Started | Aug 28 10:54:26 PM UTC 24 |
| Finished | Aug 28 10:54:33 PM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847124846 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2847124846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.2347319896 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1635363136 ps |
| CPU time | 12.73 seconds |
| Started | Aug 28 10:54:26 PM UTC 24 |
| Finished | Aug 28 10:54:43 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347319896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2347319896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.3052324066 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 95687412 ps |
| CPU time | 4.51 seconds |
| Started | Aug 28 10:54:26 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 218052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052324066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3052324066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.3079097620 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 324425837 ps |
| CPU time | 4.47 seconds |
| Started | Aug 28 10:54:26 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079097620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3079097620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.2577971082 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 41518401 ps |
| CPU time | 2.88 seconds |
| Started | Aug 28 10:54:26 PM UTC 24 |
| Finished | Aug 28 10:54:33 PM UTC 24 |
| Peak memory | 217864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577971082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2577971082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_random.2075972459 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 164424306 ps |
| CPU time | 4.54 seconds |
| Started | Aug 28 10:54:25 PM UTC 24 |
| Finished | Aug 28 10:54:30 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075972459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2075972459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.801345938 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 508219056 ps |
| CPU time | 3.09 seconds |
| Started | Aug 28 10:54:24 PM UTC 24 |
| Finished | Aug 28 10:54:29 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801345938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.801345938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.2107259097 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 574024703 ps |
| CPU time | 8.7 seconds |
| Started | Aug 28 10:54:25 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 217860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107259097 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2107259097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.2784456046 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 640404179 ps |
| CPU time | 16.3 seconds |
| Started | Aug 28 10:54:25 PM UTC 24 |
| Finished | Aug 28 10:54:42 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784456046 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2784456046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.1775481419 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1137487585 ps |
| CPU time | 22.05 seconds |
| Started | Aug 28 10:54:25 PM UTC 24 |
| Finished | Aug 28 10:54:48 PM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775481419 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1775481419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.1373536666 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 181887612 ps |
| CPU time | 3.77 seconds |
| Started | Aug 28 10:54:27 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373536666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1373536666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.1980527420 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 169112219 ps |
| CPU time | 2.09 seconds |
| Started | Aug 28 10:54:24 PM UTC 24 |
| Finished | Aug 28 10:54:28 PM UTC 24 |
| Peak memory | 215752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980527420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1980527420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.1097158233 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4903076963 ps |
| CPU time | 31.45 seconds |
| Started | Aug 28 10:54:28 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097158233 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1097158233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.1451468455 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 6545815959 ps |
| CPU time | 41.14 seconds |
| Started | Aug 28 10:54:26 PM UTC 24 |
| Finished | Aug 28 10:55:12 PM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451468455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1451468455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.2121369959 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 144957662 ps |
| CPU time | 2.43 seconds |
| Started | Aug 28 10:54:27 PM UTC 24 |
| Finished | Aug 28 10:54:34 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121369959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2121369959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.2777334899 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 63479416 ps |
| CPU time | 1.29 seconds |
| Started | Aug 28 10:54:35 PM UTC 24 |
| Finished | Aug 28 10:54:38 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777334899 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2777334899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.3261617618 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 349028555 ps |
| CPU time | 3.2 seconds |
| Started | Aug 28 10:54:31 PM UTC 24 |
| Finished | Aug 28 10:54:36 PM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261617618 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3261617618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.2723706493 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 472522219 ps |
| CPU time | 6.92 seconds |
| Started | Aug 28 10:54:34 PM UTC 24 |
| Finished | Aug 28 10:54:43 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723706493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2723706493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.699351814 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 24123167 ps |
| CPU time | 2.43 seconds |
| Started | Aug 28 10:54:31 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699351814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.699351814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.1656243491 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 220049264 ps |
| CPU time | 3.28 seconds |
| Started | Aug 28 10:54:33 PM UTC 24 |
| Finished | Aug 28 10:54:38 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656243491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1656243491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.819865577 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 162432507 ps |
| CPU time | 4.48 seconds |
| Started | Aug 28 10:54:33 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819865577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.819865577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.2459038003 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 623013118 ps |
| CPU time | 5.19 seconds |
| Started | Aug 28 10:54:31 PM UTC 24 |
| Finished | Aug 28 10:54:38 PM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459038003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2459038003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_random.1570825526 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 88158560 ps |
| CPU time | 3.4 seconds |
| Started | Aug 28 10:54:30 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570825526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1570825526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.1222393215 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 455820557 ps |
| CPU time | 6.88 seconds |
| Started | Aug 28 10:54:29 PM UTC 24 |
| Finished | Aug 28 10:54:38 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222393215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1222393215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.3477533969 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 60347923 ps |
| CPU time | 3.82 seconds |
| Started | Aug 28 10:54:30 PM UTC 24 |
| Finished | Aug 28 10:54:35 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477533969 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3477533969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.2177201970 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 326408083 ps |
| CPU time | 5.22 seconds |
| Started | Aug 28 10:54:29 PM UTC 24 |
| Finished | Aug 28 10:54:36 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177201970 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2177201970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.1867510666 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 43189082 ps |
| CPU time | 2.33 seconds |
| Started | Aug 28 10:54:30 PM UTC 24 |
| Finished | Aug 28 10:54:34 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867510666 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1867510666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.3170778450 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 432422182 ps |
| CPU time | 4.98 seconds |
| Started | Aug 28 10:54:34 PM UTC 24 |
| Finished | Aug 28 10:54:41 PM UTC 24 |
| Peak memory | 224248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170778450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3170778450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.2820933781 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 80470703 ps |
| CPU time | 3.24 seconds |
| Started | Aug 28 10:54:29 PM UTC 24 |
| Finished | Aug 28 10:54:34 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820933781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2820933781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.2300814887 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 333514499 ps |
| CPU time | 12.36 seconds |
| Started | Aug 28 10:54:34 PM UTC 24 |
| Finished | Aug 28 10:54:48 PM UTC 24 |
| Peak memory | 228200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300814887 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2300814887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all_with_rand_reset.3906652000 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 948308727 ps |
| CPU time | 9.7 seconds |
| Started | Aug 28 10:54:35 PM UTC 24 |
| Finished | Aug 28 10:54:46 PM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3906652000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymg r_stress_all_with_rand_reset.3906652000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.701570782 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 394035480 ps |
| CPU time | 5.26 seconds |
| Started | Aug 28 10:54:32 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 226068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701570782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.701570782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.935035933 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 95179769 ps |
| CPU time | 1.7 seconds |
| Started | Aug 28 10:54:34 PM UTC 24 |
| Finished | Aug 28 10:54:38 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935035933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.935035933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.2836720295 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 44311942 ps |
| CPU time | 1.01 seconds |
| Started | Aug 28 10:54:39 PM UTC 24 |
| Finished | Aug 28 10:54:41 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836720295 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2836720295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.40701533 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 142423596 ps |
| CPU time | 3.73 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 226072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40701533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.40701533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.2460367397 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2336546505 ps |
| CPU time | 10.37 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:56 PM UTC 24 |
| Peak memory | 226232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460367397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2460367397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.2043453595 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 73854607 ps |
| CPU time | 2.88 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:44 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043453595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2043453595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.2830924850 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 616070585 ps |
| CPU time | 8.11 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:53 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830924850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2830924850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.4156978912 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 493831916 ps |
| CPU time | 3.9 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156978912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.4156978912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.490956647 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 144700225 ps |
| CPU time | 3.33 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 218324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490956647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.490956647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_random.3809369149 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 59315006 ps |
| CPU time | 4.11 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809369149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3809369149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.3664194992 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 140407404 ps |
| CPU time | 3.39 seconds |
| Started | Aug 28 10:54:35 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664194992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3664194992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.927559547 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 158924854 ps |
| CPU time | 4.66 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:42 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927559547 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.927559547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.24228228 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 336754789 ps |
| CPU time | 4.07 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:42 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24228228 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.24228228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.1791822405 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 167997240 ps |
| CPU time | 4.07 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791822405 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1791822405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.1901718516 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2032595154 ps |
| CPU time | 3.68 seconds |
| Started | Aug 28 10:54:38 PM UTC 24 |
| Finished | Aug 28 10:54:44 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901718516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1901718516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.877258567 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 71270045 ps |
| CPU time | 3.2 seconds |
| Started | Aug 28 10:54:35 PM UTC 24 |
| Finished | Aug 28 10:54:40 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877258567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.877258567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.1680966519 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 12200940993 ps |
| CPU time | 69.64 seconds |
| Started | Aug 28 10:54:38 PM UTC 24 |
| Finished | Aug 28 10:55:51 PM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680966519 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1680966519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.3277741700 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 198894289 ps |
| CPU time | 4.38 seconds |
| Started | Aug 28 10:54:37 PM UTC 24 |
| Finished | Aug 28 10:54:46 PM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277741700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3277741700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.711424915 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 84246360 ps |
| CPU time | 2.64 seconds |
| Started | Aug 28 10:54:38 PM UTC 24 |
| Finished | Aug 28 10:54:43 PM UTC 24 |
| Peak memory | 220228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711424915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.711424915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.2933145667 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 21424474 ps |
| CPU time | 1.31 seconds |
| Started | Aug 28 10:54:43 PM UTC 24 |
| Finished | Aug 28 10:55:02 PM UTC 24 |
| Peak memory | 213720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933145667 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2933145667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.2518488824 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 382953618 ps |
| CPU time | 3.19 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:48 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518488824 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2518488824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.309489271 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 79877749 ps |
| CPU time | 3.1 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:49 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309489271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.309489271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.3307424877 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 61469626 ps |
| CPU time | 2.17 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:47 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307424877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3307424877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.810375908 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 63022816 ps |
| CPU time | 2.24 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:48 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810375908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.810375908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.1039528891 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 73110587 ps |
| CPU time | 2.33 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:48 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039528891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1039528891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.1347663833 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 118149549 ps |
| CPU time | 5.25 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:51 PM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347663833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1347663833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_random.4227210028 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 281429734 ps |
| CPU time | 3.57 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:49 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227210028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4227210028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.442632308 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 153370832 ps |
| CPU time | 4.17 seconds |
| Started | Aug 28 10:54:40 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442632308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.442632308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.485771351 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 500690721 ps |
| CPU time | 4.69 seconds |
| Started | Aug 28 10:54:40 PM UTC 24 |
| Finished | Aug 28 10:54:45 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485771351 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.485771351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.558997098 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 25780338 ps |
| CPU time | 2.43 seconds |
| Started | Aug 28 10:54:40 PM UTC 24 |
| Finished | Aug 28 10:54:43 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558997098 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.558997098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.159372993 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 94739899 ps |
| CPU time | 3.25 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:48 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159372993 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.159372993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.1959886991 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 167108316 ps |
| CPU time | 2.56 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:58 PM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959886991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1959886991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.3965376549 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 882891441 ps |
| CPU time | 15.84 seconds |
| Started | Aug 28 10:54:39 PM UTC 24 |
| Finished | Aug 28 10:54:57 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965376549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3965376549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.896929495 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 380808062 ps |
| CPU time | 14.8 seconds |
| Started | Aug 28 10:54:43 PM UTC 24 |
| Finished | Aug 28 10:55:16 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896929495 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.896929495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.162834281 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 286607398 ps |
| CPU time | 5.53 seconds |
| Started | Aug 28 10:54:41 PM UTC 24 |
| Finished | Aug 28 10:54:51 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162834281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.162834281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.2006728217 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 189261291 ps |
| CPU time | 2.07 seconds |
| Started | Aug 28 10:54:43 PM UTC 24 |
| Finished | Aug 28 10:55:03 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006728217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2006728217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.2309169503 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 59770995 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 10:54:47 PM UTC 24 |
| Finished | Aug 28 10:54:52 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309169503 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2309169503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.1079550903 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 746543452 ps |
| CPU time | 8.79 seconds |
| Started | Aug 28 10:54:44 PM UTC 24 |
| Finished | Aug 28 10:54:54 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079550903 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1079550903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.3976598294 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 64860425 ps |
| CPU time | 1.62 seconds |
| Started | Aug 28 10:54:45 PM UTC 24 |
| Finished | Aug 28 10:55:05 PM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976598294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3976598294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.577006343 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 71039503 ps |
| CPU time | 3.22 seconds |
| Started | Aug 28 10:54:45 PM UTC 24 |
| Finished | Aug 28 10:55:07 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577006343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.577006343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.3138055591 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 121183431 ps |
| CPU time | 2.49 seconds |
| Started | Aug 28 10:54:45 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138055591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3138055591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.1415192792 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 64199388 ps |
| CPU time | 2.7 seconds |
| Started | Aug 28 10:54:45 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415192792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1415192792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_random.2841058338 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 562850866 ps |
| CPU time | 9.09 seconds |
| Started | Aug 28 10:54:44 PM UTC 24 |
| Finished | Aug 28 10:54:54 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841058338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2841058338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.4228319940 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 89484709 ps |
| CPU time | 4.72 seconds |
| Started | Aug 28 10:54:44 PM UTC 24 |
| Finished | Aug 28 10:55:08 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228319940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4228319940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.754455865 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 222238855 ps |
| CPU time | 1.87 seconds |
| Started | Aug 28 10:54:44 PM UTC 24 |
| Finished | Aug 28 10:55:05 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754455865 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.754455865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.2926112647 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 184449756 ps |
| CPU time | 4.25 seconds |
| Started | Aug 28 10:54:44 PM UTC 24 |
| Finished | Aug 28 10:55:07 PM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926112647 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2926112647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.429529773 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 374242838 ps |
| CPU time | 3.75 seconds |
| Started | Aug 28 10:54:44 PM UTC 24 |
| Finished | Aug 28 10:55:07 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429529773 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.429529773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.2247420810 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 240630252 ps |
| CPU time | 2 seconds |
| Started | Aug 28 10:54:46 PM UTC 24 |
| Finished | Aug 28 10:54:53 PM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247420810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2247420810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.3708353913 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 577712229 ps |
| CPU time | 2.3 seconds |
| Started | Aug 28 10:54:43 PM UTC 24 |
| Finished | Aug 28 10:55:03 PM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708353913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3708353913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.1230318867 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 15414964440 ps |
| CPU time | 56.04 seconds |
| Started | Aug 28 10:54:46 PM UTC 24 |
| Finished | Aug 28 10:55:47 PM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230318867 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1230318867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.2549069901 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 559341687 ps |
| CPU time | 8.52 seconds |
| Started | Aug 28 10:54:45 PM UTC 24 |
| Finished | Aug 28 10:55:12 PM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549069901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2549069901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.2627528121 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 60854887 ps |
| CPU time | 2.21 seconds |
| Started | Aug 28 10:54:46 PM UTC 24 |
| Finished | Aug 28 10:54:53 PM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627528121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2627528121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.1864860979 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 59916389 ps |
| CPU time | 0.8 seconds |
| Started | Aug 28 10:54:53 PM UTC 24 |
| Finished | Aug 28 10:54:56 PM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864860979 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1864860979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.531362336 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 158299122 ps |
| CPU time | 6.56 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:55:08 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531362336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.531362336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.4193875166 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 173212295 ps |
| CPU time | 3.66 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:54:54 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193875166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4193875166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.449389505 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 53033576 ps |
| CPU time | 2.77 seconds |
| Started | Aug 28 10:54:50 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449389505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.449389505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.288440963 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 117785554 ps |
| CPU time | 4.83 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288440963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.288440963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_random.3790693953 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 59297378 ps |
| CPU time | 3.55 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:55:05 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790693953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3790693953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.2144702425 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 315030467 ps |
| CPU time | 5.47 seconds |
| Started | Aug 28 10:54:47 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144702425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2144702425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.3383733905 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 133146111 ps |
| CPU time | 2.8 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 217544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383733905 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3383733905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.2862165638 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 13140790929 ps |
| CPU time | 40.59 seconds |
| Started | Aug 28 10:54:48 PM UTC 24 |
| Finished | Aug 28 10:55:44 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862165638 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2862165638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.4130352190 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 16515188609 ps |
| CPU time | 31.62 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:55:33 PM UTC 24 |
| Peak memory | 216228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130352190 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4130352190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.972097303 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 599346463 ps |
| CPU time | 4.04 seconds |
| Started | Aug 28 10:54:51 PM UTC 24 |
| Finished | Aug 28 10:54:59 PM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972097303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.972097303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.3924829402 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1245849457 ps |
| CPU time | 4.9 seconds |
| Started | Aug 28 10:54:47 PM UTC 24 |
| Finished | Aug 28 10:54:56 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924829402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3924829402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.850458713 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2434170771 ps |
| CPU time | 16.23 seconds |
| Started | Aug 28 10:54:52 PM UTC 24 |
| Finished | Aug 28 10:55:17 PM UTC 24 |
| Peak memory | 232548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850458713 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.850458713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all_with_rand_reset.3435840077 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2475580664 ps |
| CPU time | 11.01 seconds |
| Started | Aug 28 10:54:52 PM UTC 24 |
| Finished | Aug 28 10:55:11 PM UTC 24 |
| Peak memory | 228352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3435840077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymg r_stress_all_with_rand_reset.3435840077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.3203117864 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 559205521 ps |
| CPU time | 7.01 seconds |
| Started | Aug 28 10:54:49 PM UTC 24 |
| Finished | Aug 28 10:55:08 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203117864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3203117864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.730643862 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 47489160 ps |
| CPU time | 1.55 seconds |
| Started | Aug 28 10:54:51 PM UTC 24 |
| Finished | Aug 28 10:54:57 PM UTC 24 |
| Peak memory | 219616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730643862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.730643862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.3323468453 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 93432161 ps |
| CPU time | 1.02 seconds |
| Started | Aug 28 10:55:00 PM UTC 24 |
| Finished | Aug 28 10:55:02 PM UTC 24 |
| Peak memory | 213512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323468453 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3323468453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.2955783833 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 141140455 ps |
| CPU time | 8.81 seconds |
| Started | Aug 28 10:54:56 PM UTC 24 |
| Finished | Aug 28 10:55:13 PM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955783833 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2955783833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.3267884611 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 155981313 ps |
| CPU time | 3.68 seconds |
| Started | Aug 28 10:54:58 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 230256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267884611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3267884611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.3851555999 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 247201543 ps |
| CPU time | 2.94 seconds |
| Started | Aug 28 10:54:57 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 218352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851555999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3851555999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.3802051148 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 69896316 ps |
| CPU time | 2.26 seconds |
| Started | Aug 28 10:54:58 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 226188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802051148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3802051148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.116982163 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 336369921 ps |
| CPU time | 3.74 seconds |
| Started | Aug 28 10:54:58 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116982163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.116982163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.1677526118 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 205003478 ps |
| CPU time | 3.14 seconds |
| Started | Aug 28 10:54:57 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677526118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1677526118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_random.1714513715 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 473978108 ps |
| CPU time | 5.16 seconds |
| Started | Aug 28 10:54:55 PM UTC 24 |
| Finished | Aug 28 10:55:01 PM UTC 24 |
| Peak memory | 215948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714513715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1714513715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.3130949202 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 64235718 ps |
| CPU time | 2.73 seconds |
| Started | Aug 28 10:54:53 PM UTC 24 |
| Finished | Aug 28 10:54:58 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130949202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3130949202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.3384162696 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 634853321 ps |
| CPU time | 6.16 seconds |
| Started | Aug 28 10:54:55 PM UTC 24 |
| Finished | Aug 28 10:55:02 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384162696 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3384162696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.3659576831 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 188775399 ps |
| CPU time | 3.23 seconds |
| Started | Aug 28 10:54:55 PM UTC 24 |
| Finished | Aug 28 10:54:59 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659576831 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3659576831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.2075000725 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 143038743 ps |
| CPU time | 2.43 seconds |
| Started | Aug 28 10:54:55 PM UTC 24 |
| Finished | Aug 28 10:54:58 PM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075000725 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2075000725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.3059583780 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 458972564 ps |
| CPU time | 2.45 seconds |
| Started | Aug 28 10:54:59 PM UTC 24 |
| Finished | Aug 28 10:55:02 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059583780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3059583780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.2804201133 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 153459631 ps |
| CPU time | 3.26 seconds |
| Started | Aug 28 10:54:53 PM UTC 24 |
| Finished | Aug 28 10:54:59 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804201133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2804201133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.1590237262 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1340307369 ps |
| CPU time | 39.42 seconds |
| Started | Aug 28 10:54:59 PM UTC 24 |
| Finished | Aug 28 10:55:40 PM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590237262 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1590237262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.1548738377 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 510712274 ps |
| CPU time | 6.39 seconds |
| Started | Aug 28 10:55:00 PM UTC 24 |
| Finished | Aug 28 10:55:08 PM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1548738377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.1548738377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.190692402 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 573723280 ps |
| CPU time | 4.89 seconds |
| Started | Aug 28 10:54:57 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190692402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.190692402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.440804774 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 580594794 ps |
| CPU time | 3.16 seconds |
| Started | Aug 28 10:54:59 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440804774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.440804774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2501417890 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 29963884 ps |
| CPU time | 1.17 seconds |
| Started | Aug 28 10:55:06 PM UTC 24 |
| Finished | Aug 28 10:55:08 PM UTC 24 |
| Peak memory | 213660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501417890 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2501417890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.2633716726 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 223906509 ps |
| CPU time | 3.76 seconds |
| Started | Aug 28 10:55:04 PM UTC 24 |
| Finished | Aug 28 10:55:08 PM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633716726 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2633716726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.635891619 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 371760022 ps |
| CPU time | 3.27 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:09 PM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635891619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.635891619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.1961591536 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 39124392 ps |
| CPU time | 2.51 seconds |
| Started | Aug 28 10:55:04 PM UTC 24 |
| Finished | Aug 28 10:55:07 PM UTC 24 |
| Peak memory | 228160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961591536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1961591536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.2073987242 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 188107860 ps |
| CPU time | 3.67 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:10 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073987242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2073987242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.2253028551 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 30296155 ps |
| CPU time | 1.83 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:08 PM UTC 24 |
| Peak memory | 223552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253028551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2253028551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_random.3051815037 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1315211320 ps |
| CPU time | 18.61 seconds |
| Started | Aug 28 10:55:04 PM UTC 24 |
| Finished | Aug 28 10:55:24 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051815037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3051815037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.3191418002 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 393312159 ps |
| CPU time | 3.69 seconds |
| Started | Aug 28 10:55:01 PM UTC 24 |
| Finished | Aug 28 10:55:06 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191418002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3191418002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.1444493353 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 180699120 ps |
| CPU time | 4.37 seconds |
| Started | Aug 28 10:55:03 PM UTC 24 |
| Finished | Aug 28 10:55:09 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444493353 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1444493353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.3165781841 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 213126223 ps |
| CPU time | 3.81 seconds |
| Started | Aug 28 10:55:02 PM UTC 24 |
| Finished | Aug 28 10:55:07 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165781841 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3165781841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.3875475137 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1293996546 ps |
| CPU time | 7.28 seconds |
| Started | Aug 28 10:55:03 PM UTC 24 |
| Finished | Aug 28 10:55:12 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875475137 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3875475137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.2968876362 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 30331354 ps |
| CPU time | 2.35 seconds |
| Started | Aug 28 10:55:00 PM UTC 24 |
| Finished | Aug 28 10:55:04 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968876362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2968876362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1557613000 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 3044952493 ps |
| CPU time | 34.08 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:41 PM UTC 24 |
| Peak memory | 232384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557613000 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1557613000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.2699220120 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 587294775 ps |
| CPU time | 10.25 seconds |
| Started | Aug 28 10:55:06 PM UTC 24 |
| Finished | Aug 28 10:55:18 PM UTC 24 |
| Peak memory | 232636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2699220120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg r_stress_all_with_rand_reset.2699220120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.954824942 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 1142867144 ps |
| CPU time | 25.67 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:32 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954824942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.954824942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.17721426 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1774260552 ps |
| CPU time | 14.01 seconds |
| Started | Aug 28 10:55:05 PM UTC 24 |
| Finished | Aug 28 10:55:20 PM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17721426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.17721426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.3413808521 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 28584745 ps |
| CPU time | 1.24 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:12 PM UTC 24 |
| Peak memory | 213568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413808521 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3413808521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.973452162 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 178985407 ps |
| CPU time | 4.12 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973452162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.973452162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.4067191977 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 1811643730 ps |
| CPU time | 5.54 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:15 PM UTC 24 |
| Peak memory | 224400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067191977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4067191977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.4037710151 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 409054345 ps |
| CPU time | 4.56 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037710151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4037710151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.672483085 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 54500234 ps |
| CPU time | 3.86 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 232540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672483085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.672483085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.1559897872 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 274580350 ps |
| CPU time | 3.81 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:13 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559897872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1559897872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_random.4080545036 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 98482292 ps |
| CPU time | 5.41 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:15 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080545036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4080545036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.3558092173 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 714091402 ps |
| CPU time | 6.51 seconds |
| Started | Aug 28 10:55:06 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558092173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3558092173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.841841226 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 43367868 ps |
| CPU time | 3.13 seconds |
| Started | Aug 28 10:55:07 PM UTC 24 |
| Finished | Aug 28 10:55:11 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841841226 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.841841226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.2407004031 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 213420477 ps |
| CPU time | 3.7 seconds |
| Started | Aug 28 10:55:06 PM UTC 24 |
| Finished | Aug 28 10:55:11 PM UTC 24 |
| Peak memory | 217924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407004031 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2407004031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.2361226138 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 75858600 ps |
| CPU time | 3.53 seconds |
| Started | Aug 28 10:55:07 PM UTC 24 |
| Finished | Aug 28 10:55:11 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361226138 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2361226138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.4136894492 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 144715853 ps |
| CPU time | 2.31 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:13 PM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136894492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4136894492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.423154933 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 33209518 ps |
| CPU time | 2.28 seconds |
| Started | Aug 28 10:55:06 PM UTC 24 |
| Finished | Aug 28 10:55:10 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423154933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.423154933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.1571512972 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 6321305061 ps |
| CPU time | 133.89 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:57:26 PM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571512972 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1571512972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.3819779529 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1108130600 ps |
| CPU time | 19.87 seconds |
| Started | Aug 28 10:55:10 PM UTC 24 |
| Finished | Aug 28 10:55:31 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3819779529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymg r_stress_all_with_rand_reset.3819779529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.1738885747 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 369274183 ps |
| CPU time | 4.02 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738885747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1738885747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.2309982909 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 116071937 ps |
| CPU time | 3.09 seconds |
| Started | Aug 28 10:55:08 PM UTC 24 |
| Finished | Aug 28 10:55:14 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309982909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2309982909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.1755022761 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 91311807 ps |
| CPU time | 1.39 seconds |
| Started | Aug 28 10:51:31 PM UTC 24 |
| Finished | Aug 28 10:51:34 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755022761 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1755022761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.2709715929 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 565769562 ps |
| CPU time | 7.6 seconds |
| Started | Aug 28 10:51:31 PM UTC 24 |
| Finished | Aug 28 10:51:40 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709715929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2709715929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.2320015557 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 57561638 ps |
| CPU time | 3.69 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:51:34 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320015557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2320015557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.800077894 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 270583648 ps |
| CPU time | 7.31 seconds |
| Started | Aug 28 10:51:30 PM UTC 24 |
| Finished | Aug 28 10:51:39 PM UTC 24 |
| Peak memory | 226512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800077894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.800077894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.595711871 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 173897677 ps |
| CPU time | 5.81 seconds |
| Started | Aug 28 10:51:31 PM UTC 24 |
| Finished | Aug 28 10:51:38 PM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595711871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.595711871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.2445520102 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 107336369 ps |
| CPU time | 3.3 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:51:34 PM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445520102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2445520102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_random.3530722884 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 534489439 ps |
| CPU time | 3.86 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:51:34 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530722884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3530722884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.1461340555 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 56006744 ps |
| CPU time | 3.17 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:51:33 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461340555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1461340555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.2262768716 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 658081672 ps |
| CPU time | 5.03 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:51:35 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262768716 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2262768716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.1506616140 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1867515379 ps |
| CPU time | 20.9 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:51:51 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506616140 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1506616140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.2534939680 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1832379178 ps |
| CPU time | 63.02 seconds |
| Started | Aug 28 10:51:29 PM UTC 24 |
| Finished | Aug 28 10:52:34 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534939680 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2534939680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.438382836 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2165729296 ps |
| CPU time | 19.03 seconds |
| Started | Aug 28 10:51:31 PM UTC 24 |
| Finished | Aug 28 10:51:51 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438382836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.438382836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.3922747587 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 94680636 ps |
| CPU time | 3.78 seconds |
| Started | Aug 28 10:51:28 PM UTC 24 |
| Finished | Aug 28 10:51:33 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922747587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3922747587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.3587910000 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 811792799 ps |
| CPU time | 13.42 seconds |
| Started | Aug 28 10:51:31 PM UTC 24 |
| Finished | Aug 28 10:51:46 PM UTC 24 |
| Peak memory | 230376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587910000 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3587910000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.443776081 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 238223233 ps |
| CPU time | 7.33 seconds |
| Started | Aug 28 10:51:30 PM UTC 24 |
| Finished | Aug 28 10:51:39 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443776081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.443776081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.599997346 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1104110436 ps |
| CPU time | 13.72 seconds |
| Started | Aug 28 10:51:31 PM UTC 24 |
| Finished | Aug 28 10:51:46 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599997346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.599997346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.2698961933 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 60285364 ps |
| CPU time | 1.28 seconds |
| Started | Aug 28 10:51:40 PM UTC 24 |
| Finished | Aug 28 10:51:43 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698961933 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2698961933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.3269253350 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 148065020 ps |
| CPU time | 2.24 seconds |
| Started | Aug 28 10:51:38 PM UTC 24 |
| Finished | Aug 28 10:51:41 PM UTC 24 |
| Peak memory | 226056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269253350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3269253350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.2201642251 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 72367702 ps |
| CPU time | 2.99 seconds |
| Started | Aug 28 10:51:36 PM UTC 24 |
| Finished | Aug 28 10:51:40 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201642251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2201642251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.2008085054 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 136644962 ps |
| CPU time | 5.1 seconds |
| Started | Aug 28 10:51:38 PM UTC 24 |
| Finished | Aug 28 10:51:44 PM UTC 24 |
| Peak memory | 224296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008085054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2008085054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.3374598914 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1539608235 ps |
| CPU time | 6.54 seconds |
| Started | Aug 28 10:51:36 PM UTC 24 |
| Finished | Aug 28 10:51:43 PM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374598914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3374598914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_random.1210402200 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 692089590 ps |
| CPU time | 12.09 seconds |
| Started | Aug 28 10:51:35 PM UTC 24 |
| Finished | Aug 28 10:51:49 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210402200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1210402200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.608913323 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 72340615 ps |
| CPU time | 2.72 seconds |
| Started | Aug 28 10:51:33 PM UTC 24 |
| Finished | Aug 28 10:51:37 PM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608913323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.608913323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.916473738 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 601383529 ps |
| CPU time | 8.86 seconds |
| Started | Aug 28 10:51:33 PM UTC 24 |
| Finished | Aug 28 10:51:43 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916473738 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.916473738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.3640192921 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 701121554 ps |
| CPU time | 7.98 seconds |
| Started | Aug 28 10:51:33 PM UTC 24 |
| Finished | Aug 28 10:51:42 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640192921 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3640192921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.3659848995 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 87586368 ps |
| CPU time | 5.45 seconds |
| Started | Aug 28 10:51:33 PM UTC 24 |
| Finished | Aug 28 10:51:40 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659848995 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3659848995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.3681995037 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 97068128 ps |
| CPU time | 1.99 seconds |
| Started | Aug 28 10:51:38 PM UTC 24 |
| Finished | Aug 28 10:51:41 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681995037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3681995037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.3045249331 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 129943332 ps |
| CPU time | 6.84 seconds |
| Started | Aug 28 10:51:33 PM UTC 24 |
| Finished | Aug 28 10:51:41 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045249331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3045249331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.2181353776 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 594168914 ps |
| CPU time | 8.29 seconds |
| Started | Aug 28 10:51:36 PM UTC 24 |
| Finished | Aug 28 10:51:45 PM UTC 24 |
| Peak memory | 218052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181353776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2181353776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3046439569 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 117835610 ps |
| CPU time | 4.3 seconds |
| Started | Aug 28 10:51:40 PM UTC 24 |
| Finished | Aug 28 10:51:46 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046439569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3046439569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.1954646568 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 23385798 ps |
| CPU time | 1.23 seconds |
| Started | Aug 28 10:51:46 PM UTC 24 |
| Finished | Aug 28 10:51:48 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954646568 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1954646568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.3762354393 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 970748611 ps |
| CPU time | 49.01 seconds |
| Started | Aug 28 10:51:43 PM UTC 24 |
| Finished | Aug 28 10:52:34 PM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762354393 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3762354393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.1848830036 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 211171752 ps |
| CPU time | 4.21 seconds |
| Started | Aug 28 10:51:43 PM UTC 24 |
| Finished | Aug 28 10:51:48 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848830036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1848830036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.127845853 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1068476477 ps |
| CPU time | 8.18 seconds |
| Started | Aug 28 10:51:44 PM UTC 24 |
| Finished | Aug 28 10:51:54 PM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127845853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.127845853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.3339448674 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 71365065 ps |
| CPU time | 3.62 seconds |
| Started | Aug 28 10:51:44 PM UTC 24 |
| Finished | Aug 28 10:51:49 PM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339448674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3339448674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.2104663175 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 221526666 ps |
| CPU time | 8.37 seconds |
| Started | Aug 28 10:51:43 PM UTC 24 |
| Finished | Aug 28 10:51:52 PM UTC 24 |
| Peak memory | 230488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104663175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2104663175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_random.3860417884 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 483537859 ps |
| CPU time | 11.84 seconds |
| Started | Aug 28 10:51:43 PM UTC 24 |
| Finished | Aug 28 10:51:56 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860417884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3860417884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.3604617566 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 260747500 ps |
| CPU time | 4.49 seconds |
| Started | Aug 28 10:51:41 PM UTC 24 |
| Finished | Aug 28 10:51:46 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604617566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3604617566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.1087627936 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 732967740 ps |
| CPU time | 6.24 seconds |
| Started | Aug 28 10:51:41 PM UTC 24 |
| Finished | Aug 28 10:51:48 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087627936 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1087627936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.2392795763 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 103987289 ps |
| CPU time | 3.17 seconds |
| Started | Aug 28 10:51:41 PM UTC 24 |
| Finished | Aug 28 10:51:45 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392795763 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2392795763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.2962856707 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 222618067 ps |
| CPU time | 6.09 seconds |
| Started | Aug 28 10:51:41 PM UTC 24 |
| Finished | Aug 28 10:51:48 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962856707 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2962856707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.2247454864 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1408660061 ps |
| CPU time | 20.86 seconds |
| Started | Aug 28 10:51:44 PM UTC 24 |
| Finished | Aug 28 10:52:07 PM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247454864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2247454864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.2468458993 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 112690142 ps |
| CPU time | 4.82 seconds |
| Started | Aug 28 10:51:40 PM UTC 24 |
| Finished | Aug 28 10:51:47 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468458993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2468458993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2804835072 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 162681543 ps |
| CPU time | 5.97 seconds |
| Started | Aug 28 10:51:43 PM UTC 24 |
| Finished | Aug 28 10:51:50 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804835072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2804835072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.1999906664 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 176295001 ps |
| CPU time | 3.28 seconds |
| Started | Aug 28 10:51:44 PM UTC 24 |
| Finished | Aug 28 10:51:49 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999906664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1999906664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.1026389330 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 22013264 ps |
| CPU time | 1.04 seconds |
| Started | Aug 28 10:51:53 PM UTC 24 |
| Finished | Aug 28 10:51:55 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026389330 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1026389330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.841906061 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 144644750 ps |
| CPU time | 7.99 seconds |
| Started | Aug 28 10:51:50 PM UTC 24 |
| Finished | Aug 28 10:52:00 PM UTC 24 |
| Peak memory | 232672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841906061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.841906061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.609639430 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 28270900 ps |
| CPU time | 2.36 seconds |
| Started | Aug 28 10:51:49 PM UTC 24 |
| Finished | Aug 28 10:51:53 PM UTC 24 |
| Peak memory | 226164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609639430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.609639430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.3210008338 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 60082649 ps |
| CPU time | 3.4 seconds |
| Started | Aug 28 10:51:50 PM UTC 24 |
| Finished | Aug 28 10:51:55 PM UTC 24 |
| Peak memory | 223788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210008338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3210008338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.2237660380 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 64514121 ps |
| CPU time | 4.5 seconds |
| Started | Aug 28 10:51:50 PM UTC 24 |
| Finished | Aug 28 10:51:56 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237660380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2237660380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.799071674 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 272081301 ps |
| CPU time | 4.85 seconds |
| Started | Aug 28 10:51:49 PM UTC 24 |
| Finished | Aug 28 10:51:55 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799071674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.799071674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_random.3747155846 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 337364586 ps |
| CPU time | 5.11 seconds |
| Started | Aug 28 10:51:48 PM UTC 24 |
| Finished | Aug 28 10:51:54 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747155846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3747155846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.739946800 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2413897236 ps |
| CPU time | 8.8 seconds |
| Started | Aug 28 10:51:47 PM UTC 24 |
| Finished | Aug 28 10:51:57 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739946800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.739946800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.300552069 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 320539075 ps |
| CPU time | 7.16 seconds |
| Started | Aug 28 10:51:47 PM UTC 24 |
| Finished | Aug 28 10:51:55 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300552069 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.300552069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.2084478371 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 136796425 ps |
| CPU time | 4.13 seconds |
| Started | Aug 28 10:51:47 PM UTC 24 |
| Finished | Aug 28 10:51:52 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084478371 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2084478371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.433333687 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 105833152 ps |
| CPU time | 4.03 seconds |
| Started | Aug 28 10:51:48 PM UTC 24 |
| Finished | Aug 28 10:51:53 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433333687 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.433333687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3616462270 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 89533944 ps |
| CPU time | 3.25 seconds |
| Started | Aug 28 10:51:51 PM UTC 24 |
| Finished | Aug 28 10:51:55 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616462270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3616462270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.3836045104 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 20675425 ps |
| CPU time | 2.41 seconds |
| Started | Aug 28 10:51:47 PM UTC 24 |
| Finished | Aug 28 10:51:50 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836045104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3836045104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.568029485 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 96389668 ps |
| CPU time | 5.86 seconds |
| Started | Aug 28 10:51:49 PM UTC 24 |
| Finished | Aug 28 10:51:56 PM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568029485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.568029485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.3105868094 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 99097155 ps |
| CPU time | 3.13 seconds |
| Started | Aug 28 10:51:52 PM UTC 24 |
| Finished | Aug 28 10:51:56 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105868094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3105868094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.4177169923 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 36346731 ps |
| CPU time | 1.27 seconds |
| Started | Aug 28 10:51:57 PM UTC 24 |
| Finished | Aug 28 10:51:59 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177169923 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.4177169923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.3404744663 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 257634664 ps |
| CPU time | 6.74 seconds |
| Started | Aug 28 10:51:56 PM UTC 24 |
| Finished | Aug 28 10:52:04 PM UTC 24 |
| Peak memory | 218556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404744663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3404744663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.729184742 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 917787355 ps |
| CPU time | 18.76 seconds |
| Started | Aug 28 10:51:55 PM UTC 24 |
| Finished | Aug 28 10:52:15 PM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729184742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.729184742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.672122499 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 337829963 ps |
| CPU time | 5.94 seconds |
| Started | Aug 28 10:51:56 PM UTC 24 |
| Finished | Aug 28 10:52:03 PM UTC 24 |
| Peak memory | 230496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672122499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.672122499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.2783618720 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 68697869 ps |
| CPU time | 4.82 seconds |
| Started | Aug 28 10:51:56 PM UTC 24 |
| Finished | Aug 28 10:52:02 PM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783618720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2783618720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.3389771606 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 40195090 ps |
| CPU time | 3.81 seconds |
| Started | Aug 28 10:51:56 PM UTC 24 |
| Finished | Aug 28 10:52:00 PM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389771606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3389771606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_random.2019613217 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2153237677 ps |
| CPU time | 69.08 seconds |
| Started | Aug 28 10:51:54 PM UTC 24 |
| Finished | Aug 28 10:53:05 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019613217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2019613217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.86297708 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 674948320 ps |
| CPU time | 10.59 seconds |
| Started | Aug 28 10:51:54 PM UTC 24 |
| Finished | Aug 28 10:52:06 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86297708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.86297708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.2069407801 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 88416503 ps |
| CPU time | 3.01 seconds |
| Started | Aug 28 10:51:54 PM UTC 24 |
| Finished | Aug 28 10:51:58 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069407801 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2069407801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.2605638800 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 261041625 ps |
| CPU time | 7.77 seconds |
| Started | Aug 28 10:51:54 PM UTC 24 |
| Finished | Aug 28 10:52:04 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605638800 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2605638800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.1850960045 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 80552718 ps |
| CPU time | 1.91 seconds |
| Started | Aug 28 10:51:54 PM UTC 24 |
| Finished | Aug 28 10:51:57 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850960045 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1850960045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.2779540429 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1650939118 ps |
| CPU time | 11.57 seconds |
| Started | Aug 28 10:51:57 PM UTC 24 |
| Finished | Aug 28 10:52:10 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779540429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2779540429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.3765605818 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 24130268 ps |
| CPU time | 2.38 seconds |
| Started | Aug 28 10:51:53 PM UTC 24 |
| Finished | Aug 28 10:51:56 PM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765605818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3765605818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.1719672350 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 256703937 ps |
| CPU time | 4.85 seconds |
| Started | Aug 28 10:51:56 PM UTC 24 |
| Finished | Aug 28 10:52:01 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719672350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1719672350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
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