Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	46	1			T71	1		T28	1		T224	1
auto[OpGenId]	13	1			T126	1		T33	1		T225	1
auto[OpGenSwOut]	17	1			T6	1		T138	1		T226	1
auto[OpGenHwOut]	19	1			T7	1		T32	1		T8	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1759	1			T11	90		T77	3		T12	180
auto[StInit]	92	1			T40	1		T104	1		T45	1
auto[StCreatorRootKey]	47	1			T6	1		T37	1		T28	1
auto[StOwnerIntKey]	40	1			T78	2		T136	1		T137	1
auto[StOwnerKey]	35	1			T71	1		T36	1		T78	1
auto[StDisabled]	447	1			T72	1		T73	1		T150	1
auto[StInvalid]	47	1			T38	1		T80	1		T54	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3439

1

T1

1

T2

1

T3

1

auto[1]

95

1

T6

1

T71

1

T28

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1751	1			T11	90		T77	3		T12	180
auto[StReset]	auto[1]	8	1			T225	1		T143	1		T144	1
auto[StInit]	auto[0]	54	1			T40	1		T104	1		T45	1
auto[StInit]	auto[1]	38	1			T32	1		T227	1		T101	2
auto[StCreatorRootKey]	auto[0]	31	1			T37	1		T44	1		T77	1
auto[StCreatorRootKey]	auto[1]	16	1			T6	1		T28	1		T126	1
auto[StOwnerIntKey]	auto[0]	26	1			T78	2		T136	1		T137	1
auto[StOwnerIntKey]	auto[1]	14	1			T138	1		T127	1		T149	1
auto[StOwnerKey]	auto[0]	27	1			T36	1		T78	1		T140	1
auto[StOwnerKey]	auto[1]	8	1			T71	1		T141	1		T117	1
auto[StDisabled]	auto[0]	436	1			T72	1		T73	1		T150	1
auto[StDisabled]	auto[1]	11	1			T7	1		T224	1		T116	1
auto[StInvalid]	auto[0]	47	1			T38	1		T80	1		T54	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	3
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	7	1			T143	1		T144	1		T42	1
auto[StReset]	auto[OpGenId]	1	1			T225	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	19	1			T227	1		T146	1		T228	1
auto[StInit]	auto[OpGenId]	5	1			T33	1		T229	1		T230	1
auto[StInit]	auto[OpGenSwOut]	5	1			T226	1		T231	1		T232	1
auto[StInit]	auto[OpGenHwOut]	9	1			T32	1		T101	2		T233	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T28	1		T142	1		T234	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T126	1		T235	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T6	1		T154	1		T236	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T8	1		T237	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T127	1		T155	1		T238	1
auto[StOwnerIntKey]	auto[OpGenId]	4	1			T149	1		T147	1		T239	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T138	1		T240	1		T241	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T242	1		T243	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	5	1			T71	1		T141	1		T117	1
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T244	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T109	1		T245	1		-	-
auto[StDisabled]	auto[OpAdvance]	4	1			T224	1		T116	1		T246	1
auto[StDisabled]	auto[OpGenId]	1	1			T149	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T247	1		T248	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	4	1			T7	1		T249	1		T250	1