Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4721

1

T1

5

T2

9

T3

8

auto[1]

541

1

T1

3

T16

2

T70

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4721

1

T1

5

T2

9

T3

8

auto[1]

541

1

T1

3

T16

2

T70

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4750

1

T1

8

T2

9

T3

4

auto[1]

512

1

T3

4

T4

3

T15

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4750

1

T1

8

T2

9

T3

4

auto[1]

512

1

T3

4

T4

3

T15

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	426	1			T5	4		T18	1		T104	1
auto[OpGenId]	1159	1			T2	5		T4	1		T15	2
auto[OpGenSwOut]	1113	1			T2	3		T4	1		T16	1
auto[OpGenHwOut]	2488	1			T1	8		T2	1		T3	8
auto[OpDisable]	76	1			T16	1		T70	1		T131	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	426	1			T5	4		T18	1		T104	1
auto[OpGenId]	1159	1			T2	5		T4	1		T15	2
auto[OpGenSwOut]	1113	1			T2	3		T4	1		T16	1
auto[OpGenHwOut]	2488	1			T1	8		T2	1		T3	8
auto[OpDisable]	76	1			T16	1		T70	1		T131	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4766

1

T1

8

T2

9

T3

8

auto[1]

496

1

T14

5

T18

2

T159

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4766

1

T1

8

T2

9

T3

8

auto[1]

496

1

T14

5

T18

2

T159

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5003

1

T1

8

T2

9

T3

8

auto[1]

259

1

T4

1

T92

11

T84

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1791	1			T1	2		T2	3		T3	2
auto[1]	674	1			T1	1		T3	2		T5	2
auto[2]	667	1			T1	1		T5	1		T14	1
auto[3]	705	1			T1	1		T2	2		T3	1
auto[4]	364	1			T3	1		T14	1		T38	1
auto[5]	326	1			T1	2		T2	2		T3	1
auto[6]	373	1			T1	1		T2	1		T3	1
auto[7]	362	1			T2	1		T16	1		T20	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1425	1			T1	3		T2	4		T3	3
clear_one[1]	674	1			T1	1		T3	2		T5	2
clear_one[2]	667	1			T1	1		T5	1		T14	1
clear_one[3]	705	1			T1	1		T2	2		T3	1
clear_none	1791	1			T1	2		T2	3		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	978	1			T2	2		T15	1		T16	5
auto[StInit]	678	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	580	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	523	1			T1	1		T3	1		T5	1
auto[StOwnerKey]	468	1			T1	1		T2	1		T3	1
auto[StDisabled]	1793	1			T1	4		T2	4		T3	4
auto[StInvalid]	242	1			T38	3		T39	4		T80	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	978	1			T2	2		T15	1		T16	5
auto[StInit]	678	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	580	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	523	1			T1	1		T3	1		T5	1
auto[StOwnerKey]	468	1			T1	1		T2	1		T3	1
auto[StDisabled]	1793	1			T1	4		T2	4		T3	4
auto[StInvalid]	242	1			T38	3		T39	4		T80	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T251	1		T252	1		T253	1
auto[0]	auto[StReset]	auto[OpGenId]	187	1			T15	1		T158	1		T207	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	170	1			T2	1		T18	1		T104	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	222	1			T16	2		T39	1		T203	1
auto[0]	auto[StInit]	auto[OpAdvance]	49	1			T5	1		T188	1		T126	1
auto[0]	auto[StInit]	auto[OpGenId]	93	1			T72	1		T27	1		T216	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	85	1			T6	1		T70	1		T103	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	198	1			T1	1		T3	1		T14	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T112	2		T141	1		T56	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	65	1			T2	1		T20	1		T72	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	58	1			T160	1		T134	1		T82	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	64	1			T15	1		T159	1		T203	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T209	1		T218	1		T254	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T78	1		T8	1		T255	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	27	1			T110	1		T78	1		T256	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T14	1		T159	1		T220	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T112	1		T257	1		T258	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T209	1		T259	1		T223	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T112	1		T113	1		T218	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T1	1		T4	1		T260	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T88	1		T49	1		T125	1
auto[0]	auto[StDisabled]	auto[OpGenId]	59	1			T2	1		T4	1		T189	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T20	1		T261	1		T74	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T3	1		T14	2		T159	1
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T139	1		T75	1		T8	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	5	1			T262	1		T263	1		T264	1
auto[0]	auto[StInvalid]	auto[OpGenId]	17	1			T38	1		T39	1		T265	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T52	1		T190	1		T266	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T212	1		T267	1		T268	1
auto[1]	auto[StReset]	auto[OpGenId]	14	1			T54	1		T269	1		T102	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	24	1			T16	1		T158	1		T212	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	40	1			T205	1		T190	1		T84	1
auto[1]	auto[StInit]	auto[OpAdvance]	2	1			T270	1		T271	1		-	-
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T15	1		T217	1		T113	2
auto[1]	auto[StInit]	auto[OpGenSwOut]	5	1			T272	1		T273	1		T61	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T274	1		T74	1		T275	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T111	1		T251	1		T276	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T53	1		T255	1		T151	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T277	1		T278	1		T279	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T205	1		T105	1		T106	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T216	1		T7	1		T280	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T19	1		T217	1		T280	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T281	1		T215	1		T282	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T222	1		T283	1		T284	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T5	1		T285	1		T66	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T286	1		T65	1		T76	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T7	1		T76	1		T287	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T3	1		T288	1		T289	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	25	1			T5	1		T27	1		T53	1
auto[1]	auto[StDisabled]	auto[OpGenId]	59	1			T20	1		T216	1		T281	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T18	1		T74	1		T56	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T1	1		T3	1		T14	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T132	1		T74	1		T223	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T290	1		T212	1		T291	1
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T292	1		T293	1		T294	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T52	1		T267	1		T264	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T265	1		T295	1		T296	1
auto[2]	auto[StReset]	auto[OpGenId]	14	1			T207	1		T104	1		T222	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T77	1		T87	1		T290	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	43	1			T220	1		T81	1		T283	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T297	1		T298	1		T299	1
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T110	1		T214	1		T74	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T223	1		T66	1		T300	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T289	1		T32	1		T301	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T28	1		T302	1		T303	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T189	1		T110	1		T74	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T18	1		T141	1		T259	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T220	1		T221	1		T304	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T18	1		T305	1		T306	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T277	1		T307	1		T308	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T125	1		T141	1		T309	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T1	1		T203	1		T221	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T310	1		T311	1		T276	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T312	1		T313	1		T314	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T88	1		T211	1		T149	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T205	1		T221	1		T188	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T5	1		T125	1		T274	1
auto[2]	auto[StDisabled]	auto[OpGenId]	53	1			T188	1		T82	1		T49	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T18	1		T188	1		T88	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T14	1		T202	1		T203	1
auto[2]	auto[StDisabled]	auto[OpDisable]	11	1			T16	1		T133	1		T79	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T214	1		T315	1		T316	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T39	1		T212	1		T292	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T80	1		T190	1		T81	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T317	1		T315	1		T292	1
auto[3]	auto[StReset]	auto[OpGenId]	19	1			T81	1		T224	1		T318	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T74	1		T79	1		T319	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	43	1			T203	1		T205	1		T220	2
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T305	1		T149	1		T320	1
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T92	1		T87	1		T317	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T22	1		T321	1		T322	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	17	1			T279	1		T323	1		T324	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T88	1		T149	1		T325	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T65	1		T326	1		T116	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T327	1		T328	1		T329	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T3	1		T14	1		T330	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T318	1		T251	1		T331	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T74	1		T269	1		T148	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T74	1		T23	1		T332	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T5	1		T103	1		T330	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T84	1		T222	1		T333	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T16	1		T277	1		T8	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T273	1		T334	1		T145	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T203	1		T106	1		T53	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	26	1			T188	1		T189	1		T269	1
auto[3]	auto[StDisabled]	auto[OpGenId]	64	1			T2	2		T73	1		T27	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T4	1		T111	1		T261	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T1	1		T4	1		T159	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T70	1		T335	1		T8	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	11	1			T81	1		T322	1		T336	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T39	1		T80	1		T55	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T54	1		T214	1		T337	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T290	1		T81	1		T266	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T19	1		T145	1		T338	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T147	1		T339	1		T240	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T203	1		T205	1		T283	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T104	1		T125	1		T199	1
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T73	1		T340	2		T341	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T296	1		T302	1		T342	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	13	1			T203	1		T205	1		T220	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T280	1		T340	1		T343	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T8	1		T344	1		T149	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T103	1		T286	1		T141	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T284	1		T345	1		T346	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T347	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T27	1		T87	1		T210	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T20	1		T278	1		T348	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T202	1		T260	1		T289	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T116	1		T349	1		T340	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T8	1		T57	1		T350	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T351	1		T352	1		T325	2
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T14	1		T220	1		T191	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T79	1		T141	1		T353	1
auto[4]	auto[StDisabled]	auto[OpGenId]	33	1			T160	1		T150	1		T82	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T82	1		T256	1		T254	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	62	1			T3	1		T18	1		T205	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T354	1		T355	1		T356	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T214	1		T322	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T39	1		T81	1		T266	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T268	1		T357	1		T300	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T38	1		T80	1		T54	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T2	1		T272	1		T108	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	14	1			T358	1		T359	1		T360	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	15	1			T361	1		T214	1		T317	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T287	2		T362	1		T155	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T360	1		T109	1		T64	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T2	1		T363	1		T147	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T364	1		T365	1		T25	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T301	1		T141	1		T101	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T223	1		T287	1		T325	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T282	1		T366	1		T359	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T1	1		T202	1		T367	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T368	1		T242	1		T343	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T8	1		T251	1		T109	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T188	1		T369	1		T370	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T3	1		T361	1		T371	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T372	1		T373	1		T374	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T19	1		T79	1		T321	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T359	1		T149	1		T201	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T160	1		T105	1		T107	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	14	1			T150	1		T112	2		T74	1
auto[5]	auto[StDisabled]	auto[OpGenId]	22	1			T65	1		T141	1		T8	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T112	1		T74	1		T309	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	62	1			T1	1		T203	1		T221	1
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T153	1		T240	1		T249	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T375	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T265	1		T376	1		T300	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T322	1		T295	1		T377	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T52	1		T266	1		T378	1
auto[6]	auto[StReset]	auto[OpGenId]	13	1			T54	1		T272	1		T109	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T92	1		T88	1		T212	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T16	1		T125	1		T361	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T151	1		T61	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T63	1		T199	1		T379	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T49	1		T116	1		T223	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T222	1		T79	1		T380	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T381	1		T382	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T383	1		T384	1		T151	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T305	1		T311	1		T303	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T107	1		T19	1		T260	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T92	1		T385	1		T386	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T387	1		T388	1		T389	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T390	1		T199	1		T155	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T106	1		T304	1		T367	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T151	1		T391	2		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T83	1		T392	1		T148	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T2	1		T108	1		T393	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	29	1			T159	1		T202	1		T304	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T92	3		T111	1		T394	1
auto[6]	auto[StDisabled]	auto[OpGenId]	26	1			T207	1		T274	1		T277	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T92	2		T19	1		T74	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T1	1		T3	1		T159	2
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T131	1		T338	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T290	1		T81	1		T336	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T38	1		T292	1		T295	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T376	2		T294	1		T395	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T54	1		T268	1		T322	1
auto[7]	auto[StReset]	auto[OpGenId]	4	1			T223	1		T396	1		T341	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	13	1			T141	1		T259	1		T147	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	15	1			T16	1		T361	1		T224	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T84	1		T397	1		T391	2
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T398	1		T199	1		T154	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T399	1		T152	1		T232	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T361	1		T400	1		T401	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T92	1		T113	2		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T84	1		T138	1		T331	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T321	1		T308	1		T149	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T92	2		T283	1		T402	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T403	1		T404	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T92	4		T49	1		T141	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T88	2		T113	1		T314	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T205	1		T191	1		T88	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T276	1		T405	1		T196	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T406	1		T407	1		T408	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T141	2		T331	1		T409	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T74	1		T410	1		T411	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T49	1		T254	1		T394	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T141	2		T309	1		T115	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T20	1		T70	1		T261	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T2	1		T205	1		T260	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T148	1		T412	1		T413	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T212	1		T267	1		T397	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T52	1		T55	1		T295	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T190	1		T267	1		T292	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T266	2		T357	1		T292	1