Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1425

1

T1

3

T2

4

T3

3

clear_one[1]

auto[0]

auto[0]

auto[0]

396

1

T1

1

T5

2

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

129

1

T14

1

T18

1

T205

2

clear_one[1]

auto[0]

auto[1]

auto[0]

111

1

T3

2

T202

1

T106

2

clear_one[1]

auto[0]

auto[1]

auto[1]

38

1

T53

1

T222

1

T58

1

clear_one[2]

auto[0]

auto[0]

auto[0]

402

1

T5

1

T39

1

T18

2

clear_one[2]

auto[0]

auto[0]

auto[1]

107

1

T14

1

T18

1

T205

2

clear_one[2]

auto[1]

auto[0]

auto[0]

129

1

T1

1

T16

1

T203

2

clear_one[2]

auto[1]

auto[0]

auto[1]

29

1

T218

1

T399

1

T279

1

clear_one[3]

auto[0]

auto[0]

auto[0]

395

1

T2

2

T5

1

T14

1

clear_one[3]

auto[0]

auto[1]

auto[0]

118

1

T3

1

T4

2

T202

1

clear_one[3]

auto[1]

auto[0]

auto[0]

140

1

T1

1

T16

1

T203

2

clear_one[3]

auto[1]

auto[1]

auto[0]

52

1

T70

1

T84

2

T113

1

clear_none

auto[0]

auto[0]

auto[0]

1341

1

T1

1

T2

3

T3

1

clear_none

auto[0]

auto[0]

auto[1]

120

1

T14

3

T159

3

T191

2

clear_none

auto[0]

auto[1]

auto[0]

116

1

T3

1

T4

1

T15

1

clear_none

auto[0]

auto[1]

auto[1]

23

1

T58

1

T352

1

T147

1

clear_none

auto[1]

auto[0]

auto[0]

111

1

T1

1

T203

1

T220

1

clear_none

auto[1]

auto[0]

auto[1]

26

1

T160

1

T112

3

T414

1

clear_none

auto[1]

auto[1]

auto[0]

30

1

T189

1

T216

1

T84

1

clear_none

auto[1]

auto[1]

auto[1]

24

1

T53

1

T112

2

T113

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1334	1			T1	3		T2	4		T3	3
clear_all	auto[1]	91	1			T92	11		T84	1		T88	2
clear_one[1]	auto[0]	641	1			T1	1		T3	2		T5	2
clear_one[1]	auto[1]	33	1			T113	3		T251	1		T280	4
clear_one[2]	auto[0]	640	1			T1	1		T5	1		T14	1
clear_one[2]	auto[1]	27	1			T88	2		T310	1		T311	1
clear_one[3]	auto[0]	662	1			T1	1		T2	2		T3	1
clear_one[3]	auto[1]	43	1			T4	1		T84	1		T115	1
clear_none	auto[0]	1726	1			T1	2		T2	3		T3	2
clear_none	auto[1]	65	1			T88	2		T125	2		T112	4