Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11087

1

T1

4

T2

13

T3

4

auto[Attestation]

7686

1

T1

4

T2

5

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2708	1			T2	2		T4	5		T5	4
auto[Aes]	3423	1			T1	8		T2	3		T4	1
auto[Kmac]	3307	1			T2	2		T3	8		T4	3
auto[Otbn]	3359	1			T2	2		T4	2		T14	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7520	1			T1	8		T2	8		T3	8
auto[OpGenId]	5976	1			T2	9		T4	5		T5	1
auto[OpGenSwOut]	5944	1			T2	7		T4	3		T5	3
auto[OpGenHwOut]	6853	1			T1	8		T2	2		T3	8
auto[OpDisable]	142	1			T16	1		T70	1		T103	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10470

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

15965

1

T1

8

T2

18

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6460	1			T1	1		T2	11		T3	1
auto[StInit]	3730	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3157	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2726	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2448	1			T1	2		T2	2		T3	2
auto[StDisabled]	7914	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	322	1			T5	1		T16	2		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T21	1		T28	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T18	1		T37	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	78	1			T20	1		T36	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	66	1			T2	1		T73	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	203	1			T5	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	351	1			T2	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	100	1			T2	1		T70	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	88	1			T17	1		T208	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	80	1			T73	1		T92	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T71	1		T73	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	225	1			T4	1		T16	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	358	1			T2	1		T17	2		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	106	1			T16	1		T6	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T207	1		T83	1		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T92	1		T188	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T17	1		T92	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	181	1			T16	1		T18	2		T208	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	336	1			T2	2		T16	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	104	1			T6	1		T17	1		T158	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T82	1		T58	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	57	1			T189	1		T88	2		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T19	1		T211	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	239	1			T208	1		T103	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	65	1			T212	1		T141	4		T148	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	89	1			T4	1		T158	1		T150	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T44	1		T78	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T16	1		T71	1		T73	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	69	1			T208	1		T19	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	229	1			T5	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	61	1			T54	1		T214	1		T141	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	114	1			T71	1		T72	1		T103	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T16	2		T18	1		T160	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T215	1		T78	1		T141	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	59	1			T72	1		T92	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	240	1			T18	1		T72	1		T92	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T214	1		T212	3		T141	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	88	1			T6	1		T207	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T15	1		T103	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T2	1		T158	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	71	1			T19	1		T216	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	205	1			T4	1		T18	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	85	1			T54	1		T141	5		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	97	1			T18	1		T70	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T73	1		T44	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T73	1		T110	1		T217	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	71	1			T188	1		T216	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	217	1			T18	1		T21	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	300	1			T2	1		T16	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T4	1		T20	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	69	1			T20	1		T189	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	45	1			T5	1		T218	1		T141	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	67	1			T4	1		T16	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	182	1			T4	1		T72	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	415	1			T16	2		T39	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	134	1			T1	1		T158	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	111	1			T1	1		T203	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	95	1			T158	2		T203	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	85	1			T220	1		T221	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	278	1			T1	2		T2	1		T160	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	432	1			T39	3		T18	1		T158	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T3	1		T158	1		T160	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T15	2		T202	1		T106	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T73	1		T106	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T36	1		T150	2		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	265	1			T3	3		T16	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	425	1			T16	3		T158	1		T205	8
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T4	1		T15	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	103	1			T159	1		T205	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T159	1		T205	1		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T205	1		T191	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	287	1			T4	1		T14	3		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T214	1		T74	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	85	1			T16	1		T20	1		T70	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T4	1		T87	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T86	1		T111	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T86	1		T53	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T18	1		T20	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	45	1			T212	1		T141	2		T148	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T220	1		T221	1		T105	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	125	1			T15	1		T70	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	103	1			T1	1		T220	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	87	1			T1	1		T16	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	288	1			T1	2		T203	1		T220	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T54	2		T212	2		T141	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	121	1			T15	1		T71	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	117	1			T3	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T3	1		T71	1		T158	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	78	1			T3	1		T160	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	302	1			T3	1		T4	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T141	2		T223	3		T149	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T14	1		T219	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T14	1		T15	1		T150	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	104	1			T14	1		T71	1		T158	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	87	1			T14	1		T71	1		T159	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T14	1		T18	1		T159	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	211	1			T2	1		T18	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	635	1			T5	2		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	213	1			T17	1		T71	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	690	1			T2	2		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	205	1			T17	1		T207	1		T92	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	666	1			T2	1		T16	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	184	1			T19	1		T189	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	690	1			T2	2		T16	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	189	1			T16	1		T71	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	405	1			T4	1		T5	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	198	1			T16	2		T18	1		T160	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	433	1			T71	1		T18	1		T72	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T2	1		T15	1		T158	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	385	1			T4	1		T6	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	210	1			T73	2		T44	1		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	414	1			T18	2		T70	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T4	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	600	1			T2	1		T4	2		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	275	1			T1	1		T158	2		T203	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	843	1			T1	3		T2	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	239	1			T15	2		T202	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	829	1			T3	4		T16	1		T39	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T159	2		T205	3		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	848	1			T4	2		T14	3		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	172	1			T4	1		T86	2		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	330	1			T16	1		T18	1		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	298	1			T1	2		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	473	1			T1	2		T203	1		T220	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T3	3		T15	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	503	1			T3	1		T4	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	274	1			T14	3		T15	1		T71	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	479	1			T14	2		T18	1		T159	1