Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32104

1

T1

20

T2

29

T3

19

auto[1]

312

1

T4

2

T92

11

T84

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32113	1			T1	20		T2	29		T3	19
auto[134217728:268435455]	16	1			T92	1		T88	1		T112	1
auto[268435456:402653183]	5	1			T437	1		T438	1		T439	1
auto[402653184:536870911]	12	1			T4	1		T112	1		T218	1
auto[536870912:671088639]	11	1			T125	1		T113	1		T254	1
auto[671088640:805306367]	9	1			T92	1		T113	1		T115	1
auto[805306368:939524095]	7	1			T254	1		T252	2		T387	1
auto[939524096:1073741823]	12	1			T84	1		T112	1		T254	1
auto[1073741824:1207959551]	10	1			T92	2		T113	1		T218	1
auto[1207959552:1342177279]	11	1			T351	1		T280	1		T311	1
auto[1342177280:1476395007]	3	1			T88	1		T437	1		T440	1
auto[1476395008:1610612735]	11	1			T254	1		T310	1		T287	1
auto[1610612736:1744830463]	12	1			T113	1		T351	1		T254	1
auto[1744830464:1879048191]	10	1			T92	1		T254	1		T441	1
auto[1879048192:2013265919]	6	1			T4	1		T252	1		T276	1
auto[2013265920:2147483647]	17	1			T88	1		T254	1		T280	1
auto[2147483648:2281701375]	9	1			T92	1		T88	1		T311	1
auto[2281701376:2415919103]	8	1			T218	1		T280	1		T310	1
auto[2415919104:2550136831]	11	1			T113	1		T442	1		T348	2
auto[2550136832:2684354559]	9	1			T92	1		T287	1		T348	1
auto[2684354560:2818572287]	9	1			T92	1		T112	1		T287	1
auto[2818572288:2952790015]	8	1			T441	1		T424	1		T443	1
auto[2952790016:3087007743]	12	1			T88	1		T113	2		T351	1
auto[3087007744:3221225471]	10	1			T310	1		T348	1		T444	1
auto[3221225472:3355443199]	13	1			T92	2		T113	1		T254	1
auto[3355443200:3489660927]	12	1			T113	1		T115	1		T254	3
auto[3489660928:3623878655]	12	1			T84	1		T113	1		T270	1
auto[3623878656:3758096383]	10	1			T113	1		T115	2		T311	1
auto[3758096384:3892314111]	4	1			T252	1		T443	1		T445	1
auto[3892314112:4026531839]	12	1			T112	1		T113	1		T218	1
auto[4026531840:4160749567]	7	1			T92	1		T88	1		T442	1
auto[4160749568:4294967295]	5	1			T113	2		T254	1		T348	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32104	1			T1	20		T2	29		T3	19
auto[0:134217727]	auto[1]	9	1			T113	1		T218	1		T348	1
auto[134217728:268435455]	auto[1]	16	1			T92	1		T88	1		T112	1
auto[268435456:402653183]	auto[1]	5	1			T437	1		T438	1		T439	1
auto[402653184:536870911]	auto[1]	12	1			T4	1		T112	1		T218	1
auto[536870912:671088639]	auto[1]	11	1			T125	1		T113	1		T254	1
auto[671088640:805306367]	auto[1]	9	1			T92	1		T113	1		T115	1
auto[805306368:939524095]	auto[1]	7	1			T254	1		T252	2		T387	1
auto[939524096:1073741823]	auto[1]	12	1			T84	1		T112	1		T254	1
auto[1073741824:1207959551]	auto[1]	10	1			T92	2		T113	1		T218	1
auto[1207959552:1342177279]	auto[1]	11	1			T351	1		T280	1		T311	1
auto[1342177280:1476395007]	auto[1]	3	1			T88	1		T437	1		T440	1
auto[1476395008:1610612735]	auto[1]	11	1			T254	1		T310	1		T287	1
auto[1610612736:1744830463]	auto[1]	12	1			T113	1		T351	1		T254	1
auto[1744830464:1879048191]	auto[1]	10	1			T92	1		T254	1		T441	1
auto[1879048192:2013265919]	auto[1]	6	1			T4	1		T252	1		T276	1
auto[2013265920:2147483647]	auto[1]	17	1			T88	1		T254	1		T280	1
auto[2147483648:2281701375]	auto[1]	9	1			T92	1		T88	1		T311	1
auto[2281701376:2415919103]	auto[1]	8	1			T218	1		T280	1		T310	1
auto[2415919104:2550136831]	auto[1]	11	1			T113	1		T442	1		T348	2
auto[2550136832:2684354559]	auto[1]	9	1			T92	1		T287	1		T348	1
auto[2684354560:2818572287]	auto[1]	9	1			T92	1		T112	1		T287	1
auto[2818572288:2952790015]	auto[1]	8	1			T441	1		T424	1		T443	1
auto[2952790016:3087007743]	auto[1]	12	1			T88	1		T113	2		T351	1
auto[3087007744:3221225471]	auto[1]	10	1			T310	1		T348	1		T444	1
auto[3221225472:3355443199]	auto[1]	13	1			T92	2		T113	1		T254	1
auto[3355443200:3489660927]	auto[1]	12	1			T113	1		T115	1		T254	3
auto[3489660928:3623878655]	auto[1]	12	1			T84	1		T113	1		T270	1
auto[3623878656:3758096383]	auto[1]	10	1			T113	1		T115	2		T311	1
auto[3758096384:3892314111]	auto[1]	4	1			T252	1		T443	1		T445	1
auto[3892314112:4026531839]	auto[1]	12	1			T112	1		T113	1		T218	1
auto[4026531840:4160749567]	auto[1]	7	1			T92	1		T88	1		T442	1
auto[4160749568:4294967295]	auto[1]	5	1			T113	2		T254	1		T348	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1663

1

T5

1

T16

1

T6

2

auto[1]

1758

1

T4

2

T5

4

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T4	1		T38	1		T19	1
auto[134217728:268435455]	111	1			T73	1		T19	1		T189	1
auto[268435456:402653183]	99	1			T16	2		T30	1		T446	2
auto[402653184:536870911]	92	1			T71	1		T150	1		T88	1
auto[536870912:671088639]	109	1			T52	1		T139	1		T215	1
auto[671088640:805306367]	112	1			T38	1		T72	1		T73	1
auto[805306368:939524095]	102	1			T92	1		T77	1		T217	1
auto[939524096:1073741823]	112	1			T5	1		T158	1		T92	1
auto[1073741824:1207959551]	113	1			T16	1		T71	1		T20	1
auto[1207959552:1342177279]	98	1			T52	2		T84	2		T363	1
auto[1342177280:1476395007]	88	1			T18	2		T216	1		T53	1
auto[1476395008:1610612735]	118	1			T6	1		T38	1		T73	1
auto[1610612736:1744830463]	100	1			T72	1		T54	1		T55	2
auto[1744830464:1879048191]	103	1			T104	1		T266	1		T138	1
auto[1879048192:2013265919]	110	1			T5	1		T15	1		T19	1
auto[2013265920:2147483647]	120	1			T15	1		T150	1		T82	1
auto[2147483648:2281701375]	111	1			T20	1		T92	1		T54	1
auto[2281701376:2415919103]	107	1			T219	1		T216	1		T49	1
auto[2415919104:2550136831]	100	1			T5	1		T16	1		T71	1
auto[2550136832:2684354559]	98	1			T38	1		T72	1		T27	1
auto[2684354560:2818572287]	120	1			T72	1		T28	1		T215	1
auto[2818572288:2952790015]	111	1			T16	1		T39	1		T80	1
auto[2952790016:3087007743]	116	1			T104	1		T111	1		T290	1
auto[3087007744:3221225471]	109	1			T39	1		T80	1		T27	2
auto[3221225472:3355443199]	104	1			T39	1		T188	1		T217	1
auto[3355443200:3489660927]	105	1			T39	1		T18	1		T20	1
auto[3489660928:3623878655]	105	1			T5	1		T188	1		T266	1
auto[3623878656:3758096383]	105	1			T71	1		T20	1		T188	1
auto[3758096384:3892314111]	107	1			T4	1		T5	1		T6	1
auto[3892314112:4026531839]	112	1			T71	1		T80	1		T52	1
auto[4026531840:4160749567]	98	1			T38	2		T39	1		T29	1
auto[4160749568:4294967295]	106	1			T83	1		T86	1		T125	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T38	1		T189	1		T190	2
auto[0:134217727]	auto[1]	65	1			T4	1		T19	1		T84	1
auto[134217728:268435455]	auto[0]	47	1			T189	1		T190	1		T77	1
auto[134217728:268435455]	auto[1]	64	1			T73	1		T19	1		T190	1
auto[268435456:402653183]	auto[0]	50	1			T446	1		T267	1		T22	1
auto[268435456:402653183]	auto[1]	49	1			T16	2		T30	1		T446	1
auto[402653184:536870911]	auto[0]	47	1			T71	1		T150	1		T363	1
auto[402653184:536870911]	auto[1]	45	1			T88	1		T53	1		T131	1
auto[536870912:671088639]	auto[0]	57	1			T52	1		T215	1		T81	1
auto[536870912:671088639]	auto[1]	52	1			T139	1		T126	1		T78	1
auto[671088640:805306367]	auto[0]	58	1			T38	1		T77	1		T290	1
auto[671088640:805306367]	auto[1]	54	1			T72	1		T73	1		T103	1
auto[805306368:939524095]	auto[0]	52	1			T77	1		T217	1		T266	1
auto[805306368:939524095]	auto[1]	50	1			T92	1		T74	1		T447	1
auto[939524096:1073741823]	auto[0]	59	1			T5	1		T189	1		T84	1
auto[939524096:1073741823]	auto[1]	53	1			T158	1		T92	1		T188	1
auto[1073741824:1207959551]	auto[0]	51	1			T20	1		T28	1		T77	1
auto[1073741824:1207959551]	auto[1]	62	1			T16	1		T71	1		T92	1
auto[1207959552:1342177279]	auto[0]	53	1			T52	2		T84	2		T363	1
auto[1207959552:1342177279]	auto[1]	45	1			T435	1		T212	1		T142	1
auto[1342177280:1476395007]	auto[0]	38	1			T18	1		T32	1		T74	1
auto[1342177280:1476395007]	auto[1]	50	1			T18	1		T216	1		T53	1
auto[1476395008:1610612735]	auto[0]	59	1			T6	1		T38	1		T215	1
auto[1476395008:1610612735]	auto[1]	59	1			T73	1		T27	1		T189	1
auto[1610612736:1744830463]	auto[0]	51	1			T54	1		T41	1		T431	1
auto[1610612736:1744830463]	auto[1]	49	1			T72	1		T55	2		T7	1
auto[1744830464:1879048191]	auto[0]	51	1			T74	1		T58	1		T65	1
auto[1744830464:1879048191]	auto[1]	52	1			T104	1		T266	1		T138	1
auto[1879048192:2013265919]	auto[0]	58	1			T54	1		T84	1		T111	1
auto[1879048192:2013265919]	auto[1]	52	1			T5	1		T15	1		T19	1
auto[2013265920:2147483647]	auto[0]	69	1			T83	1		T84	1		T125	1
auto[2013265920:2147483647]	auto[1]	51	1			T15	1		T150	1		T82	1
auto[2147483648:2281701375]	auto[0]	54	1			T54	1		T82	1		T290	2
auto[2147483648:2281701375]	auto[1]	57	1			T20	1		T92	1		T83	1
auto[2281701376:2415919103]	auto[0]	42	1			T219	1		T216	1		T317	1
auto[2281701376:2415919103]	auto[1]	65	1			T49	1		T351	1		T399	2
auto[2415919104:2550136831]	auto[0]	35	1			T71	1		T189	1		T190	1
auto[2415919104:2550136831]	auto[1]	65	1			T5	1		T16	1		T150	1
auto[2550136832:2684354559]	auto[0]	39	1			T38	1		T54	1		T190	1
auto[2550136832:2684354559]	auto[1]	59	1			T72	1		T27	1		T84	1
auto[2684354560:2818572287]	auto[0]	55	1			T28	1		T274	1		T399	1
auto[2684354560:2818572287]	auto[1]	65	1			T72	1		T215	1		T113	1
auto[2818572288:2952790015]	auto[0]	55	1			T16	1		T39	1		T80	1
auto[2818572288:2952790015]	auto[1]	56	1			T125	1		T215	1		T78	1
auto[2952790016:3087007743]	auto[0]	57	1			T290	1		T49	1		T126	1
auto[2952790016:3087007743]	auto[1]	59	1			T104	1		T111	1		T351	1
auto[3087007744:3221225471]	auto[0]	53	1			T39	1		T80	1		T88	1
auto[3087007744:3221225471]	auto[1]	56	1			T27	2		T29	1		T435	1
auto[3221225472:3355443199]	auto[0]	54	1			T39	1		T188	1		T217	1
auto[3221225472:3355443199]	auto[1]	50	1			T261	1		T79	1		T335	1
auto[3355443200:3489660927]	auto[0]	50	1			T18	1		T80	1		T138	1
auto[3355443200:3489660927]	auto[1]	55	1			T39	1		T20	1		T83	1
auto[3489660928:3623878655]	auto[0]	48	1			T266	1		T213	1		T74	1
auto[3489660928:3623878655]	auto[1]	57	1			T5	1		T188	1		T214	1
auto[3623878656:3758096383]	auto[0]	50	1			T188	1		T82	1		T112	1
auto[3623878656:3758096383]	auto[1]	55	1			T71	1		T20	1		T190	1
auto[3758096384:3892314111]	auto[0]	55	1			T6	1		T150	1		T53	1
auto[3758096384:3892314111]	auto[1]	52	1			T4	1		T5	1		T18	1
auto[3892314112:4026531839]	auto[0]	52	1			T80	1		T52	1		T54	1
auto[3892314112:4026531839]	auto[1]	60	1			T71	1		T84	1		T209	1
auto[4026531840:4160749567]	auto[0]	50	1			T38	2		T39	1		T138	1
auto[4026531840:4160749567]	auto[1]	48	1			T29	1		T209	1		T112	1
auto[4160749568:4294967295]	auto[0]	59	1			T86	1		T74	1		T141	1
auto[4160749568:4294967295]	auto[1]	47	1			T83	1		T125	1		T112	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1689

1

T4

1

T5

2

T16

1

auto[1]

1732

1

T4

1

T5

3

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T222	1		T112	1		T363	1
auto[134217728:268435455]	114	1			T5	1		T39	1		T290	1
auto[268435456:402653183]	97	1			T219	1		T27	1		T52	1
auto[402653184:536870911]	104	1			T20	1		T72	1		T190	2
auto[536870912:671088639]	117	1			T20	1		T88	1		T290	1
auto[671088640:805306367]	100	1			T5	1		T71	1		T39	1
auto[805306368:939524095]	98	1			T4	1		T72	1		T103	1
auto[939524096:1073741823]	111	1			T71	1		T18	1		T188	1
auto[1073741824:1207959551]	125	1			T38	2		T71	1		T52	1
auto[1207959552:1342177279]	108	1			T92	1		T217	1		T266	1
auto[1342177280:1476395007]	115	1			T4	1		T16	2		T19	1
auto[1476395008:1610612735]	100	1			T16	1		T39	1		T104	1
auto[1610612736:1744830463]	95	1			T92	1		T52	1		T189	2
auto[1744830464:1879048191]	99	1			T104	1		T188	1		T54	1
auto[1879048192:2013265919]	93	1			T71	1		T39	1		T18	1
auto[2013265920:2147483647]	102	1			T6	1		T158	1		T73	1
auto[2147483648:2281701375]	97	1			T80	2		T190	1		T209	1
auto[2281701376:2415919103]	110	1			T150	1		T77	1		T53	1
auto[2415919104:2550136831]	96	1			T16	1		T72	1		T19	1
auto[2550136832:2684354559]	103	1			T188	1		T150	1		T190	1
auto[2684354560:2818572287]	119	1			T15	1		T73	1		T19	1
auto[2818572288:2952790015]	110	1			T27	1		T82	1		T83	1
auto[2952790016:3087007743]	120	1			T72	1		T28	1		T190	1
auto[3087007744:3221225471]	113	1			T52	2		T216	1		T88	1
auto[3221225472:3355443199]	110	1			T73	1		T80	2		T150	1
auto[3355443200:3489660927]	119	1			T38	1		T188	1		T189	1
auto[3489660928:3623878655]	113	1			T38	1		T28	1		T77	1
auto[3623878656:3758096383]	114	1			T15	1		T20	1		T92	1
auto[3758096384:3892314111]	108	1			T5	1		T6	1		T38	1
auto[3892314112:4026531839]	86	1			T38	1		T71	1		T18	1
auto[4026531840:4160749567]	109	1			T5	1		T27	1		T7	1
auto[4160749568:4294967295]	106	1			T5	1		T16	1		T18	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	60	1			T112	1		T363	1		T81	1
auto[0:134217727]	auto[1]	50	1			T222	1		T81	1		T446	1
auto[134217728:268435455]	auto[0]	56	1			T39	1		T49	1		T266	1
auto[134217728:268435455]	auto[1]	58	1			T5	1		T290	1		T55	1
auto[268435456:402653183]	auto[0]	49	1			T219	1		T52	1		T54	1
auto[268435456:402653183]	auto[1]	48	1			T27	1		T54	1		T29	1
auto[402653184:536870911]	auto[0]	60	1			T190	2		T290	1		T222	1
auto[402653184:536870911]	auto[1]	44	1			T20	1		T72	1		T84	1
auto[536870912:671088639]	auto[0]	58	1			T88	1		T290	1		T214	1
auto[536870912:671088639]	auto[1]	59	1			T20	1		T55	1		T274	1
auto[671088640:805306367]	auto[0]	49	1			T290	2		T74	1		T142	1
auto[671088640:805306367]	auto[1]	51	1			T5	1		T71	1		T39	1
auto[805306368:939524095]	auto[0]	41	1			T138	1		T74	1		T335	1
auto[805306368:939524095]	auto[1]	57	1			T4	1		T72	1		T103	1
auto[939524096:1073741823]	auto[0]	42	1			T188	1		T77	1		T84	1
auto[939524096:1073741823]	auto[1]	69	1			T71	1		T18	1		T78	1
auto[1073741824:1207959551]	auto[0]	73	1			T38	2		T52	1		T54	1
auto[1073741824:1207959551]	auto[1]	52	1			T71	1		T83	1		T269	1
auto[1207959552:1342177279]	auto[0]	54	1			T217	1		T266	1		T74	1
auto[1207959552:1342177279]	auto[1]	54	1			T92	1		T138	1		T447	1
auto[1342177280:1476395007]	auto[0]	51	1			T4	1		T84	1		T217	1
auto[1342177280:1476395007]	auto[1]	64	1			T16	2		T19	1		T7	1
auto[1476395008:1610612735]	auto[0]	51	1			T16	1		T39	1		T216	1
auto[1476395008:1610612735]	auto[1]	49	1			T104	1		T131	1		T214	1
auto[1610612736:1744830463]	auto[0]	42	1			T52	1		T189	1		T83	1
auto[1610612736:1744830463]	auto[1]	53	1			T92	1		T189	1		T216	1
auto[1744830464:1879048191]	auto[0]	49	1			T188	1		T84	1		T290	1
auto[1744830464:1879048191]	auto[1]	50	1			T104	1		T54	1		T35	1
auto[1879048192:2013265919]	auto[0]	41	1			T39	1		T189	1		T30	1
auto[1879048192:2013265919]	auto[1]	52	1			T71	1		T18	1		T20	1
auto[2013265920:2147483647]	auto[0]	43	1			T6	1		T81	1		T213	1
auto[2013265920:2147483647]	auto[1]	59	1			T158	1		T73	1		T125	1
auto[2147483648:2281701375]	auto[0]	52	1			T80	2		T190	1		T217	1
auto[2147483648:2281701375]	auto[1]	45	1			T209	1		T214	1		T58	1
auto[2281701376:2415919103]	auto[0]	51	1			T77	1		T53	1		T266	1
auto[2281701376:2415919103]	auto[1]	59	1			T150	1		T209	1		T49	1
auto[2415919104:2550136831]	auto[0]	43	1			T88	1		T215	1		T213	1
auto[2415919104:2550136831]	auto[1]	53	1			T16	1		T72	1		T19	1
auto[2550136832:2684354559]	auto[0]	51	1			T150	1		T88	1		T222	1
auto[2550136832:2684354559]	auto[1]	52	1			T188	1		T190	1		T83	1
auto[2684354560:2818572287]	auto[0]	58	1			T80	1		T150	1		T49	1
auto[2684354560:2818572287]	auto[1]	61	1			T15	1		T73	1		T19	1
auto[2818572288:2952790015]	auto[0]	49	1			T82	1		T83	1		T81	1
auto[2818572288:2952790015]	auto[1]	61	1			T27	1		T139	1		T29	1
auto[2952790016:3087007743]	auto[0]	66	1			T190	1		T290	1		T113	1
auto[2952790016:3087007743]	auto[1]	54	1			T72	1		T28	1		T84	1
auto[3087007744:3221225471]	auto[0]	44	1			T52	2		T113	1		T218	1
auto[3087007744:3221225471]	auto[1]	69	1			T216	1		T88	1		T111	1
auto[3221225472:3355443199]	auto[0]	63	1			T80	2		T150	1		T84	1
auto[3221225472:3355443199]	auto[1]	47	1			T73	1		T83	1		T29	1
auto[3355443200:3489660927]	auto[0]	60	1			T38	1		T189	1		T54	1
auto[3355443200:3489660927]	auto[1]	59	1			T188	1		T113	1		T214	1
auto[3489660928:3623878655]	auto[0]	62	1			T38	1		T28	1		T77	1
auto[3489660928:3623878655]	auto[1]	51	1			T113	1		T74	1		T79	2
auto[3623878656:3758096383]	auto[0]	65	1			T20	1		T77	1		T363	1
auto[3623878656:3758096383]	auto[1]	49	1			T15	1		T92	1		T78	1
auto[3758096384:3892314111]	auto[0]	56	1			T5	1		T6	1		T38	1
auto[3758096384:3892314111]	auto[1]	52	1			T188	1		T53	1		T215	1
auto[3892314112:4026531839]	auto[0]	40	1			T38	1		T71	1		T18	1
auto[3892314112:4026531839]	auto[1]	46	1			T53	1		T290	1		T126	1
auto[4026531840:4160749567]	auto[0]	56	1			T317	1		T212	1		T76	1
auto[4026531840:4160749567]	auto[1]	53	1			T5	1		T27	1		T7	1
auto[4160749568:4294967295]	auto[0]	54	1			T5	1		T18	1		T92	1
auto[4160749568:4294967295]	auto[1]	52	1			T16	1		T53	1		T55	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1678

1

T4

1

T5

2

T16

2

auto[1]

1744

1

T4

1

T5

3

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T53	1		T139	1		T49	1
auto[134217728:268435455]	91	1			T92	1		T189	1		T53	1
auto[268435456:402653183]	104	1			T150	2		T363	1		T126	1
auto[402653184:536870911]	113	1			T16	1		T72	1		T73	1
auto[536870912:671088639]	103	1			T16	1		T72	1		T52	1
auto[671088640:805306367]	97	1			T5	1		T28	1		T52	1
auto[805306368:939524095]	103	1			T15	1		T71	1		T39	1
auto[939524096:1073741823]	122	1			T38	1		T18	2		T27	1
auto[1073741824:1207959551]	107	1			T38	1		T54	1		T84	1
auto[1207959552:1342177279]	128	1			T104	1		T92	1		T80	1
auto[1342177280:1476395007]	102	1			T71	1		T19	2		T188	1
auto[1476395008:1610612735]	100	1			T52	1		T82	1		T290	2
auto[1610612736:1744830463]	87	1			T15	1		T80	1		T83	1
auto[1744830464:1879048191]	106	1			T71	1		T27	1		T52	1
auto[1879048192:2013265919]	98	1			T4	1		T16	1		T18	1
auto[2013265920:2147483647]	118	1			T19	1		T189	2		T55	1
auto[2147483648:2281701375]	122	1			T20	1		T77	1		T55	1
auto[2281701376:2415919103]	105	1			T39	1		T18	1		T83	1
auto[2415919104:2550136831]	121	1			T5	1		T72	1		T219	1
auto[2550136832:2684354559]	122	1			T38	1		T71	1		T190	1
auto[2684354560:2818572287]	85	1			T190	1		T82	1		T261	1
auto[2818572288:2952790015]	119	1			T16	1		T20	1		T27	1
auto[2952790016:3087007743]	119	1			T5	1		T6	1		T83	1
auto[3087007744:3221225471]	98	1			T6	1		T111	1		T53	1
auto[3221225472:3355443199]	97	1			T5	1		T363	1		T81	1
auto[3355443200:3489660927]	124	1			T39	1		T158	1		T84	1
auto[3489660928:3623878655]	96	1			T4	1		T72	1		T28	1
auto[3623878656:3758096383]	91	1			T5	1		T103	1		T54	1
auto[3758096384:3892314111]	116	1			T39	1		T73	1		T83	1
auto[3892314112:4026531839]	107	1			T16	1		T38	1		T20	1
auto[4026531840:4160749567]	102	1			T38	1		T71	1		T39	1
auto[4160749568:4294967295]	97	1			T38	1		T20	1		T80	1