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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3016 1 T4 2 T5 5 T15 2
auto[1] 303 1 T4 4 T92 15 T84 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 117 1 T6 1 T92 1 T125 1
auto[134217728:268435455] 99 1 T92 1 T80 1 T84 1
auto[268435456:402653183] 91 1 T4 2 T92 1 T216 1
auto[402653184:536870911] 81 1 T4 2 T219 1 T73 1
auto[536870912:671088639] 109 1 T5 1 T16 1 T38 1
auto[671088640:805306367] 112 1 T92 1 T189 1 T77 1
auto[805306368:939524095] 117 1 T5 1 T16 1 T72 1
auto[939524096:1073741823] 115 1 T92 2 T53 2 T112 3
auto[1073741824:1207959551] 106 1 T71 1 T39 1 T27 1
auto[1207959552:1342177279] 86 1 T92 1 T86 1 T88 1
auto[1342177280:1476395007] 95 1 T80 1 T188 1 T82 1
auto[1476395008:1610612735] 126 1 T4 1 T5 1 T92 1
auto[1610612736:1744830463] 107 1 T38 1 T71 1 T39 1
auto[1744830464:1879048191] 112 1 T92 1 T80 1 T27 1
auto[1879048192:2013265919] 95 1 T5 1 T92 2 T54 1
auto[2013265920:2147483647] 115 1 T39 1 T52 1 T189 2
auto[2147483648:2281701375] 101 1 T15 1 T20 1 T103 1
auto[2281701376:2415919103] 87 1 T38 2 T20 1 T72 1
auto[2415919104:2550136831] 117 1 T4 1 T92 3 T150 1
auto[2550136832:2684354559] 109 1 T28 1 T189 1 T190 1
auto[2684354560:2818572287] 96 1 T18 1 T19 1 T82 1
auto[2818572288:2952790015] 109 1 T39 1 T92 1 T19 1
auto[2952790016:3087007743] 99 1 T5 1 T39 1 T84 1
auto[3087007744:3221225471] 100 1 T18 1 T92 2 T80 1
auto[3221225472:3355443199] 101 1 T15 1 T52 1 T150 1
auto[3355443200:3489660927] 84 1 T83 1 T84 2 T88 2
auto[3489660928:3623878655] 86 1 T16 1 T38 1 T18 1
auto[3623878656:3758096383] 111 1 T38 1 T92 1 T52 1
auto[3758096384:3892314111] 106 1 T16 1 T71 1 T20 1
auto[3892314112:4026531839] 108 1 T16 1 T6 1 T18 1
auto[4026531840:4160749567] 109 1 T73 1 T92 1 T189 1
auto[4160749568:4294967295] 113 1 T20 1 T158 1 T52 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 107 1 T6 1 T125 1 T446 1
auto[0:134217727] auto[1] 10 1 T92 1 T311 1 T252 1
auto[134217728:268435455] auto[0] 85 1 T80 1 T84 1 T222 1
auto[134217728:268435455] auto[1] 14 1 T92 1 T115 1 T311 1
auto[268435456:402653183] auto[0] 79 1 T216 1 T49 1 T435 1
auto[268435456:402653183] auto[1] 12 1 T4 2 T92 1 T113 1
auto[402653184:536870911] auto[0] 74 1 T4 2 T219 1 T73 1
auto[402653184:536870911] auto[1] 7 1 T84 1 T437 1 T445 2
auto[536870912:671088639] auto[0] 100 1 T5 1 T16 1 T38 1
auto[536870912:671088639] auto[1] 9 1 T112 1 T115 1 T276 1
auto[671088640:805306367] auto[0] 105 1 T92 1 T189 1 T77 1
auto[671088640:805306367] auto[1] 7 1 T115 1 T254 1 T311 1
auto[805306368:939524095] auto[0] 107 1 T5 1 T16 1 T72 1
auto[805306368:939524095] auto[1] 10 1 T88 1 T254 1 T311 1
auto[939524096:1073741823] auto[0] 108 1 T92 1 T53 2 T112 2
auto[939524096:1073741823] auto[1] 7 1 T92 1 T112 1 T252 1
auto[1073741824:1207959551] auto[0] 96 1 T71 1 T39 1 T27 1
auto[1073741824:1207959551] auto[1] 10 1 T84 1 T112 1 T254 1
auto[1207959552:1342177279] auto[0] 80 1 T86 1 T88 1 T290 1
auto[1207959552:1342177279] auto[1] 6 1 T92 1 T112 1 T311 1
auto[1342177280:1476395007] auto[0] 88 1 T80 1 T188 1 T82 1
auto[1342177280:1476395007] auto[1] 7 1 T88 1 T251 1 T348 1
auto[1476395008:1610612735] auto[0] 114 1 T5 1 T83 1 T53 2
auto[1476395008:1610612735] auto[1] 12 1 T4 1 T92 1 T254 1
auto[1610612736:1744830463] auto[0] 105 1 T38 1 T71 1 T39 1
auto[1610612736:1744830463] auto[1] 2 1 T115 1 T382 1 - -
auto[1744830464:1879048191] auto[0] 95 1 T80 1 T27 1 T188 1
auto[1744830464:1879048191] auto[1] 17 1 T92 1 T351 1 T311 2
auto[1879048192:2013265919] auto[0] 80 1 T5 1 T54 1 T190 2
auto[1879048192:2013265919] auto[1] 15 1 T92 2 T84 1 T115 2
auto[2013265920:2147483647] auto[0] 103 1 T39 1 T52 1 T189 2
auto[2013265920:2147483647] auto[1] 12 1 T115 2 T254 1 T311 1
auto[2147483648:2281701375] auto[0] 96 1 T15 1 T20 1 T103 1
auto[2147483648:2281701375] auto[1] 5 1 T280 1 T379 1 T449 1
auto[2281701376:2415919103] auto[0] 79 1 T38 2 T20 1 T72 1
auto[2281701376:2415919103] auto[1] 8 1 T112 1 T348 1 T443 1
auto[2415919104:2550136831] auto[0] 108 1 T92 1 T150 1 T189 1
auto[2415919104:2550136831] auto[1] 9 1 T4 1 T92 2 T437 1
auto[2550136832:2684354559] auto[0] 95 1 T28 1 T189 1 T190 1
auto[2550136832:2684354559] auto[1] 14 1 T254 1 T311 3 T348 1
auto[2684354560:2818572287] auto[0] 93 1 T18 1 T19 1 T82 1
auto[2684354560:2818572287] auto[1] 3 1 T252 1 T276 1 T443 1
auto[2818572288:2952790015] auto[0] 101 1 T39 1 T19 1 T82 1
auto[2818572288:2952790015] auto[1] 8 1 T92 1 T270 1 T287 1
auto[2952790016:3087007743] auto[0] 87 1 T5 1 T39 1 T84 1
auto[2952790016:3087007743] auto[1] 12 1 T88 3 T270 1 T280 1
auto[3087007744:3221225471] auto[0] 90 1 T18 1 T80 1 T188 1
auto[3087007744:3221225471] auto[1] 10 1 T92 2 T84 1 T311 1
auto[3221225472:3355443199] auto[0] 90 1 T15 1 T52 1 T150 1
auto[3221225472:3355443199] auto[1] 11 1 T113 1 T254 1 T287 1
auto[3355443200:3489660927] auto[0] 79 1 T83 1 T84 2 T88 1
auto[3355443200:3489660927] auto[1] 5 1 T88 1 T113 2 T443 1
auto[3489660928:3623878655] auto[0] 78 1 T16 1 T38 1 T18 1
auto[3489660928:3623878655] auto[1] 8 1 T254 1 T280 1 T252 1
auto[3623878656:3758096383] auto[0] 102 1 T38 1 T92 1 T52 1
auto[3623878656:3758096383] auto[1] 9 1 T112 1 T113 1 T115 1
auto[3758096384:3892314111] auto[0] 95 1 T16 1 T71 1 T20 1
auto[3758096384:3892314111] auto[1] 11 1 T88 1 T287 1 T443 2
auto[3892314112:4026531839] auto[0] 99 1 T16 1 T6 1 T18 1
auto[3892314112:4026531839] auto[1] 9 1 T113 1 T351 1 T254 1
auto[4026531840:4160749567] auto[0] 96 1 T73 1 T189 1 T216 1
auto[4026531840:4160749567] auto[1] 13 1 T92 1 T88 1 T351 1
auto[4160749568:4294967295] auto[0] 102 1 T20 1 T158 1 T52 1
auto[4160749568:4294967295] auto[1] 11 1 T113 2 T115 1 T311 1

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