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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1665 1 T5 1 T16 1 T6 2
auto[1] 1757 1 T4 2 T5 4 T15 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 104 1 T104 1 T189 1 T112 1
auto[134217728:268435455] 121 1 T18 1 T20 1 T103 1
auto[268435456:402653183] 126 1 T20 1 T72 1 T73 1
auto[402653184:536870911] 106 1 T5 1 T16 1 T20 1
auto[536870912:671088639] 112 1 T92 1 T19 1 T216 1
auto[671088640:805306367] 101 1 T39 1 T80 1 T150 1
auto[805306368:939524095] 104 1 T5 1 T18 1 T28 1
auto[939524096:1073741823] 107 1 T5 1 T49 2 T112 1
auto[1073741824:1207959551] 104 1 T5 1 T19 1 T80 1
auto[1207959552:1342177279] 100 1 T15 1 T77 1 T290 2
auto[1342177280:1476395007] 97 1 T6 1 T38 1 T217 1
auto[1476395008:1610612735] 99 1 T5 1 T72 2 T77 1
auto[1610612736:1744830463] 102 1 T54 1 T82 1 T35 1
auto[1744830464:1879048191] 121 1 T71 2 T158 1 T80 1
auto[1879048192:2013265919] 107 1 T4 1 T54 1 T190 1
auto[2013265920:2147483647] 108 1 T16 2 T38 1 T71 1
auto[2147483648:2281701375] 97 1 T16 1 T38 1 T92 1
auto[2281701376:2415919103] 106 1 T104 1 T53 1 T290 1
auto[2415919104:2550136831] 109 1 T38 2 T39 1 T18 1
auto[2550136832:2684354559] 102 1 T6 1 T18 1 T83 1
auto[2684354560:2818572287] 93 1 T16 1 T83 1 T77 1
auto[2818572288:2952790015] 117 1 T38 1 T219 1 T27 1
auto[2952790016:3087007743] 101 1 T71 1 T190 1 T88 1
auto[3087007744:3221225471] 113 1 T28 1 T80 1 T188 1
auto[3221225472:3355443199] 99 1 T71 1 T39 1 T72 1
auto[3355443200:3489660927] 115 1 T29 1 T261 1 T113 1
auto[3489660928:3623878655] 91 1 T39 1 T73 1 T80 1
auto[3623878656:3758096383] 119 1 T188 1 T290 1 T363 1
auto[3758096384:3892314111] 126 1 T39 1 T190 1 T53 1
auto[3892314112:4026531839] 108 1 T4 1 T73 1 T27 1
auto[4026531840:4160749567] 87 1 T15 1 T83 1 T222 1
auto[4160749568:4294967295] 120 1 T52 1 T83 1 T77 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 58 1 T189 1 T112 1 T212 1
auto[0:134217727] auto[1] 46 1 T104 1 T224 1 T448 1
auto[134217728:268435455] auto[0] 44 1 T20 1 T52 1 T274 1
auto[134217728:268435455] auto[1] 77 1 T18 1 T103 1 T92 1
auto[268435456:402653183] auto[0] 64 1 T20 1 T150 1 T190 1
auto[268435456:402653183] auto[1] 62 1 T72 1 T73 1 T216 1
auto[402653184:536870911] auto[0] 48 1 T54 1 T274 1 T74 1
auto[402653184:536870911] auto[1] 58 1 T5 1 T16 1 T20 1
auto[536870912:671088639] auto[0] 54 1 T82 1 T290 1 T49 1
auto[536870912:671088639] auto[1] 58 1 T92 1 T19 1 T216 1
auto[671088640:805306367] auto[0] 45 1 T80 1 T150 1 T189 1
auto[671088640:805306367] auto[1] 56 1 T39 1 T84 2 T88 1
auto[805306368:939524095] auto[0] 40 1 T18 1 T286 1 T141 1
auto[805306368:939524095] auto[1] 64 1 T5 1 T28 1 T27 1
auto[939524096:1073741823] auto[0] 49 1 T49 1 T363 1 T78 1
auto[939524096:1073741823] auto[1] 58 1 T5 1 T49 1 T112 1
auto[1073741824:1207959551] auto[0] 52 1 T80 1 T84 1 T74 1
auto[1073741824:1207959551] auto[1] 52 1 T5 1 T19 1 T150 1
auto[1207959552:1342177279] auto[0] 48 1 T77 1 T290 1 T214 1
auto[1207959552:1342177279] auto[1] 52 1 T15 1 T290 1 T113 1
auto[1342177280:1476395007] auto[0] 51 1 T6 1 T38 1 T217 1
auto[1342177280:1476395007] auto[1] 46 1 T74 1 T270 1 T305 1
auto[1476395008:1610612735] auto[0] 48 1 T5 1 T77 1 T86 1
auto[1476395008:1610612735] auto[1] 51 1 T72 2 T74 1 T351 1
auto[1610612736:1744830463] auto[0] 58 1 T54 1 T82 1 T215 1
auto[1610612736:1744830463] auto[1] 44 1 T35 1 T125 1 T335 1
auto[1744830464:1879048191] auto[0] 58 1 T80 1 T52 1 T188 1
auto[1744830464:1879048191] auto[1] 63 1 T71 2 T158 1 T27 1
auto[1879048192:2013265919] auto[0] 59 1 T54 1 T190 1 T126 1
auto[1879048192:2013265919] auto[1] 48 1 T4 1 T55 1 T78 1
auto[2013265920:2147483647] auto[0] 57 1 T16 1 T38 1 T71 1
auto[2013265920:2147483647] auto[1] 51 1 T16 1 T111 1 T261 1
auto[2147483648:2281701375] auto[0] 36 1 T38 1 T84 1 T215 1
auto[2147483648:2281701375] auto[1] 61 1 T16 1 T92 1 T217 1
auto[2281701376:2415919103] auto[0] 46 1 T81 1 T213 1 T32 1
auto[2281701376:2415919103] auto[1] 60 1 T104 1 T53 1 T290 1
auto[2415919104:2550136831] auto[0] 58 1 T38 1 T39 1 T18 1
auto[2415919104:2550136831] auto[1] 51 1 T38 1 T84 1 T55 2
auto[2550136832:2684354559] auto[0] 51 1 T6 1 T84 2 T111 1
auto[2550136832:2684354559] auto[1] 51 1 T18 1 T83 1 T29 1
auto[2684354560:2818572287] auto[0] 43 1 T83 1 T77 1 T138 1
auto[2684354560:2818572287] auto[1] 50 1 T16 1 T290 1 T209 1
auto[2818572288:2952790015] auto[0] 63 1 T38 1 T219 1 T52 1
auto[2818572288:2952790015] auto[1] 54 1 T27 1 T84 1 T88 1
auto[2952790016:3087007743] auto[0] 49 1 T190 1 T88 1 T290 1
auto[2952790016:3087007743] auto[1] 52 1 T71 1 T53 1 T139 1
auto[3087007744:3221225471] auto[0] 51 1 T28 1 T54 1 T190 1
auto[3087007744:3221225471] auto[1] 62 1 T80 1 T188 1 T190 1
auto[3221225472:3355443199] auto[0] 45 1 T39 1 T52 1 T189 1
auto[3221225472:3355443199] auto[1] 54 1 T71 1 T72 1 T92 1
auto[3355443200:3489660927] auto[0] 57 1 T431 1 T358 1 T279 2
auto[3355443200:3489660927] auto[1] 58 1 T29 1 T261 1 T113 1
auto[3489660928:3623878655] auto[0] 44 1 T39 1 T80 1 T88 1
auto[3489660928:3623878655] auto[1] 47 1 T73 1 T189 1 T139 1
auto[3623878656:3758096383] auto[0] 61 1 T188 1 T266 1 T74 1
auto[3623878656:3758096383] auto[1] 58 1 T290 1 T363 1 T7 2
auto[3758096384:3892314111] auto[0] 76 1 T39 1 T190 1 T53 1
auto[3758096384:3892314111] auto[1] 50 1 T126 1 T261 1 T74 1
auto[3892314112:4026531839] auto[0] 50 1 T84 1 T213 1 T113 1
auto[3892314112:4026531839] auto[1] 58 1 T4 1 T73 1 T27 1
auto[4026531840:4160749567] auto[0] 46 1 T209 1 T363 1 T81 1
auto[4026531840:4160749567] auto[1] 41 1 T15 1 T83 1 T222 1
auto[4160749568:4294967295] auto[0] 56 1 T52 1 T77 1 T290 1
auto[4160749568:4294967295] auto[1] 64 1 T83 1 T53 1 T131 1

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