Unified Coverage Report :: Group Instance : attest_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1676

1

T5

1

T6

2

T38

6

auto[1]

1745

1

T4

2

T5

4

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T16	1		T83	2		T88	1
auto[134217728:268435455]	112	1			T71	1		T28	1		T150	1
auto[268435456:402653183]	109	1			T38	1		T20	1		T92	1
auto[402653184:536870911]	95	1			T73	1		T19	1		T52	1
auto[536870912:671088639]	95	1			T5	1		T16	1		T6	1
auto[671088640:805306367]	117	1			T5	1		T38	1		T71	1
auto[805306368:939524095]	113	1			T52	2		T82	1		T77	1
auto[939524096:1073741823]	106	1			T83	1		T215	1		T266	1
auto[1073741824:1207959551]	99	1			T18	1		T27	1		T189	1
auto[1207959552:1342177279]	107	1			T72	1		T73	1		T188	1
auto[1342177280:1476395007]	114	1			T38	1		T72	1		T189	1
auto[1476395008:1610612735]	100	1			T5	1		T71	1		T80	1
auto[1610612736:1744830463]	112	1			T18	1		T20	1		T49	1
auto[1744830464:1879048191]	99	1			T38	1		T39	1		T158	1
auto[1879048192:2013265919]	122	1			T18	1		T80	2		T54	1
auto[2013265920:2147483647]	103	1			T4	1		T27	1		T150	1
auto[2147483648:2281701375]	111	1			T16	1		T20	1		T80	1
auto[2281701376:2415919103]	93	1			T188	1		T82	1		T290	1
auto[2415919104:2550136831]	114	1			T15	1		T38	1		T39	1
auto[2550136832:2684354559]	92	1			T80	1		T52	1		T290	2
auto[2684354560:2818572287]	114	1			T39	1		T216	1		T82	1
auto[2818572288:2952790015]	96	1			T86	1		T88	1		T55	1
auto[2952790016:3087007743]	110	1			T16	1		T52	1		T188	1
auto[3087007744:3221225471]	114	1			T73	1		T150	1		T88	1
auto[3221225472:3355443199]	119	1			T6	1		T71	1		T39	1
auto[3355443200:3489660927]	109	1			T72	1		T53	1		T363	1
auto[3489660928:3623878655]	122	1			T38	1		T103	1		T104	1
auto[3623878656:3758096383]	100	1			T5	1		T18	1		T20	1
auto[3758096384:3892314111]	99	1			T92	1		T52	1		T84	3
auto[3892314112:4026531839]	103	1			T72	1		T19	1		T150	1
auto[4026531840:4160749567]	116	1			T4	1		T15	1		T71	1
auto[4160749568:4294967295]	103	1			T5	1		T16	1		T39	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T83	1		T88	1		T363	1
auto[0:134217727]	auto[1]	52	1			T16	1		T83	1		T53	1
auto[134217728:268435455]	auto[0]	62	1			T28	1		T150	1		T54	1
auto[134217728:268435455]	auto[1]	50	1			T71	1		T84	1		T209	1
auto[268435456:402653183]	auto[0]	58	1			T38	1		T190	1		T77	1
auto[268435456:402653183]	auto[1]	51	1			T20	1		T92	1		T53	1
auto[402653184:536870911]	auto[0]	53	1			T52	1		T112	1		T402	1
auto[402653184:536870911]	auto[1]	42	1			T73	1		T19	1		T290	1
auto[536870912:671088639]	auto[0]	43	1			T6	1		T84	1		T125	1
auto[536870912:671088639]	auto[1]	52	1			T5	1		T16	1		T290	1
auto[671088640:805306367]	auto[0]	64	1			T5	1		T38	1		T224	1
auto[671088640:805306367]	auto[1]	53	1			T71	1		T27	1		T83	1
auto[805306368:939524095]	auto[0]	52	1			T52	2		T82	1		T77	1
auto[805306368:939524095]	auto[1]	61	1			T84	2		T139	1		T29	1
auto[939524096:1073741823]	auto[0]	50	1			T266	1		T224	1		T262	1
auto[939524096:1073741823]	auto[1]	56	1			T83	1		T215	1		T447	1
auto[1073741824:1207959551]	auto[0]	40	1			T18	1		T189	1		T74	1
auto[1073741824:1207959551]	auto[1]	59	1			T27	1		T53	1		T78	1
auto[1207959552:1342177279]	auto[0]	47	1			T81	2		T213	1		T274	1
auto[1207959552:1342177279]	auto[1]	60	1			T72	1		T73	1		T188	1
auto[1342177280:1476395007]	auto[0]	60	1			T38	1		T189	1		T83	1
auto[1342177280:1476395007]	auto[1]	54	1			T72	1		T113	1		T214	1
auto[1476395008:1610612735]	auto[0]	49	1			T71	1		T80	1		T222	1
auto[1476395008:1610612735]	auto[1]	51	1			T5	1		T214	1		T277	1
auto[1610612736:1744830463]	auto[0]	55	1			T20	1		T363	1		T78	1
auto[1610612736:1744830463]	auto[1]	57	1			T18	1		T49	1		T75	1
auto[1744830464:1879048191]	auto[0]	48	1			T38	1		T39	1		T54	1
auto[1744830464:1879048191]	auto[1]	51	1			T158	1		T317	1		T399	1
auto[1879048192:2013265919]	auto[0]	66	1			T80	1		T53	1		T217	1
auto[1879048192:2013265919]	auto[1]	56	1			T18	1		T80	1		T54	1
auto[2013265920:2147483647]	auto[0]	48	1			T54	1		T190	1		T217	1
auto[2013265920:2147483647]	auto[1]	55	1			T4	1		T27	1		T150	1
auto[2147483648:2281701375]	auto[0]	57	1			T80	1		T189	1		T82	1
auto[2147483648:2281701375]	auto[1]	54	1			T16	1		T20	1		T190	1
auto[2281701376:2415919103]	auto[0]	44	1			T188	1		T82	1		T290	1
auto[2281701376:2415919103]	auto[1]	49	1			T55	1		T222	1		T35	1
auto[2415919104:2550136831]	auto[0]	55	1			T38	1		T92	1		T53	1
auto[2415919104:2550136831]	auto[1]	59	1			T15	1		T39	1		T104	1
auto[2550136832:2684354559]	auto[0]	46	1			T80	1		T52	1		T290	1
auto[2550136832:2684354559]	auto[1]	46	1			T290	1		T112	1		T78	1
auto[2684354560:2818572287]	auto[0]	60	1			T39	1		T77	1		T222	1
auto[2684354560:2818572287]	auto[1]	54	1			T216	1		T82	1		T209	1
auto[2818572288:2952790015]	auto[0]	49	1			T86	1		T88	1		T55	1
auto[2818572288:2952790015]	auto[1]	47	1			T274	1		T141	4		T8	1
auto[2952790016:3087007743]	auto[0]	50	1			T52	1		T84	1		T290	1
auto[2952790016:3087007743]	auto[1]	60	1			T16	1		T188	1		T54	1
auto[3087007744:3221225471]	auto[0]	53	1			T266	1		T138	1		T212	1
auto[3087007744:3221225471]	auto[1]	61	1			T73	1		T150	1		T88	1
auto[3221225472:3355443199]	auto[0]	58	1			T6	1		T39	1		T150	1
auto[3221225472:3355443199]	auto[1]	61	1			T71	1		T92	1		T19	1
auto[3355443200:3489660927]	auto[0]	50	1			T53	1		T363	1		T126	1
auto[3355443200:3489660927]	auto[1]	59	1			T72	1		T132	1		T133	1
auto[3489660928:3623878655]	auto[0]	52	1			T38	1		T28	1		T190	1
auto[3489660928:3623878655]	auto[1]	70	1			T103	1		T104	1		T216	1
auto[3623878656:3758096383]	auto[0]	50	1			T18	1		T20	1		T150	1
auto[3623878656:3758096383]	auto[1]	50	1			T5	1		T261	1		T30	1
auto[3758096384:3892314111]	auto[0]	53	1			T52	1		T84	1		T49	1
auto[3758096384:3892314111]	auto[1]	46	1			T92	1		T84	2		T209	1
auto[3892314112:4026531839]	auto[0]	54	1			T150	1		T217	1		T112	1
auto[3892314112:4026531839]	auto[1]	49	1			T72	1		T19	1		T139	1
auto[4026531840:4160749567]	auto[0]	55	1			T219	1		T290	2		T32	1
auto[4026531840:4160749567]	auto[1]	61	1			T4	1		T15	1		T71	1
auto[4160749568:4294967295]	auto[0]	44	1			T39	1		T190	1		T111	1
auto[4160749568:4294967295]	auto[1]	59	1			T5	1		T16	1		T27	1