| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 87.50 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 8 | 1 | 7 | 87.50 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| invalid_hw_input_cp | 8 | 1 | 7 | 87.50 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 8 | 1 | 7 | 87.50 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| auto[OtpRootKeyValidLow] | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[OtpRootKeyInvalid] | 1 | 1 | T199 | 1 | - | - | - | - | ||||
| auto[LcStateInvalid] | 36 | 1 | T394 | 36 | - | - | - | - | ||||
| auto[OtpDevIdInvalid] | 108 | 1 | T26 | 48 | T58 | 24 | T385 | 12 | ||||
| auto[RomDigestInvalid] | 12 | 1 | T26 | 12 | - | - | - | - | ||||
| auto[RomDigestValidLow] | 60 | 1 | T22 | 12 | T62 | 48 | - | - | ||||
| auto[FlashCreatorSeedInvalid] | 60 | 1 | T58 | 36 | T59 | 24 | - | - | ||||
| auto[FlashOwnerSeedInvalid] | 12 | 1 | T22 | 12 | - | - | - | - |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |