Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4923

1

T2

3

T4

4

T5

6

auto[1]

554

1

T4

4

T18

2

T27

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4923

1

T2

3

T4

4

T5

6

auto[1]

554

1

T4

4

T18

2

T27

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4944

1

T2

3

T4

8

T5

6

auto[1]

533

1

T18

1

T38

3

T48

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4944

1

T2

3

T4

8

T5

6

auto[1]

533

1

T18

1

T38

3

T48

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	438	1			T5	1		T17	1		T27	1
auto[OpGenId]	1191	1			T2	1		T5	1		T16	1
auto[OpGenSwOut]	1217	1			T2	1		T5	1		T16	3
auto[OpGenHwOut]	2565	1			T4	8		T5	3		T16	2
auto[OpDisable]	66	1			T2	1		T111	1		T82	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	438	1			T5	1		T17	1		T27	1
auto[OpGenId]	1191	1			T2	1		T5	1		T16	1
auto[OpGenSwOut]	1217	1			T2	1		T5	1		T16	3
auto[OpGenHwOut]	2565	1			T4	8		T5	3		T16	2
auto[OpDisable]	66	1			T2	1		T111	1		T82	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4940

1

T2

3

T4

8

T5

4

auto[1]

537

1

T5

2

T16

1

T37

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4940

1

T2

3

T4

8

T5

4

auto[1]

537

1

T5

2

T16

1

T37

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5195

1

T2

3

T4

8

T5

6

auto[1]

282

1

T91

6

T92

18

T126

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1888	1			T2	1		T4	2		T5	1
auto[1]	714	1			T4	2		T5	2		T16	1
auto[2]	709	1			T2	1		T4	3		T16	1
auto[3]	716	1			T2	1		T5	1		T17	1
auto[4]	364	1			T5	1		T16	1		T27	2
auto[5]	345	1			T16	1		T17	1		T37	1
auto[6]	378	1			T5	1		T16	1		T27	1
auto[7]	363	1			T4	1		T48	2		T71	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1450	1			T4	1		T5	2		T16	3
clear_one[1]	714	1			T4	2		T5	2		T16	1
clear_one[2]	709	1			T2	1		T4	3		T16	1
clear_one[3]	716	1			T2	1		T5	1		T17	1
clear_none	1888	1			T2	1		T4	2		T5	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1061	1			T5	2		T18	1		T37	1
auto[StInit]	651	1			T4	1		T5	1		T16	1
auto[StCreatorRootKey]	593	1			T4	1		T18	1		T37	1
auto[StOwnerIntKey]	506	1			T4	1		T16	1		T18	1
auto[StOwnerKey]	481	1			T2	1		T4	1		T5	1
auto[StDisabled]	1876	1			T2	2		T4	4		T5	2
auto[StInvalid]	309	1			T17	5		T21	5		T74	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1061	1			T5	2		T18	1		T37	1
auto[StInit]	651	1			T4	1		T5	1		T16	1
auto[StCreatorRootKey]	593	1			T4	1		T18	1		T37	1
auto[StOwnerIntKey]	506	1			T4	1		T16	1		T18	1
auto[StOwnerKey]	481	1			T2	1		T4	1		T5	1
auto[StDisabled]	1876	1			T2	2		T4	4		T5	2
auto[StInvalid]	309	1			T17	5		T21	5		T74	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[4]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	7	1			T91	2		T126	1		T247	1
auto[0]	auto[StReset]	auto[OpGenId]	159	1			T5	1		T27	1		T214	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	195	1			T18	1		T21	1		T70	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	262	1			T37	1		T20	1		T38	1
auto[0]	auto[StInit]	auto[OpAdvance]	46	1			T91	1		T77	1		T78	1
auto[0]	auto[StInit]	auto[OpGenId]	80	1			T21	1		T82	1		T92	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	90	1			T6	1		T64	1		T72	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	176	1			T4	1		T16	1		T67	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	19	1			T77	1		T248	1		T249	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	54	1			T92	2		T72	1		T131	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	57	1			T250	1		T113	1		T77	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	70	1			T18	1		T48	1		T92	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T78	1		T145	1		T99	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T77	1		T251	5		T84	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T40	1		T126	1		T252	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T109	1		T110	1		T6	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T253	4		T254	1		T255	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	22	1			T38	1		T82	1		T28	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	27	1			T2	1		T105	1		T212	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	55	1			T109	1		T110	1		T215	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	26	1			T206	1		T55	1		T157	1
auto[0]	auto[StDisabled]	auto[OpGenId]	69	1			T27	2		T80	1		T72	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	71	1			T38	2		T105	2		T80	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T4	1		T37	2		T67	1
auto[0]	auto[StDisabled]	auto[OpDisable]	21	1			T78	1		T150	1		T98	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	14	1			T74	1		T56	1		T256	1
auto[0]	auto[StInvalid]	auto[OpGenId]	29	1			T17	1		T21	1		T44	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	22	1			T17	1		T74	1		T54	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	18	1			T257	1		T258	1		T259	2
auto[1]	auto[StReset]	auto[OpGenId]	17	1			T69	1		T260	1		T98	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	25	1			T261	1		T262	1		T263	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	42	1			T264	1		T265	1		T266	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T25	1		T267	1		T268	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T77	1		T98	1		T269	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T270	1		T147	1		T211	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	25	1			T37	1		T271	1		T272	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T77	1		T30	1		T273	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T215	1		T78	1		T262	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T55	1		T84	1		T274	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T37	1		T275	1		T276	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T277	1		T232	1		T278	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T279	1		T280	1		T231	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T113	1		T281	1		T84	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T37	1		T81	1		T82	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T282	1		T283	1		T247	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	14	1			T284	1		T285	1		T286	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T126	1		T208	1		T287	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T5	1		T81	1		T221	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	27	1			T112	1		T288	1		T289	1
auto[1]	auto[StDisabled]	auto[OpGenId]	64	1			T215	1		T290	1		T78	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T5	1		T112	1		T291	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T4	2		T16	1		T67	1
auto[1]	auto[StDisabled]	auto[OpDisable]	8	1			T128	1		T292	1		T293	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	11	1			T74	1		T53	1		T54	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T21	1		T73	1		T49	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T56	1		T53	1		T54	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T52	1		T294	1		T256	1
auto[2]	auto[StReset]	auto[OpGenId]	31	1			T38	1		T128	1		T147	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T214	1		T128	1		T112	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	61	1			T81	1		T221	1		T275	2
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T58	1		T295	1		T296	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T27	1		T266	1		T148	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T78	1		T84	1		T260	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T68	1		T8	1		T136	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T77	1		T148	1		T236	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T91	1		T114	1		T78	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T77	1		T231	1		T297	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T4	1		T109	1		T110	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T270	1		T137	1		T243	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T78	1		T298	1		T116	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T18	1		T104	1		T78	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T4	1		T68	1		T83	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T288	1		T77	1		T255	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T290	1		T299	1		T211	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T16	1		T98	1		T137	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T4	1		T67	1		T264	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	20	1			T212	1		T77	1		T300	1
auto[2]	auto[StDisabled]	auto[OpGenId]	65	1			T2	1		T144	1		T55	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T71	1		T77	1		T78	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	134	1			T37	1		T48	1		T110	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T131	1		T107	1		T138	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T301	2		T302	1		T303	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T21	1		T56	1		T256	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T130	1		T258	1		T223	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T17	1		T53	1		T73	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T304	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	24	1			T142	1		T305	1		T306	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T20	1		T104	1		T128	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	48	1			T20	1		T104	1		T221	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T211	1		T163	2		T307	1
auto[3]	auto[StInit]	auto[OpGenId]	16	1			T75	1		T78	1		T298	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	16	1			T207	1		T308	1		T78	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	19	1			T5	1		T110	1		T212	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T270	1		T232	2		T247	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T32	1		T112	1		T309	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T7	1		T78	1		T310	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T83	1		T311	1		T312	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T291	1		T289	1		T114	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T7	1		T78	1		T134	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T55	1		T117	1		T313	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T147	1		T314	1		T272	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T77	1		T211	1		T315	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	8	1			T316	1		T99	1		T137	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T114	2		T300	1		T281	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T37	1		T48	1		T265	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	20	1			T206	1		T317	1		T55	1
auto[3]	auto[StDisabled]	auto[OpGenId]	60	1			T28	1		T318	1		T291	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T126	2		T250	1		T77	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T109	1		T110	1		T68	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T2	1		T111	1		T82	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T52	2		T44	1		T319	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T17	1		T54	1		T320	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T21	1		T56	1		T44	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T21	1		T51	1		T52	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T77	1		T319	1		T321	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T52	1		T53	1		T8	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T5	1		T264	1		T322	1
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T323	1		T324	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T208	1		T305	2		T325	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	11	1			T104	1		T81	1		T214	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T27	1		T114	1		T326	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T208	1		T117	1		T269	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T76	1		T25	1		T231	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T67	1		T222	1		T327	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T326	1		T227	1		T245	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T305	1		T211	1		T202	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T16	1		T114	1		T328	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T329	1		T211	2		T330	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T298	1		T306	1		T331	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T218	1		T332	1		T243	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T298	1		T306	1		T150	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T68	1		T224	1		T72	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T298	1		T211	1		T150	1
auto[4]	auto[StDisabled]	auto[OpGenId]	29	1			T27	1		T114	5		T333	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T77	1		T211	1		T149	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	91	1			T67	1		T109	2		T224	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T134	1		T260	1		T99	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T334	1		T335	1		T336	1
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T79	1		T337	1		T338	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T258	1		T339	1		T340	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T51	1		T302	1		T341	1
auto[5]	auto[StReset]	auto[OpGenId]	4	1			T266	1		T231	1		T33	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T212	1		T342	1		T313	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	23	1			T128	1		T264	1		T265	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T191	1		T343	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T77	1		T263	1		T117	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T38	1		T344	1		T58	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T264	1		T127	1		T345	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T104	1		T346	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T347	1		T137	1		T168	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T281	1		T116	1		T236	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T348	1		T349	1		T350	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T333	1		T351	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T99	1		T352	1		T351	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T243	1		T102	1		T232	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T91	1		T275	1		T264	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T91	2		T305	1		T351	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	8	1			T104	1		T78	2		T243	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T353	1		T352	1		T138	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T305	1		T354	1		T232	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	19	1			T212	1		T164	1		T274	2
auto[5]	auto[StDisabled]	auto[OpGenId]	24	1			T211	2		T231	1		T98	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T16	1		T91	2		T207	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T37	1		T48	1		T221	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T355	1		T356	1		T232	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T17	1		T223	1		T357	1
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T56	1		T358	1		T359	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T360	1		T361	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T161	1		T319	1		T341	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T8	1		T326	1		T155	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	9	1			T261	1		T362	1		T58	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	15	1			T363	1		T349	1		T364	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T26	1		T204	1		T365	1
auto[6]	auto[StInit]	auto[OpGenId]	10	1			T40	1		T211	1		T243	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T253	2		T168	1		T366	2
auto[6]	auto[StInit]	auto[OpGenHwOut]	9	1			T349	1		T158	1		T26	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T92	1		T332	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T211	1		T367	1		T368	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T105	1		T211	1		T369	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T81	1		T265	1		T78	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T92	2		T140	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T290	1		T143	1		T211	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T105	1		T248	1		T132	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T67	1		T224	1		T221	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T92	2		T317	1		T370	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	11	1			T92	1		T318	1		T332	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T84	1		T231	1		T371	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T27	1		T83	1		T92	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T5	1		T92	4		T249	1
auto[6]	auto[StDisabled]	auto[OpGenId]	39	1			T16	1		T77	1		T78	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T92	1		T318	1		T231	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T67	1		T83	2		T224	1
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T150	1		T372	1		T373	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	6	1			T161	1		T374	1		T337	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T375	1		T376	1		T357	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T51	1		T320	2		T161	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T258	1		T319	1		T377	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T51	1		T8	1		T281	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	12	1			T270	1		T77	1		T305	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	16	1			T48	1		T68	1		T342	1
auto[7]	auto[StInit]	auto[OpAdvance]	7	1			T306	3		T378	1		T236	1
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T28	1		T379	1		T204	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	2	1			T243	1		T58	1		-	-
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T221	1		T275	1		T251	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T251	1		T137	1		T138	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T380	1		T230	1		T205	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T306	1		T159	1		T332	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T381	1		T272	1		T143	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T217	1		T255	1		T234	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T71	1		T137	1		T382	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T112	1		T142	1		T306	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T48	1		T322	1		T349	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T126	3		T383	1		T384	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	3	1			T385	1		T386	1		T204	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T7	1		T342	1		T98	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T327	1		T329	1		T78	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	13	1			T112	1		T113	1		T251	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T285	1		T211	2		T163	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T105	1		T126	1		T78	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T4	1		T80	1		T207	1
auto[7]	auto[StDisabled]	auto[OpDisable]	2	1			T150	1		T365	1		-	-
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T258	1		T337	1		T387	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T257	1		T388	1		T389	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T53	2		T390	1		T319	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T54	1		T294	1		T391	1