Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1450

1

T4

1

T5

2

T16

3

clear_one[1]

auto[0]

auto[0]

auto[0]

432

1

T4

2

T37

1

T21

1

clear_one[1]

auto[0]

auto[0]

auto[1]

128

1

T5

2

T16

1

T37

2

clear_one[1]

auto[0]

auto[1]

auto[0]

109

1

T48

2

T110

1

T81

4

clear_one[1]

auto[0]

auto[1]

auto[1]

45

1

T279

1

T77

1

T291

1

clear_one[2]

auto[0]

auto[0]

auto[0]

417

1

T2

1

T16

1

T17

1

clear_one[2]

auto[0]

auto[0]

auto[1]

122

1

T37

1

T109

1

T71

1

clear_one[2]

auto[1]

auto[0]

auto[0]

127

1

T4

3

T18

1

T67

1

clear_one[2]

auto[1]

auto[0]

auto[1]

43

1

T72

1

T266

1

T211

2

clear_one[3]

auto[0]

auto[0]

auto[0]

444

1

T2

1

T5

1

T17

1

clear_one[3]

auto[0]

auto[1]

auto[0]

109

1

T48

1

T110

1

T111

1

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T68

1

T317

1

T7

1

clear_one[3]

auto[1]

auto[1]

auto[0]

36

1

T206

1

T78

1

T117

1

clear_none

auto[0]

auto[0]

auto[0]

1380

1

T2

1

T4

1

T5

1

clear_none

auto[0]

auto[0]

auto[1]

117

1

T37

2

T109

2

T6

1

clear_none

auto[0]

auto[1]

auto[0]

138

1

T38

3

T48

1

T110

3

clear_none

auto[0]

auto[1]

auto[1]

32

1

T28

1

T306

3

T157

1

clear_none

auto[1]

auto[0]

auto[0]

131

1

T4

1

T27

2

T67

1

clear_none

auto[1]

auto[0]

auto[1]

26

1

T104

1

T92

1

T126

1

clear_none

auto[1]

auto[1]

auto[0]

40

1

T18

1

T206

1

T392

1

clear_none

auto[1]

auto[1]

auto[1]

24

1

T72

1

T78

1

T281

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1343	1			T4	1		T5	2		T16	3
clear_all	auto[1]	107	1			T91	4		T92	15		T126	3
clear_one[1]	auto[0]	671	1			T4	2		T5	2		T16	1
clear_one[1]	auto[1]	43	1			T126	1		T274	1		T333	2
clear_one[2]	auto[0]	687	1			T2	1		T4	3		T16	1
clear_one[2]	auto[1]	22	1			T116	1		T353	1		T393	6
clear_one[3]	auto[0]	686	1			T2	1		T5	1		T17	1
clear_one[3]	auto[1]	30	1			T126	1		T114	2		T298	1
clear_none	auto[0]	1808	1			T2	1		T4	2		T5	1
clear_none	auto[1]	80	1			T91	2		T92	3		T126	2