Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11322

1

T1

4

T2

13

T4

4

auto[Attestation]

8027

1

T1

4

T2

2

T4

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2815	1			T1	2		T2	5		T5	10
auto[Aes]	3520	1			T1	1		T2	1		T4	8
auto[Kmac]	3477	1			T1	4		T2	2		T5	3
auto[Otbn]	3367	1			T2	2		T5	3		T16	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7856	1			T1	8		T2	5		T3	1
auto[OpGenId]	6170	1			T1	1		T2	5		T5	14
auto[OpGenSwOut]	6205	1			T1	7		T2	8		T5	8
auto[OpGenHwOut]	6974	1			T2	2		T4	8		T5	10
auto[OpDisable]	133	1			T2	1		T111	1		T82	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10932

1

T1

8

T2

13

T3

1

auto[OpDoneFail]

16406

1

T1

8

T2

8

T4

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6758	1			T1	1		T2	4		T3	1
auto[StInit]	3751	1			T1	2		T2	3		T4	2
auto[StCreatorRootKey]	3234	1			T1	2		T2	3		T4	2
auto[StOwnerIntKey]	2906	1			T1	2		T2	3		T4	2
auto[StOwnerKey]	2472	1			T1	2		T2	5		T4	2
auto[StDisabled]	8217	1			T1	7		T2	3		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	342	1			T5	1		T18	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	107	1			T1	1		T2	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T5	1		T18	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T2	1		T165	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	77	1			T2	1		T105	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	225	1			T1	1		T5	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	308	1			T5	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	94	1			T5	1		T64	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	87	1			T2	1		T91	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T16	1		T27	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	54	1			T72	1		T76	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	210	1			T1	1		T111	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	352	1			T2	1		T5	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T6	1		T71	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	68	1			T2	1		T165	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T18	1		T6	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T16	1		T91	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	229	1			T1	1		T27	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	359	1			T19	1		T20	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	102	1			T20	1		T27	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T6	1		T207	1		T112	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T39	2		T91	1		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T2	1		T207	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	226	1			T38	1		T27	3		T105	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T72	3		T78	2		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	114	1			T128	1		T72	2		T9	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	100	1			T21	1		T85	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T104	1		T105	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T126	1		T212	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	238	1			T5	2		T6	2		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	101	1			T72	1		T76	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T18	1		T6	2		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	84	1			T214	1		T28	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	79	1			T18	1		T6	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T215	1		T216	1		T217	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	245	1			T27	2		T104	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	87	1			T21	1		T77	2		T78	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	94	1			T18	1		T214	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T18	1		T80	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T1	1		T18	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	69	1			T1	1		T91	1		T215	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	229	1			T1	1		T16	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	104	1			T21	1		T76	2		T77	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	96	1			T2	1		T6	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	73	1			T16	1		T214	1		T219	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T108	1		T72	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T206	1		T43	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	225	1			T104	1		T91	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	247	1			T2	1		T5	3		T20	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T104	1		T82	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	64	1			T64	1		T220	1		T131	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	65	1			T19	1		T38	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T2	1		T82	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	186	1			T5	1		T27	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	563	1			T19	1		T20	2		T38	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T4	1		T92	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	123	1			T21	1		T220	2		T221	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	102	1			T18	1		T92	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	70	1			T43	1		T222	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	293	1			T4	3		T27	1		T67	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	439	1			T19	2		T20	1		T48	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T111	1		T165	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T18	1		T38	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	113	1			T48	1		T81	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T110	1		T71	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	304	1			T48	1		T110	2		T81	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	395	1			T37	3		T20	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T109	1		T39	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T6	1		T83	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T37	1		T6	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T37	1		T109	1		T165	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	282	1			T16	1		T37	2		T109	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T21	1		T75	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	90	1			T16	1		T111	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T39	1		T91	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	81	1			T6	1		T85	1		T214	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	45	1			T5	1		T27	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	170	1			T27	1		T80	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	58	1			T72	1		T78	5		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	118	1			T18	1		T67	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	128	1			T4	1		T18	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	106	1			T4	1		T18	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T4	1		T67	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	259	1			T4	1		T67	1		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	69	1			T77	1		T78	4		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T5	1		T48	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T18	1		T110	1		T111	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T18	1		T110	1		T104	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T27	1		T48	1		T165	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	286	1			T5	1		T48	3		T110	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	69	1			T21	1		T77	3		T78	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	111	1			T5	1		T37	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T5	2		T37	1		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T109	1		T165	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T165	1		T71	1		T224	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	289	1			T37	2		T104	1		T83	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	209	1			T2	2		T5	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	688	1			T1	2		T2	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	204	1			T2	1		T16	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	621	1			T1	1		T5	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	199	1			T2	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	711	1			T1	1		T2	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	212	1			T2	1		T6	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	702	1			T19	1		T20	3		T38	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	227	1			T104	1		T105	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	449	1			T5	2		T21	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	214	1			T18	1		T6	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	480	1			T18	1		T27	2		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	223	1			T1	2		T18	2		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	429	1			T1	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T16	1		T108	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	441	1			T2	1		T21	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	173	1			T2	1		T19	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	547	1			T2	1		T5	4		T20	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	286	1			T18	1		T92	1		T220	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	971	1			T4	4		T19	1		T20	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	288	1			T18	1		T38	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	873	1			T19	2		T20	1		T48	6
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	251	1			T37	2		T109	1		T165	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	808	1			T16	1		T37	5		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	188	1			T27	1		T6	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	334	1			T5	1		T16	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	289	1			T4	3		T18	2		T67	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	455	1			T4	1		T18	1		T67	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T18	2		T27	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	476	1			T5	2		T48	4		T110	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T5	1		T37	1		T109	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	490	1			T5	2		T37	3		T27	1