Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33606

1

T1

20

T2

23

T3

1

auto[1]

261

1

T91

7

T92

13

T112

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33615	1			T1	20		T2	23		T3	1
auto[134217728:268435455]	12	1			T112	3		T126	1		T114	1
auto[268435456:402653183]	4	1			T251	1		T274	2		T417	1
auto[402653184:536870911]	12	1			T91	1		T92	1		T126	1
auto[536870912:671088639]	7	1			T91	1		T92	1		T116	1
auto[671088640:805306367]	7	1			T91	1		T92	1		T163	1
auto[805306368:939524095]	8	1			T91	1		T114	1		T116	1
auto[939524096:1073741823]	10	1			T92	1		T114	1		T298	1
auto[1073741824:1207959551]	10	1			T112	1		T326	1		T306	2
auto[1207959552:1342177279]	14	1			T112	1		T126	1		T114	1
auto[1342177280:1476395007]	4	1			T418	1		T419	1		T420	1
auto[1476395008:1610612735]	7	1			T112	1		T326	1		T305	1
auto[1610612736:1744830463]	11	1			T92	1		T305	1		T401	1
auto[1744830464:1879048191]	7	1			T163	1		T393	1		T267	1
auto[1879048192:2013265919]	5	1			T421	1		T422	1		T423	2
auto[2013265920:2147483647]	11	1			T112	2		T163	1		T117	1
auto[2147483648:2281701375]	9	1			T92	1		T114	1		T163	1
auto[2281701376:2415919103]	10	1			T251	1		T116	1		T401	1
auto[2415919104:2550136831]	12	1			T91	1		T92	1		T114	1
auto[2550136832:2684354559]	4	1			T92	1		T393	1		T424	1
auto[2684354560:2818572287]	5	1			T401	1		T282	1		T393	1
auto[2818572288:2952790015]	10	1			T92	1		T251	1		T277	1
auto[2952790016:3087007743]	7	1			T112	1		T114	1		T117	1
auto[3087007744:3221225471]	6	1			T112	1		T306	1		T425	1
auto[3221225472:3355443199]	10	1			T92	1		T112	2		T298	1
auto[3355443200:3489660927]	11	1			T92	1		T116	1		T253	1
auto[3489660928:3623878655]	6	1			T306	1		T304	1		T419	1
auto[3623878656:3758096383]	8	1			T92	1		T253	1		T353	1
auto[3758096384:3892314111]	6	1			T91	1		T333	1		T253	1
auto[3892314112:4026531839]	1	1			T426	1		-	-		-	-
auto[4026531840:4160749567]	11	1			T91	1		T92	1		T112	1
auto[4160749568:4294967295]	7	1			T126	1		T306	1		T333	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33606	1			T1	20		T2	23		T3	1
auto[0:134217727]	auto[1]	9	1			T306	1		T333	1		T393	1
auto[134217728:268435455]	auto[1]	12	1			T112	3		T126	1		T114	1
auto[268435456:402653183]	auto[1]	4	1			T251	1		T274	2		T417	1
auto[402653184:536870911]	auto[1]	12	1			T91	1		T92	1		T126	1
auto[536870912:671088639]	auto[1]	7	1			T91	1		T92	1		T116	1
auto[671088640:805306367]	auto[1]	7	1			T91	1		T92	1		T163	1
auto[805306368:939524095]	auto[1]	8	1			T91	1		T114	1		T116	1
auto[939524096:1073741823]	auto[1]	10	1			T92	1		T114	1		T298	1
auto[1073741824:1207959551]	auto[1]	10	1			T112	1		T326	1		T306	2
auto[1207959552:1342177279]	auto[1]	14	1			T112	1		T126	1		T114	1
auto[1342177280:1476395007]	auto[1]	4	1			T418	1		T419	1		T420	1
auto[1476395008:1610612735]	auto[1]	7	1			T112	1		T326	1		T305	1
auto[1610612736:1744830463]	auto[1]	11	1			T92	1		T305	1		T401	1
auto[1744830464:1879048191]	auto[1]	7	1			T163	1		T393	1		T267	1
auto[1879048192:2013265919]	auto[1]	5	1			T421	1		T422	1		T423	2
auto[2013265920:2147483647]	auto[1]	11	1			T112	2		T163	1		T117	1
auto[2147483648:2281701375]	auto[1]	9	1			T92	1		T114	1		T163	1
auto[2281701376:2415919103]	auto[1]	10	1			T251	1		T116	1		T401	1
auto[2415919104:2550136831]	auto[1]	12	1			T91	1		T92	1		T114	1
auto[2550136832:2684354559]	auto[1]	4	1			T92	1		T393	1		T424	1
auto[2684354560:2818572287]	auto[1]	5	1			T401	1		T282	1		T393	1
auto[2818572288:2952790015]	auto[1]	10	1			T92	1		T251	1		T277	1
auto[2952790016:3087007743]	auto[1]	7	1			T112	1		T114	1		T117	1
auto[3087007744:3221225471]	auto[1]	6	1			T112	1		T306	1		T425	1
auto[3221225472:3355443199]	auto[1]	10	1			T92	1		T112	2		T298	1
auto[3355443200:3489660927]	auto[1]	11	1			T92	1		T116	1		T253	1
auto[3489660928:3623878655]	auto[1]	6	1			T306	1		T304	1		T419	1
auto[3623878656:3758096383]	auto[1]	8	1			T92	1		T253	1		T353	1
auto[3758096384:3892314111]	auto[1]	6	1			T91	1		T333	1		T253	1
auto[3892314112:4026531839]	auto[1]	1	1			T426	1		-	-		-	-
auto[4026531840:4160749567]	auto[1]	11	1			T91	1		T92	1		T112	1
auto[4160749568:4294967295]	auto[1]	7	1			T126	1		T306	1		T333	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1669

1

T3

4

T18

1

T20

3

auto[1]

1774

1

T2

3

T3

1

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T3	1		T104	1		T51	1
auto[134217728:268435455]	113	1			T5	1		T111	1		T74	1
auto[268435456:402653183]	105	1			T2	1		T21	1		T111	1
auto[402653184:536870911]	110	1			T3	1		T71	1		T215	1
auto[536870912:671088639]	100	1			T74	1		T53	1		T212	1
auto[671088640:805306367]	114	1			T6	1		T64	1		T72	1
auto[805306368:939524095]	106	1			T21	1		T51	1		T54	1
auto[939524096:1073741823]	104	1			T74	1		T206	1		T317	2
auto[1073741824:1207959551]	108	1			T27	1		T74	1		T104	1
auto[1207959552:1342177279]	101	1			T2	1		T18	1		T20	1
auto[1342177280:1476395007]	113	1			T165	1		T70	1		T71	1
auto[1476395008:1610612735]	99	1			T71	1		T128	1		T72	1
auto[1610612736:1744830463]	114	1			T21	1		T111	1		T82	1
auto[1744830464:1879048191]	123	1			T3	1		T70	1		T56	1
auto[1879048192:2013265919]	116	1			T2	1		T5	1		T27	1
auto[2013265920:2147483647]	99	1			T165	1		T28	1		T112	1
auto[2147483648:2281701375]	110	1			T111	1		T70	1		T71	1
auto[2281701376:2415919103]	102	1			T21	1		T56	1		T91	1
auto[2415919104:2550136831]	120	1			T82	1		T64	1		T28	1
auto[2550136832:2684354559]	108	1			T5	1		T20	2		T51	1
auto[2684354560:2818572287]	114	1			T21	1		T71	1		T214	1
auto[2818572288:2952790015]	108	1			T20	1		T104	1		T214	1
auto[2952790016:3087007743]	97	1			T165	1		T70	1		T126	1
auto[3087007744:3221225471]	92	1			T91	2		T64	1		T52	1
auto[3221225472:3355443199]	121	1			T27	1		T51	2		T128	1
auto[3355443200:3489660927]	97	1			T21	1		T104	1		T51	1
auto[3489660928:3623878655]	90	1			T6	1		T317	1		T131	1
auto[3623878656:3758096383]	104	1			T3	1		T56	1		T135	1
auto[3758096384:3892314111]	109	1			T17	1		T27	1		T21	1
auto[3892314112:4026531839]	115	1			T17	1		T21	1		T70	1
auto[4026531840:4160749567]	111	1			T74	1		T32	1		T112	1
auto[4160749568:4294967295]	101	1			T3	1		T21	1		T212	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T3	1		T51	1		T92	1
auto[0:134217727]	auto[1]	62	1			T104	1		T112	1		T279	1
auto[134217728:268435455]	auto[0]	56	1			T74	1		T82	1		T144	1
auto[134217728:268435455]	auto[1]	57	1			T5	1		T111	1		T206	1
auto[268435456:402653183]	auto[0]	58	1			T21	1		T111	1		T70	1
auto[268435456:402653183]	auto[1]	47	1			T2	1		T214	1		T77	1
auto[402653184:536870911]	auto[0]	58	1			T208	1		T289	1		T35	1
auto[402653184:536870911]	auto[1]	52	1			T3	1		T71	1		T215	1
auto[536870912:671088639]	auto[0]	53	1			T74	1		T53	1		T76	1
auto[536870912:671088639]	auto[1]	47	1			T212	1		T55	1		T217	1
auto[671088640:805306367]	auto[0]	51	1			T6	1		T136	1		T258	1
auto[671088640:805306367]	auto[1]	63	1			T64	1		T72	1		T7	1
auto[805306368:939524095]	auto[0]	57	1			T21	1		T51	1		T54	1
auto[805306368:939524095]	auto[1]	49	1			T72	1		T392	1		T291	1
auto[939524096:1073741823]	auto[0]	47	1			T74	1		T317	1		T215	1
auto[939524096:1073741823]	auto[1]	57	1			T206	1		T317	1		T215	1
auto[1073741824:1207959551]	auto[0]	50	1			T74	1		T54	1		T218	1
auto[1073741824:1207959551]	auto[1]	58	1			T27	1		T104	1		T288	1
auto[1207959552:1342177279]	auto[0]	41	1			T18	1		T20	1		T70	1
auto[1207959552:1342177279]	auto[1]	60	1			T2	1		T92	1		T206	1
auto[1342177280:1476395007]	auto[0]	53	1			T70	1		T71	1		T214	1
auto[1342177280:1476395007]	auto[1]	60	1			T165	1		T136	1		T288	1
auto[1476395008:1610612735]	auto[0]	46	1			T71	1		T128	1		T136	1
auto[1476395008:1610612735]	auto[1]	53	1			T72	1		T257	1		T248	1
auto[1610612736:1744830463]	auto[0]	57	1			T111	1		T53	1		T92	1
auto[1610612736:1744830463]	auto[1]	57	1			T21	1		T82	1		T72	1
auto[1744830464:1879048191]	auto[0]	61	1			T3	1		T28	1		T130	1
auto[1744830464:1879048191]	auto[1]	62	1			T70	1		T56	1		T72	1
auto[1879048192:2013265919]	auto[0]	56	1			T135	1		T78	1		T133	1
auto[1879048192:2013265919]	auto[1]	60	1			T2	1		T5	1		T27	1
auto[2013265920:2147483647]	auto[0]	47	1			T130	1		T215	1		T8	1
auto[2013265920:2147483647]	auto[1]	52	1			T165	1		T28	1		T112	1
auto[2147483648:2281701375]	auto[0]	51	1			T111	1		T52	1		T53	1
auto[2147483648:2281701375]	auto[1]	59	1			T70	1		T71	1		T104	1
auto[2281701376:2415919103]	auto[0]	44	1			T56	1		T91	1		T136	1
auto[2281701376:2415919103]	auto[1]	58	1			T21	1		T72	1		T392	1
auto[2415919104:2550136831]	auto[0]	54	1			T128	1		T212	1		T77	1
auto[2415919104:2550136831]	auto[1]	66	1			T82	1		T64	1		T28	1
auto[2550136832:2684354559]	auto[0]	44	1			T20	2		T44	1		T280	1
auto[2550136832:2684354559]	auto[1]	64	1			T5	1		T51	1		T52	1
auto[2684354560:2818572287]	auto[0]	61	1			T21	1		T214	1		T92	1
auto[2684354560:2818572287]	auto[1]	53	1			T71	1		T317	1		T73	1
auto[2818572288:2952790015]	auto[0]	54	1			T214	1		T53	1		T220	1
auto[2818572288:2952790015]	auto[1]	54	1			T20	1		T104	1		T257	1
auto[2952790016:3087007743]	auto[0]	43	1			T70	1		T257	1		T258	1
auto[2952790016:3087007743]	auto[1]	54	1			T165	1		T126	1		T212	1
auto[3087007744:3221225471]	auto[0]	48	1			T91	2		T64	1		T52	1
auto[3087007744:3221225471]	auto[1]	44	1			T77	1		T78	1		T350	1
auto[3221225472:3355443199]	auto[0]	58	1			T51	1		T128	1		T112	1
auto[3221225472:3355443199]	auto[1]	63	1			T27	1		T51	1		T77	3
auto[3355443200:3489660927]	auto[0]	44	1			T54	1		T8	1		T75	1
auto[3355443200:3489660927]	auto[1]	53	1			T21	1		T104	1		T51	1
auto[3489660928:3623878655]	auto[0]	40	1			T317	1		T131	1		T308	1
auto[3489660928:3623878655]	auto[1]	50	1			T6	1		T212	1		T288	1
auto[3623878656:3758096383]	auto[0]	55	1			T3	1		T56	1		T135	1
auto[3623878656:3758096383]	auto[1]	49	1			T279	1		T78	1		T298	1
auto[3758096384:3892314111]	auto[0]	58	1			T44	1		T113	1		T77	1
auto[3758096384:3892314111]	auto[1]	51	1			T17	1		T27	1		T21	1
auto[3892314112:4026531839]	auto[0]	68	1			T21	1		T70	1		T51	1
auto[3892314112:4026531839]	auto[1]	47	1			T17	1		T299	1		T211	1
auto[4026531840:4160749567]	auto[0]	51	1			T32	1		T112	1		T55	1
auto[4026531840:4160749567]	auto[1]	60	1			T74	1		T7	1		T131	1
auto[4160749568:4294967295]	auto[0]	48	1			T3	1		T21	1		T208	1
auto[4160749568:4294967295]	auto[1]	53	1			T212	1		T288	1		T217	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1682

1

T3

4

T18

1

T20

3

auto[1]

1761

1

T2

3

T3

1

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T2	1		T27	1		T21	1
auto[134217728:268435455]	95	1			T21	1		T70	1		T71	1
auto[268435456:402653183]	77	1			T215	1		T44	1		T75	1
auto[402653184:536870911]	107	1			T21	1		T74	1		T206	1
auto[536870912:671088639]	125	1			T5	1		T6	1		T51	1
auto[671088640:805306367]	104	1			T74	1		T70	1		T53	1
auto[805306368:939524095]	102	1			T21	1		T214	1		T40	1
auto[939524096:1073741823]	94	1			T51	1		T220	1		T7	2
auto[1073741824:1207959551]	106	1			T3	1		T17	1		T18	1
auto[1207959552:1342177279]	115	1			T21	1		T51	1		T92	1
auto[1342177280:1476395007]	109	1			T2	1		T165	1		T104	1
auto[1476395008:1610612735]	118	1			T104	1		T53	1		T112	1
auto[1610612736:1744830463]	119	1			T70	1		T6	1		T53	1
auto[1744830464:1879048191]	118	1			T165	2		T82	1		T51	1
auto[1879048192:2013265919]	114	1			T27	1		T111	1		T82	1
auto[2013265920:2147483647]	112	1			T3	1		T21	2		T111	1
auto[2147483648:2281701375]	109	1			T3	1		T111	1		T28	1
auto[2281701376:2415919103]	104	1			T28	1		T130	1		T72	1
auto[2415919104:2550136831]	107	1			T21	1		T70	1		T215	1
auto[2550136832:2684354559]	109	1			T17	1		T111	1		T56	1
auto[2684354560:2818572287]	117	1			T74	1		T71	1		T32	1
auto[2818572288:2952790015]	113	1			T20	1		T27	1		T70	1
auto[2952790016:3087007743]	117	1			T2	1		T74	1		T70	1
auto[3087007744:3221225471]	104	1			T20	1		T53	1		T92	1
auto[3221225472:3355443199]	118	1			T5	1		T56	1		T317	1
auto[3355443200:3489660927]	112	1			T20	1		T21	1		T64	1
auto[3489660928:3623878655]	104	1			T3	1		T5	1		T74	1
auto[3623878656:3758096383]	104	1			T20	1		T104	1		T72	1
auto[3758096384:3892314111]	111	1			T27	1		T71	1		T32	1
auto[3892314112:4026531839]	97	1			T21	1		T51	1		T214	1
auto[4026531840:4160749567]	116	1			T3	1		T71	1		T91	1
auto[4160749568:4294967295]	92	1			T70	1		T71	1		T104	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T91	1		T112	1		T54	1
auto[0:134217727]	auto[1]	55	1			T2	1		T27	1		T21	1
auto[134217728:268435455]	auto[0]	59	1			T70	1		T71	1		T8	1
auto[134217728:268435455]	auto[1]	36	1			T21	1		T51	1		T317	1
auto[268435456:402653183]	auto[0]	34	1			T44	1		T75	1		T294	1
auto[268435456:402653183]	auto[1]	43	1			T215	1		T217	1		T115	1
auto[402653184:536870911]	auto[0]	48	1			T74	1		T392	1		T9	1
auto[402653184:536870911]	auto[1]	59	1			T21	1		T206	1		T112	1
auto[536870912:671088639]	auto[0]	64	1			T6	1		T53	1		T8	1
auto[536870912:671088639]	auto[1]	61	1			T5	1		T51	1		T206	1
auto[671088640:805306367]	auto[0]	46	1			T74	1		T70	1		T53	1
auto[671088640:805306367]	auto[1]	58	1			T212	1		T257	1		T288	1
auto[805306368:939524095]	auto[0]	52	1			T214	1		T40	1		T208	1
auto[805306368:939524095]	auto[1]	50	1			T21	1		T392	1		T78	1
auto[939524096:1073741823]	auto[0]	47	1			T220	1		T75	1		T256	1
auto[939524096:1073741823]	auto[1]	47	1			T51	1		T7	2		T77	2
auto[1073741824:1207959551]	auto[0]	54	1			T3	1		T18	1		T52	1
auto[1073741824:1207959551]	auto[1]	52	1			T17	1		T270	1		T76	1
auto[1207959552:1342177279]	auto[0]	55	1			T21	1		T51	1		T92	1
auto[1207959552:1342177279]	auto[1]	60	1			T40	1		T72	1		T55	1
auto[1342177280:1476395007]	auto[0]	43	1			T392	1		T78	2		T223	1
auto[1342177280:1476395007]	auto[1]	66	1			T2	1		T165	1		T104	1
auto[1476395008:1610612735]	auto[0]	52	1			T112	1		T130	1		T135	1
auto[1476395008:1610612735]	auto[1]	66	1			T104	1		T53	1		T78	2
auto[1610612736:1744830463]	auto[0]	57	1			T70	1		T53	1		T212	1
auto[1610612736:1744830463]	auto[1]	62	1			T6	1		T54	1		T72	1
auto[1744830464:1879048191]	auto[0]	56	1			T136	1		T78	2		T326	1
auto[1744830464:1879048191]	auto[1]	62	1			T165	2		T82	1		T51	1
auto[1879048192:2013265919]	auto[0]	49	1			T111	1		T54	1		T35	1
auto[1879048192:2013265919]	auto[1]	65	1			T27	1		T82	1		T72	1
auto[2013265920:2147483647]	auto[0]	58	1			T21	1		T214	1		T136	1
auto[2013265920:2147483647]	auto[1]	54	1			T3	1		T21	1		T111	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	1		T111	1		T258	1
auto[2147483648:2281701375]	auto[1]	56	1			T28	1		T126	1		T75	1
auto[2281701376:2415919103]	auto[0]	53	1			T130	1		T136	1		T77	1
auto[2281701376:2415919103]	auto[1]	51	1			T28	1		T72	1		T288	1
auto[2415919104:2550136831]	auto[0]	56	1			T215	1		T135	1		T44	1
auto[2415919104:2550136831]	auto[1]	51	1			T21	1		T70	1		T257	1
auto[2550136832:2684354559]	auto[0]	60	1			T111	1		T56	1		T215	1
auto[2550136832:2684354559]	auto[1]	49	1			T17	1		T220	1		T392	1
auto[2684354560:2818572287]	auto[0]	55	1			T74	1		T52	1		T215	1
auto[2684354560:2818572287]	auto[1]	62	1			T71	1		T32	1		T72	1
auto[2818572288:2952790015]	auto[0]	58	1			T70	1		T92	1		T8	1
auto[2818572288:2952790015]	auto[1]	55	1			T20	1		T27	1		T28	1
auto[2952790016:3087007743]	auto[0]	68	1			T74	1		T6	1		T136	1
auto[2952790016:3087007743]	auto[1]	49	1			T2	1		T70	1		T104	1
auto[3087007744:3221225471]	auto[0]	55	1			T20	1		T53	1		T92	1
auto[3087007744:3221225471]	auto[1]	49	1			T73	1		T77	1		T318	1
auto[3221225472:3355443199]	auto[0]	58	1			T56	1		T317	1		T73	1
auto[3221225472:3355443199]	auto[1]	60	1			T5	1		T7	1		T77	2
auto[3355443200:3489660927]	auto[0]	57	1			T20	1		T64	1		T257	1
auto[3355443200:3489660927]	auto[1]	55	1			T21	1		T214	1		T215	1
auto[3489660928:3623878655]	auto[0]	46	1			T3	1		T91	1		T131	1
auto[3489660928:3623878655]	auto[1]	58	1			T5	1		T74	1		T56	1
auto[3623878656:3758096383]	auto[0]	48	1			T20	1		T8	1		T218	1
auto[3623878656:3758096383]	auto[1]	56	1			T104	1		T72	1		T7	1
auto[3758096384:3892314111]	auto[0]	49	1			T32	1		T52	1		T144	1
auto[3758096384:3892314111]	auto[1]	62	1			T27	1		T71	1		T216	1
auto[3892314112:4026531839]	auto[0]	43	1			T21	1		T51	1		T214	1
auto[3892314112:4026531839]	auto[1]	54	1			T112	1		T392	1		T270	1
auto[4026531840:4160749567]	auto[0]	57	1			T3	1		T91	1		T82	1
auto[4026531840:4160749567]	auto[1]	59	1			T71	1		T72	1		T55	1
auto[4160749568:4294967295]	auto[0]	53	1			T70	1		T51	1		T112	1
auto[4160749568:4294967295]	auto[1]	39	1			T71	1		T104	1		T317	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1673

1

T2

1

T3

4

T20

3

auto[1]

1770

1

T2

2

T3

1

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T3	2		T74	1		T70	1
auto[134217728:268435455]	115	1			T20	1		T53	1		T130	1
auto[268435456:402653183]	119	1			T20	1		T21	4		T111	1
auto[402653184:536870911]	106	1			T165	1		T71	1		T215	2
auto[536870912:671088639]	98	1			T5	1		T111	1		T92	1
auto[671088640:805306367]	122	1			T104	1		T52	1		T128	1
auto[805306368:939524095]	113	1			T2	1		T92	1		T206	1
auto[939524096:1073741823]	86	1			T70	1		T82	1		T64	1
auto[1073741824:1207959551]	110	1			T71	1		T214	1		T92	1
auto[1207959552:1342177279]	103	1			T21	2		T214	1		T28	1
auto[1342177280:1476395007]	116	1			T5	1		T71	1		T112	1
auto[1476395008:1610612735]	114	1			T56	1		T135	1		T113	1
auto[1610612736:1744830463]	108	1			T21	1		T111	1		T91	1
auto[1744830464:1879048191]	100	1			T21	1		T74	1		T70	1
auto[1879048192:2013265919]	107	1			T2	1		T111	1		T104	1
auto[2013265920:2147483647]	94	1			T17	1		T18	1		T51	1
auto[2147483648:2281701375]	115	1			T74	1		T214	1		T257	1
auto[2281701376:2415919103]	91	1			T20	1		T52	1		T130	1
auto[2415919104:2550136831]	104	1			T3	1		T72	1		T44	1
auto[2550136832:2684354559]	117	1			T165	1		T51	1		T72	1
auto[2684354560:2818572287]	118	1			T27	1		T28	1		T54	1
auto[2818572288:2952790015]	117	1			T91	1		T53	2		T112	1
auto[2952790016:3087007743]	97	1			T2	1		T71	1		T53	1
auto[3087007744:3221225471]	119	1			T27	1		T70	1		T104	1
auto[3221225472:3355443199]	96	1			T6	1		T56	1		T135	1
auto[3355443200:3489660927]	103	1			T3	1		T21	1		T70	2
auto[3489660928:3623878655]	112	1			T27	2		T21	1		T70	1
auto[3623878656:3758096383]	111	1			T6	1		T214	1		T54	1
auto[3758096384:3892314111]	94	1			T5	1		T17	1		T74	1
auto[3892314112:4026531839]	114	1			T74	1		T51	1		T128	1
auto[4026531840:4160749567]	103	1			T3	1		T91	1		T51	1
auto[4160749568:4294967295]	108	1			T20	1		T206	1		T128	1