Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4748

1

T2

4

T3

6

T5

6

auto[1]

2138

1

T2

2

T3

4

T17

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	246	1			T2	2		T3	2		T21	2
auto[134217728:268435455]	178	1			T51	2		T52	2		T28	2
auto[268435456:402653183]	240	1			T71	2		T91	2		T51	2
auto[402653184:536870911]	176	1			T27	2		T165	2		T128	2
auto[536870912:671088639]	228	1			T3	2		T32	2		T392	2
auto[671088640:805306367]	240	1			T104	2		T82	2		T214	2
auto[805306368:939524095]	206	1			T70	2		T214	2		T279	2
auto[939524096:1073741823]	202	1			T165	2		T104	2		T92	2
auto[1073741824:1207959551]	176	1			T92	2		T206	2		T72	2
auto[1207959552:1342177279]	184	1			T2	4		T5	2		T104	2
auto[1342177280:1476395007]	226	1			T27	2		T70	2		T392	2
auto[1476395008:1610612735]	208	1			T3	2		T18	2		T21	2
auto[1610612736:1744830463]	228	1			T21	2		T165	2		T104	2
auto[1744830464:1879048191]	230	1			T74	2		T51	2		T206	2
auto[1879048192:2013265919]	228	1			T3	2		T5	4		T21	2
auto[2013265920:2147483647]	212	1			T3	2		T17	2		T27	2
auto[2147483648:2281701375]	204	1			T21	2		T6	2		T52	2
auto[2281701376:2415919103]	226	1			T20	2		T21	2		T56	2
auto[2415919104:2550136831]	230	1			T27	2		T74	2		T6	2
auto[2550136832:2684354559]	226	1			T21	2		T56	2		T71	2
auto[2684354560:2818572287]	224	1			T111	6		T74	2		T64	2
auto[2818572288:2952790015]	226	1			T6	2		T54	2		T72	2
auto[2952790016:3087007743]	204	1			T82	2		T51	2		T206	2
auto[3087007744:3221225471]	210	1			T17	2		T74	2		T70	2
auto[3221225472:3355443199]	218	1			T104	2		T91	2		T214	2
auto[3355443200:3489660927]	202	1			T21	2		T70	2		T52	2
auto[3489660928:3623878655]	252	1			T74	2		T28	2		T54	2
auto[3623878656:3758096383]	228	1			T70	2		T71	2		T51	2
auto[3758096384:3892314111]	212	1			T71	2		T51	2		T215	2
auto[3892314112:4026531839]	192	1			T20	2		T64	2		T215	2
auto[4026531840:4160749567]	232	1			T21	2		T53	2		T92	2
auto[4160749568:4294967295]	192	1			T20	4		T21	2		T112	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	164	1			T2	2		T21	2		T82	2
auto[0:134217727]	auto[1]	82	1			T3	2		T72	2		T76	2
auto[134217728:268435455]	auto[0]	126	1			T51	2		T52	2		T28	2
auto[134217728:268435455]	auto[1]	52	1			T76	2		T113	2		T149	2
auto[268435456:402653183]	auto[0]	154	1			T71	2		T91	2		T206	2
auto[268435456:402653183]	auto[1]	86	1			T51	2		T220	2		T77	2
auto[402653184:536870911]	auto[0]	122	1			T27	2		T165	2		T128	2
auto[402653184:536870911]	auto[1]	54	1			T112	2		T140	2		T251	2
auto[536870912:671088639]	auto[0]	166	1			T3	2		T32	2		T392	2
auto[536870912:671088639]	auto[1]	62	1			T144	2		T217	4		T299	4
auto[671088640:805306367]	auto[0]	184	1			T104	2		T214	2		T72	2
auto[671088640:805306367]	auto[1]	56	1			T82	2		T28	2		T300	2
auto[805306368:939524095]	auto[0]	162	1			T214	2		T279	2		T136	2
auto[805306368:939524095]	auto[1]	44	1			T70	2		T248	2		T243	2
auto[939524096:1073741823]	auto[0]	134	1			T165	2		T104	2		T72	2
auto[939524096:1073741823]	auto[1]	68	1			T92	2		T258	2		T270	2
auto[1073741824:1207959551]	auto[0]	126	1			T92	2		T72	2		T7	2
auto[1073741824:1207959551]	auto[1]	50	1			T206	2		T308	2		T300	2
auto[1207959552:1342177279]	auto[0]	108	1			T2	2		T5	2		T104	2
auto[1207959552:1342177279]	auto[1]	76	1			T2	2		T91	2		T215	2
auto[1342177280:1476395007]	auto[0]	164	1			T27	2		T70	2		T392	2
auto[1342177280:1476395007]	auto[1]	62	1			T140	2		T231	2		T297	2
auto[1476395008:1610612735]	auto[0]	152	1			T21	2		T70	2		T71	2
auto[1476395008:1610612735]	auto[1]	56	1			T3	2		T18	2		T257	2
auto[1610612736:1744830463]	auto[0]	174	1			T21	2		T165	2		T104	2
auto[1610612736:1744830463]	auto[1]	54	1			T342	2		T116	2		T99	2
auto[1744830464:1879048191]	auto[0]	138	1			T51	2		T112	2		T317	2
auto[1744830464:1879048191]	auto[1]	92	1			T74	2		T206	2		T223	2
auto[1879048192:2013265919]	auto[0]	160	1			T3	2		T5	4		T21	2
auto[1879048192:2013265919]	auto[1]	68	1			T111	2		T56	2		T64	2
auto[2013265920:2147483647]	auto[0]	128	1			T3	2		T214	2		T77	2
auto[2013265920:2147483647]	auto[1]	84	1			T17	2		T27	2		T70	2
auto[2147483648:2281701375]	auto[0]	150	1			T21	2		T6	2		T52	2
auto[2147483648:2281701375]	auto[1]	54	1			T8	2		T44	2		T76	2
auto[2281701376:2415919103]	auto[0]	154	1			T21	2		T56	2		T317	2
auto[2281701376:2415919103]	auto[1]	72	1			T20	2		T54	2		T258	2
auto[2415919104:2550136831]	auto[0]	146	1			T6	2		T215	2		T136	2
auto[2415919104:2550136831]	auto[1]	84	1			T27	2		T74	2		T218	2
auto[2550136832:2684354559]	auto[0]	160	1			T21	2		T56	2		T53	4
auto[2550136832:2684354559]	auto[1]	66	1			T71	2		T279	2		T10	2
auto[2684354560:2818572287]	auto[0]	152	1			T111	2		T74	2		T64	2
auto[2684354560:2818572287]	auto[1]	72	1			T111	4		T40	2		T72	2
auto[2818572288:2952790015]	auto[0]	152	1			T54	2		T72	2		T212	2
auto[2818572288:2952790015]	auto[1]	74	1			T6	2		T44	2		T77	2
auto[2952790016:3087007743]	auto[0]	144	1			T51	2		T206	2		T220	2
auto[2952790016:3087007743]	auto[1]	60	1			T82	2		T318	2		T294	2
auto[3087007744:3221225471]	auto[0]	140	1			T70	2		T72	2		T76	2
auto[3087007744:3221225471]	auto[1]	70	1			T17	2		T74	2		T75	2
auto[3221225472:3355443199]	auto[0]	150	1			T104	2		T91	2		T214	2
auto[3221225472:3355443199]	auto[1]	68	1			T72	2		T135	2		T257	2
auto[3355443200:3489660927]	auto[0]	146	1			T21	2		T70	2		T7	2
auto[3355443200:3489660927]	auto[1]	56	1			T52	2		T259	2		T431	2
auto[3489660928:3623878655]	auto[0]	188	1			T74	2		T28	2		T54	2
auto[3489660928:3623878655]	auto[1]	64	1			T216	2		T78	2		T320	2
auto[3623878656:3758096383]	auto[0]	164	1			T70	2		T71	2		T317	2
auto[3623878656:3758096383]	auto[1]	64	1			T51	2		T9	2		T257	2
auto[3758096384:3892314111]	auto[0]	136	1			T71	2		T136	2		T216	2
auto[3758096384:3892314111]	auto[1]	76	1			T51	2		T215	2		T350	2
auto[3892314112:4026531839]	auto[0]	118	1			T215	2		T77	2		T291	2
auto[3892314112:4026531839]	auto[1]	74	1			T20	2		T64	2		T257	2
auto[4026531840:4160749567]	auto[0]	164	1			T21	2		T53	2		T92	2
auto[4026531840:4160749567]	auto[1]	68	1			T7	2		T218	2		T84	4
auto[4160749568:4294967295]	auto[0]	122	1			T21	2		T112	4		T72	2
auto[4160749568:4294967295]	auto[1]	70	1			T20	4		T318	2		T35	2