Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2945

1

T2

3

T5

3

T17

2

auto[1]

245

1

T91

4

T92

10

T112

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T27	1		T21	1		T220	1
auto[134217728:268435455]	105	1			T91	1		T112	1		T215	1
auto[268435456:402653183]	101	1			T21	1		T74	1		T104	1
auto[402653184:536870911]	100	1			T56	1		T28	1		T112	1
auto[536870912:671088639]	100	1			T2	1		T6	1		T206	1
auto[671088640:805306367]	84	1			T5	1		T257	1		T44	1
auto[805306368:939524095]	101	1			T6	1		T214	1		T92	1
auto[939524096:1073741823]	98	1			T20	1		T21	1		T53	1
auto[1073741824:1207959551]	110	1			T2	1		T17	1		T27	1
auto[1207959552:1342177279]	107	1			T18	1		T71	1		T92	1
auto[1342177280:1476395007]	101	1			T20	1		T82	1		T92	1
auto[1476395008:1610612735]	95	1			T70	1		T32	1		T214	1
auto[1610612736:1744830463]	95	1			T71	1		T51	1		T53	1
auto[1744830464:1879048191]	109	1			T104	1		T91	1		T64	1
auto[1879048192:2013265919]	101	1			T21	1		T111	1		T104	1
auto[2013265920:2147483647]	87	1			T21	1		T70	1		T92	1
auto[2147483648:2281701375]	101	1			T17	1		T21	2		T82	1
auto[2281701376:2415919103]	112	1			T74	1		T56	1		T52	1
auto[2415919104:2550136831]	109	1			T56	1		T91	1		T53	1
auto[2550136832:2684354559]	97	1			T5	1		T92	2		T291	1
auto[2684354560:2818572287]	92	1			T20	1		T72	2		T215	1
auto[2818572288:2952790015]	104	1			T27	1		T74	1		T165	1
auto[2952790016:3087007743]	92	1			T2	1		T111	1		T206	1
auto[3087007744:3221225471]	90	1			T5	1		T71	1		T104	1
auto[3221225472:3355443199]	102	1			T91	1		T92	1		T317	1
auto[3355443200:3489660927]	102	1			T27	1		T74	1		T70	1
auto[3489660928:3623878655]	93	1			T111	1		T165	1		T71	1
auto[3623878656:3758096383]	110	1			T21	1		T70	1		T91	1
auto[3758096384:3892314111]	89	1			T21	1		T214	1		T72	1
auto[3892314112:4026531839]	103	1			T165	1		T214	1		T92	1
auto[4026531840:4160749567]	96	1			T74	1		T51	1		T53	1
auto[4160749568:4294967295]	116	1			T21	1		T91	1		T82	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	81	1			T27	1		T21	1		T220	1
auto[0:134217727]	auto[1]	7	1			T274	1		T277	1		T267	1
auto[134217728:268435455]	auto[0]	99	1			T215	1		T212	1		T257	1
auto[134217728:268435455]	auto[1]	6	1			T91	1		T112	1		T306	1
auto[268435456:402653183]	auto[0]	97	1			T21	1		T74	1		T104	1
auto[268435456:402653183]	auto[1]	4	1			T333	1		T253	1		T353	1
auto[402653184:536870911]	auto[0]	93	1			T56	1		T28	1		T72	1
auto[402653184:536870911]	auto[1]	7	1			T112	1		T274	1		T253	1
auto[536870912:671088639]	auto[0]	93	1			T2	1		T6	1		T206	1
auto[536870912:671088639]	auto[1]	7	1			T126	1		T114	1		T251	2
auto[671088640:805306367]	auto[0]	77	1			T5	1		T257	1		T44	1
auto[671088640:805306367]	auto[1]	7	1			T251	1		T306	1		T253	1
auto[805306368:939524095]	auto[0]	94	1			T6	1		T214	1		T215	2
auto[805306368:939524095]	auto[1]	7	1			T92	1		T306	1		T116	1
auto[939524096:1073741823]	auto[0]	90	1			T20	1		T21	1		T53	1
auto[939524096:1073741823]	auto[1]	8	1			T306	1		T274	1		T435	1
auto[1073741824:1207959551]	auto[0]	106	1			T2	1		T17	1		T27	1
auto[1073741824:1207959551]	auto[1]	4	1			T92	1		T420	1		T422	1
auto[1207959552:1342177279]	auto[0]	96	1			T18	1		T71	1		T92	1
auto[1207959552:1342177279]	auto[1]	11	1			T116	1		T117	1		T333	1
auto[1342177280:1476395007]	auto[0]	89	1			T20	1		T82	1		T92	1
auto[1342177280:1476395007]	auto[1]	12	1			T251	1		T306	1		T333	1
auto[1476395008:1610612735]	auto[0]	88	1			T70	1		T32	1		T214	1
auto[1476395008:1610612735]	auto[1]	7	1			T393	1		T267	1		T436	1
auto[1610612736:1744830463]	auto[0]	82	1			T71	1		T51	1		T53	1
auto[1610612736:1744830463]	auto[1]	13	1			T126	3		T114	1		T306	1
auto[1744830464:1879048191]	auto[0]	101	1			T104	1		T64	1		T206	1
auto[1744830464:1879048191]	auto[1]	8	1			T91	1		T274	1		T425	1
auto[1879048192:2013265919]	auto[0]	93	1			T21	1		T111	1		T104	1
auto[1879048192:2013265919]	auto[1]	8	1			T251	1		T333	1		T253	1
auto[2013265920:2147483647]	auto[0]	83	1			T21	1		T70	1		T136	2
auto[2013265920:2147483647]	auto[1]	4	1			T92	1		T251	1		T282	1
auto[2147483648:2281701375]	auto[0]	95	1			T17	1		T21	2		T82	1
auto[2147483648:2281701375]	auto[1]	6	1			T251	1		T274	1		T253	1
auto[2281701376:2415919103]	auto[0]	103	1			T74	1		T56	1		T52	1
auto[2281701376:2415919103]	auto[1]	9	1			T126	1		T116	1		T277	1
auto[2415919104:2550136831]	auto[0]	103	1			T56	1		T91	1		T53	1
auto[2415919104:2550136831]	auto[1]	6	1			T306	1		T163	1		T274	1
auto[2550136832:2684354559]	auto[0]	83	1			T5	1		T92	1		T291	1
auto[2550136832:2684354559]	auto[1]	14	1			T92	1		T251	1		T333	1
auto[2684354560:2818572287]	auto[0]	86	1			T20	1		T72	2		T215	1
auto[2684354560:2818572287]	auto[1]	6	1			T163	1		T255	1		T436	1
auto[2818572288:2952790015]	auto[0]	97	1			T27	1		T74	1		T165	1
auto[2818572288:2952790015]	auto[1]	7	1			T92	1		T305	1		T436	1
auto[2952790016:3087007743]	auto[0]	86	1			T2	1		T111	1		T206	1
auto[2952790016:3087007743]	auto[1]	6	1			T126	1		T426	1		T304	1
auto[3087007744:3221225471]	auto[0]	80	1			T5	1		T71	1		T104	1
auto[3087007744:3221225471]	auto[1]	10	1			T326	1		T305	1		T353	1
auto[3221225472:3355443199]	auto[0]	92	1			T91	1		T317	1		T258	1
auto[3221225472:3355443199]	auto[1]	10	1			T92	1		T163	1		T253	1
auto[3355443200:3489660927]	auto[0]	95	1			T27	1		T74	1		T70	1
auto[3355443200:3489660927]	auto[1]	7	1			T114	1		T326	1		T298	1
auto[3489660928:3623878655]	auto[0]	87	1			T111	1		T165	1		T71	1
auto[3489660928:3623878655]	auto[1]	6	1			T92	1		T253	1		T426	1
auto[3623878656:3758096383]	auto[0]	100	1			T21	1		T70	1		T51	1
auto[3623878656:3758096383]	auto[1]	10	1			T91	1		T92	1		T114	1
auto[3758096384:3892314111]	auto[0]	81	1			T21	1		T214	1		T72	1
auto[3758096384:3892314111]	auto[1]	8	1			T306	1		T274	1		T253	1
auto[3892314112:4026531839]	auto[0]	96	1			T165	1		T214	1		T44	2
auto[3892314112:4026531839]	auto[1]	7	1			T92	1		T305	1		T247	1
auto[4026531840:4160749567]	auto[0]	89	1			T74	1		T51	1		T53	1
auto[4026531840:4160749567]	auto[1]	7	1			T92	1		T333	1		T393	1
auto[4160749568:4294967295]	auto[0]	110	1			T21	1		T82	1		T28	1
auto[4160749568:4294967295]	auto[1]	6	1			T91	1		T251	1		T163	1