Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1699

1

T2

1

T3

4

T18

1

auto[1]

1744

1

T2

2

T3

1

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	79	1			T165	1		T70	1		T317	1
auto[134217728:268435455]	96	1			T111	1		T70	1		T64	1
auto[268435456:402653183]	103	1			T71	1		T136	1		T248	1
auto[402653184:536870911]	107	1			T72	2		T317	1		T7	1
auto[536870912:671088639]	117	1			T3	1		T20	1		T21	1
auto[671088640:805306367]	118	1			T27	1		T21	1		T70	1
auto[805306368:939524095]	106	1			T5	1		T74	1		T72	1
auto[939524096:1073741823]	107	1			T165	1		T104	1		T214	1
auto[1073741824:1207959551]	95	1			T104	2		T72	1		T392	1
auto[1207959552:1342177279]	110	1			T51	1		T28	1		T53	1
auto[1342177280:1476395007]	100	1			T6	1		T71	1		T112	1
auto[1476395008:1610612735]	117	1			T74	1		T51	1		T206	1
auto[1610612736:1744830463]	99	1			T5	1		T104	1		T214	1
auto[1744830464:1879048191]	108	1			T18	1		T111	1		T70	1
auto[1879048192:2013265919]	116	1			T32	1		T53	1		T130	1
auto[2013265920:2147483647]	106	1			T3	1		T20	1		T21	1
auto[2147483648:2281701375]	118	1			T91	1		T135	1		T136	1
auto[2281701376:2415919103]	113	1			T2	1		T17	1		T27	1
auto[2415919104:2550136831]	100	1			T2	1		T74	1		T53	1
auto[2550136832:2684354559]	101	1			T21	1		T131	1		T73	1
auto[2684354560:2818572287]	108	1			T20	1		T21	1		T70	2
auto[2818572288:2952790015]	113	1			T3	1		T74	1		T71	1
auto[2952790016:3087007743]	99	1			T2	1		T17	1		T111	1
auto[3087007744:3221225471]	103	1			T3	1		T27	1		T70	1
auto[3221225472:3355443199]	114	1			T21	3		T56	1		T91	1
auto[3355443200:3489660927]	122	1			T27	1		T32	1		T64	1
auto[3489660928:3623878655]	117	1			T53	1		T92	2		T112	1
auto[3623878656:3758096383]	117	1			T82	1		T317	1		T392	1
auto[3758096384:3892314111]	110	1			T51	1		T206	1		T112	1
auto[3892314112:4026531839]	93	1			T5	1		T56	1		T28	1
auto[4026531840:4160749567]	103	1			T3	1		T6	2		T71	2
auto[4160749568:4294967295]	128	1			T20	1		T165	1		T52	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	35	1			T70	1		T294	1		T281	1
auto[0:134217727]	auto[1]	44	1			T165	1		T317	1		T279	1
auto[134217728:268435455]	auto[0]	45	1			T111	1		T70	1		T53	1
auto[134217728:268435455]	auto[1]	51	1			T64	1		T77	1		T290	1
auto[268435456:402653183]	auto[0]	57	1			T71	1		T136	1		T78	2
auto[268435456:402653183]	auto[1]	46	1			T248	1		T390	1		T78	1
auto[402653184:536870911]	auto[0]	48	1			T317	1		T44	1		T75	1
auto[402653184:536870911]	auto[1]	59	1			T72	2		T7	1		T257	1
auto[536870912:671088639]	auto[0]	64	1			T3	1		T20	1		T91	1
auto[536870912:671088639]	auto[1]	53	1			T21	1		T76	1		T77	2
auto[671088640:805306367]	auto[0]	58	1			T21	1		T70	1		T214	1
auto[671088640:805306367]	auto[1]	60	1			T27	1		T288	2		T289	1
auto[805306368:939524095]	auto[0]	47	1			T74	1		T280	1		T342	1
auto[805306368:939524095]	auto[1]	59	1			T5	1		T72	1		T215	1
auto[939524096:1073741823]	auto[0]	46	1			T92	1		T54	1		T75	1
auto[939524096:1073741823]	auto[1]	61	1			T165	1		T104	1		T214	1
auto[1073741824:1207959551]	auto[0]	47	1			T8	1		T218	1		T223	1
auto[1073741824:1207959551]	auto[1]	48	1			T104	2		T72	1		T392	1
auto[1207959552:1342177279]	auto[0]	57	1			T28	1		T53	1		T392	1
auto[1207959552:1342177279]	auto[1]	53	1			T51	1		T317	1		T7	1
auto[1342177280:1476395007]	auto[0]	52	1			T71	1		T54	1		T44	1
auto[1342177280:1476395007]	auto[1]	48	1			T6	1		T112	1		T217	1
auto[1476395008:1610612735]	auto[0]	49	1			T74	1		T129	1		T289	1
auto[1476395008:1610612735]	auto[1]	68	1			T51	1		T206	1		T212	1
auto[1610612736:1744830463]	auto[0]	50	1			T214	1		T128	2		T135	1
auto[1610612736:1744830463]	auto[1]	49	1			T5	1		T104	1		T317	1
auto[1744830464:1879048191]	auto[0]	49	1			T18	1		T92	1		T392	1
auto[1744830464:1879048191]	auto[1]	59	1			T111	1		T70	1		T214	1
auto[1879048192:2013265919]	auto[0]	56	1			T53	1		T130	1		T258	1
auto[1879048192:2013265919]	auto[1]	60	1			T32	1		T220	1		T75	1
auto[2013265920:2147483647]	auto[0]	54	1			T3	1		T51	1		T40	1
auto[2013265920:2147483647]	auto[1]	52	1			T20	1		T21	1		T206	1
auto[2147483648:2281701375]	auto[0]	60	1			T91	1		T135	1		T136	1
auto[2147483648:2281701375]	auto[1]	58	1			T113	1		T318	1		T390	1
auto[2281701376:2415919103]	auto[0]	60	1			T111	1		T74	1		T308	1
auto[2281701376:2415919103]	auto[1]	53	1			T2	1		T17	1		T27	1
auto[2415919104:2550136831]	auto[0]	50	1			T74	1		T53	1		T135	1
auto[2415919104:2550136831]	auto[1]	50	1			T2	1		T112	2		T77	1
auto[2550136832:2684354559]	auto[0]	53	1			T21	1		T131	1		T73	1
auto[2550136832:2684354559]	auto[1]	48	1			T217	2		T290	2		T78	1
auto[2684354560:2818572287]	auto[0]	58	1			T20	1		T70	2		T104	1
auto[2684354560:2818572287]	auto[1]	50	1			T21	1		T215	1		T212	1
auto[2818572288:2952790015]	auto[0]	56	1			T3	1		T74	1		T214	1
auto[2818572288:2952790015]	auto[1]	57	1			T71	1		T72	1		T215	1
auto[2952790016:3087007743]	auto[0]	47	1			T2	1		T51	1		T64	1
auto[2952790016:3087007743]	auto[1]	52	1			T17	1		T111	1		T82	1
auto[3087007744:3221225471]	auto[0]	38	1			T3	1		T70	1		T52	1
auto[3087007744:3221225471]	auto[1]	65	1			T27	1		T51	1		T113	1
auto[3221225472:3355443199]	auto[0]	59	1			T21	1		T56	1		T52	1
auto[3221225472:3355443199]	auto[1]	55	1			T21	2		T91	1		T130	1
auto[3355443200:3489660927]	auto[0]	59	1			T32	1		T215	1		T44	1
auto[3355443200:3489660927]	auto[1]	63	1			T27	1		T64	1		T220	1
auto[3489660928:3623878655]	auto[0]	66	1			T53	1		T92	2		T112	1
auto[3489660928:3623878655]	auto[1]	51	1			T77	1		T147	1		T114	1
auto[3623878656:3758096383]	auto[0]	59	1			T82	1		T317	1		T9	1
auto[3623878656:3758096383]	auto[1]	58	1			T392	1		T270	1		T251	1
auto[3758096384:3892314111]	auto[0]	61	1			T51	1		T112	1		T8	1
auto[3758096384:3892314111]	auto[1]	49	1			T206	1		T77	1		T208	1
auto[3892314112:4026531839]	auto[0]	51	1			T56	1		T212	1		T77	1
auto[3892314112:4026531839]	auto[1]	42	1			T5	1		T28	1		T7	1
auto[4026531840:4160749567]	auto[0]	53	1			T6	1		T51	1		T8	1
auto[4026531840:4160749567]	auto[1]	50	1			T3	1		T6	1		T71	2
auto[4160749568:4294967295]	auto[0]	55	1			T20	1		T52	1		T144	1
auto[4160749568:4294967295]	auto[1]	73	1			T165	1		T72	3		T75	1