dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4702 1 T2 4 T3 8 T5 4
auto[1] 2184 1 T2 2 T3 2 T5 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 216 1 T21 2 T7 2 T215 2
auto[134217728:268435455] 206 1 T6 2 T51 2 T112 2
auto[268435456:402653183] 218 1 T71 2 T51 2 T28 2
auto[402653184:536870911] 224 1 T165 2 T70 2 T104 2
auto[536870912:671088639] 212 1 T111 2 T53 2 T206 2
auto[671088640:805306367] 224 1 T2 2 T3 2 T70 2
auto[805306368:939524095] 228 1 T21 2 T9 2 T279 2
auto[939524096:1073741823] 220 1 T21 2 T70 2 T220 2
auto[1073741824:1207959551] 222 1 T70 2 T82 2 T72 2
auto[1207959552:1342177279] 210 1 T2 2 T21 2 T6 2
auto[1342177280:1476395007] 250 1 T32 2 T206 2 T128 2
auto[1476395008:1610612735] 198 1 T214 2 T7 2 T215 2
auto[1610612736:1744830463] 236 1 T27 2 T74 2 T214 2
auto[1744830464:1879048191] 216 1 T3 2 T5 2 T21 2
auto[1879048192:2013265919] 236 1 T3 4 T21 2 T70 2
auto[2013265920:2147483647] 236 1 T17 2 T20 2 T91 2
auto[2147483648:2281701375] 230 1 T74 2 T6 2 T64 2
auto[2281701376:2415919103] 222 1 T21 2 T165 2 T52 2
auto[2415919104:2550136831] 182 1 T18 2 T82 2 T64 2
auto[2550136832:2684354559] 160 1 T17 2 T71 2 T130 2
auto[2684354560:2818572287] 218 1 T2 2 T20 2 T21 2
auto[2818572288:2952790015] 198 1 T5 2 T27 2 T21 2
auto[2952790016:3087007743] 184 1 T165 2 T112 2 T72 4
auto[3087007744:3221225471] 182 1 T20 2 T27 2 T74 2
auto[3221225472:3355443199] 198 1 T20 2 T74 4 T136 2
auto[3355443200:3489660927] 218 1 T3 2 T27 2 T51 2
auto[3489660928:3623878655] 224 1 T5 2 T71 2 T112 4
auto[3623878656:3758096383] 236 1 T21 2 T111 2 T70 2
auto[3758096384:3892314111] 236 1 T56 2 T71 2 T91 2
auto[3892314112:4026531839] 202 1 T56 2 T32 2 T92 2
auto[4026531840:4160749567] 236 1 T111 4 T56 2 T51 2
auto[4160749568:4294967295] 208 1 T104 4 T52 2 T112 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 148 1 T21 2 T7 2 T215 2
auto[0:134217727] auto[1] 68 1 T44 2 T77 2 T294 2
auto[134217728:268435455] auto[0] 152 1 T6 2 T51 2 T112 2
auto[134217728:268435455] auto[1] 54 1 T8 2 T76 2 T77 2
auto[268435456:402653183] auto[0] 150 1 T71 2 T51 2 T113 2
auto[268435456:402653183] auto[1] 68 1 T28 2 T212 2 T76 2
auto[402653184:536870911] auto[0] 158 1 T70 2 T104 2 T54 2
auto[402653184:536870911] auto[1] 66 1 T165 2 T52 2 T72 2
auto[536870912:671088639] auto[0] 160 1 T111 2 T53 2 T55 2
auto[536870912:671088639] auto[1] 52 1 T206 2 T78 2 T142 2
auto[671088640:805306367] auto[0] 154 1 T70 2 T51 2 T53 2
auto[671088640:805306367] auto[1] 70 1 T2 2 T3 2 T64 2
auto[805306368:939524095] auto[0] 146 1 T21 2 T279 2 T136 2
auto[805306368:939524095] auto[1] 82 1 T9 2 T8 2 T136 2
auto[939524096:1073741823] auto[0] 150 1 T21 2 T70 2 T220 2
auto[939524096:1073741823] auto[1] 70 1 T126 2 T208 2 T390 2
auto[1073741824:1207959551] auto[0] 164 1 T70 2 T82 2 T72 2
auto[1073741824:1207959551] auto[1] 58 1 T132 2 T305 2 T211 2
auto[1207959552:1342177279] auto[0] 138 1 T2 2 T82 2 T53 2
auto[1207959552:1342177279] auto[1] 72 1 T21 2 T6 2 T206 2
auto[1342177280:1476395007] auto[0] 166 1 T7 2 T288 2 T289 2
auto[1342177280:1476395007] auto[1] 84 1 T32 2 T206 2 T128 2
auto[1476395008:1610612735] auto[0] 154 1 T7 2 T44 2 T136 4
auto[1476395008:1610612735] auto[1] 44 1 T214 2 T215 2 T212 2
auto[1610612736:1744830463] auto[0] 174 1 T74 2 T214 2 T92 2
auto[1610612736:1744830463] auto[1] 62 1 T27 2 T208 2 T78 4
auto[1744830464:1879048191] auto[0] 154 1 T3 2 T5 2 T91 2
auto[1744830464:1879048191] auto[1] 62 1 T21 2 T89 2 T375 2
auto[1879048192:2013265919] auto[0] 146 1 T3 4 T21 2 T70 2
auto[1879048192:2013265919] auto[1] 90 1 T8 2 T44 2 T76 2
auto[2013265920:2147483647] auto[0] 172 1 T20 2 T91 2 T51 2
auto[2013265920:2147483647] auto[1] 64 1 T17 2 T128 2 T270 2
auto[2147483648:2281701375] auto[0] 146 1 T74 2 T64 2 T28 4
auto[2147483648:2281701375] auto[1] 84 1 T6 2 T215 2 T291 2
auto[2281701376:2415919103] auto[0] 138 1 T215 2 T392 2 T136 2
auto[2281701376:2415919103] auto[1] 84 1 T21 2 T165 2 T52 2
auto[2415919104:2550136831] auto[0] 126 1 T131 2 T114 2 T78 6
auto[2415919104:2550136831] auto[1] 56 1 T18 2 T82 2 T64 2
auto[2550136832:2684354559] auto[0] 110 1 T71 2 T7 2 T84 2
auto[2550136832:2684354559] auto[1] 50 1 T17 2 T130 2 T79 2
auto[2684354560:2818572287] auto[0] 138 1 T2 2 T20 2 T21 2
auto[2684354560:2818572287] auto[1] 80 1 T104 2 T379 2 T11 2
auto[2818572288:2952790015] auto[0] 122 1 T21 2 T70 2 T104 2
auto[2818572288:2952790015] auto[1] 76 1 T5 2 T27 2 T218 2
auto[2952790016:3087007743] auto[0] 134 1 T112 2 T72 4 T270 2
auto[2952790016:3087007743] auto[1] 50 1 T165 2 T144 2 T248 2
auto[3087007744:3221225471] auto[0] 110 1 T20 2 T74 2 T136 2
auto[3087007744:3221225471] auto[1] 72 1 T27 2 T71 2 T257 2
auto[3221225472:3355443199] auto[0] 122 1 T20 2 T74 2 T136 2
auto[3221225472:3355443199] auto[1] 76 1 T74 2 T76 2 T77 2
auto[3355443200:3489660927] auto[0] 152 1 T3 2 T51 2 T279 2
auto[3355443200:3489660927] auto[1] 66 1 T27 2 T390 2 T289 2
auto[3489660928:3623878655] auto[0] 152 1 T5 2 T71 2 T112 4
auto[3489660928:3623878655] auto[1] 72 1 T215 2 T78 2 T140 2
auto[3623878656:3758096383] auto[0] 170 1 T111 2 T70 2 T51 2
auto[3623878656:3758096383] auto[1] 66 1 T21 2 T40 2 T130 2
auto[3758096384:3892314111] auto[0] 162 1 T56 2 T71 2 T91 2
auto[3758096384:3892314111] auto[1] 74 1 T218 2 T147 2 T114 2
auto[3892314112:4026531839] auto[0] 134 1 T92 2 T72 2 T392 2
auto[3892314112:4026531839] auto[1] 68 1 T56 2 T32 2 T131 2
auto[4026531840:4160749567] auto[0] 162 1 T56 2 T51 2 T92 2
auto[4026531840:4160749567] auto[1] 74 1 T111 4 T214 2 T390 2
auto[4160749568:4294967295] auto[0] 138 1 T104 4 T52 2 T112 2
auto[4160749568:4294967295] auto[1] 70 1 T208 2 T78 4 T298 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%