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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.07 98.43 100.00 99.02 98.63 91.19


Total test records in report: 1083
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T180 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.208515282 Sep 04 03:02:17 AM UTC 24 Sep 04 03:02:21 AM UTC 24 55094773 ps
T1007 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2748877430 Sep 04 03:02:17 AM UTC 24 Sep 04 03:02:21 AM UTC 24 48033603 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1515014928 Sep 04 03:02:15 AM UTC 24 Sep 04 03:02:21 AM UTC 24 467415291 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.4132003209 Sep 04 03:02:19 AM UTC 24 Sep 04 03:02:21 AM UTC 24 33752038 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.3180690803 Sep 04 03:02:19 AM UTC 24 Sep 04 03:02:21 AM UTC 24 121312218 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3151138118 Sep 04 03:02:16 AM UTC 24 Sep 04 03:02:21 AM UTC 24 465420001 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1623671389 Sep 04 03:02:19 AM UTC 24 Sep 04 03:02:22 AM UTC 24 36271750 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2350288563 Sep 04 03:02:19 AM UTC 24 Sep 04 03:02:22 AM UTC 24 45703687 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3791716460 Sep 04 03:02:19 AM UTC 24 Sep 04 03:02:22 AM UTC 24 64937936 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1393542806 Sep 04 03:02:19 AM UTC 24 Sep 04 03:02:22 AM UTC 24 64721621 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.793579079 Sep 04 03:02:18 AM UTC 24 Sep 04 03:02:23 AM UTC 24 81721749 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.291865333 Sep 04 03:02:15 AM UTC 24 Sep 04 03:02:23 AM UTC 24 2670744530 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.4060771105 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:23 AM UTC 24 13036278 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.645504079 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:23 AM UTC 24 17241156 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.581730026 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:23 AM UTC 24 51156068 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.2383825946 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:24 AM UTC 24 29798202 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3119686436 Sep 04 03:02:19 AM UTC 24 Sep 04 03:02:24 AM UTC 24 127178923 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1449981681 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:24 AM UTC 24 81390086 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.4027491954 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:24 AM UTC 24 544997097 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3695054918 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:25 AM UTC 24 127043825 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.586118852 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:26 AM UTC 24 197035421 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1754960946 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:25 AM UTC 24 175358022 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1319523444 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:25 AM UTC 24 275356801 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.4018889081 Sep 04 03:02:15 AM UTC 24 Sep 04 03:02:25 AM UTC 24 1340089675 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2991903543 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:25 AM UTC 24 96833194 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.445543122 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:25 AM UTC 24 11628047 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3176922077 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:25 AM UTC 24 21616862 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1811175803 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:26 AM UTC 24 19415890 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.386249128 Sep 04 03:02:10 AM UTC 24 Sep 04 03:02:26 AM UTC 24 448753318 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.801204237 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:26 AM UTC 24 102411208 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4076424675 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:26 AM UTC 24 36391340 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.1698851400 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:27 AM UTC 24 11493321 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3337820426 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:27 AM UTC 24 84729646 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.105722070 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:27 AM UTC 24 100429825 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1208525273 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:27 AM UTC 24 39890387 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.4127183594 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:28 AM UTC 24 24451112 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3708449596 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:28 AM UTC 24 114424089 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.1058996470 Sep 04 03:02:24 AM UTC 24 Sep 04 03:02:29 AM UTC 24 278995926 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1801900816 Sep 04 03:02:27 AM UTC 24 Sep 04 03:02:29 AM UTC 24 34852738 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3821519875 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:29 AM UTC 24 692155068 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2355641630 Sep 04 03:02:27 AM UTC 24 Sep 04 03:02:29 AM UTC 24 20823506 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2596057876 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:29 AM UTC 24 119614377 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2409356586 Sep 04 03:02:27 AM UTC 24 Sep 04 03:02:29 AM UTC 24 15294694 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.4129104438 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 30564247 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3091019752 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:30 AM UTC 24 129516014 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1008950578 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 38332760 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1005915939 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 13404716 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2957264173 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 51198674 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4055894168 Sep 04 03:02:27 AM UTC 24 Sep 04 03:02:30 AM UTC 24 21933499 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.131492722 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 11979760 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2756183559 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 14406377 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.1674562299 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 10698865 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1339406595 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 23212082 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2954480652 Sep 04 03:02:27 AM UTC 24 Sep 04 03:02:30 AM UTC 24 14644881 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1852680984 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 30803288 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2544584613 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:30 AM UTC 24 315975985 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1839889285 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:30 AM UTC 24 306334852 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.787752796 Sep 04 03:02:28 AM UTC 24 Sep 04 03:02:30 AM UTC 24 14058920 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4037959606 Sep 04 03:02:27 AM UTC 24 Sep 04 03:02:30 AM UTC 24 53938275 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.981258309 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:31 AM UTC 24 345042392 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3890816309 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:31 AM UTC 24 1159009749 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.4211383511 Sep 04 03:02:29 AM UTC 24 Sep 04 03:02:31 AM UTC 24 9001815 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.727315310 Sep 04 03:02:29 AM UTC 24 Sep 04 03:02:31 AM UTC 24 13869966 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1678816184 Sep 04 03:02:29 AM UTC 24 Sep 04 03:02:31 AM UTC 24 51506645 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.137575368 Sep 04 03:02:29 AM UTC 24 Sep 04 03:02:31 AM UTC 24 28357889 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2943779399 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:32 AM UTC 24 533046388 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2830285076 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:33 AM UTC 24 9919798 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1700088585 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:33 AM UTC 24 42937082 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3893404481 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 11877706 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.986620125 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 12793059 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3559436201 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 11444688 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.439377864 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 37899979 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3557218917 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 45643432 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1222863433 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 21160729 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3831216282 Sep 04 03:02:16 AM UTC 24 Sep 04 03:02:34 AM UTC 24 643513892 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.3354843546 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 17747088 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.4254272855 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 11664589 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1923716550 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 8528056 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2702327981 Sep 04 03:02:32 AM UTC 24 Sep 04 03:02:34 AM UTC 24 33161080 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.2769066409 Sep 04 03:02:23 AM UTC 24 Sep 04 03:02:35 AM UTC 24 476231511 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.1696359343 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:35 AM UTC 24 2485098568 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3954620943 Sep 04 03:02:21 AM UTC 24 Sep 04 03:02:37 AM UTC 24 1663498302 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2574981935 Sep 04 03:02:25 AM UTC 24 Sep 04 03:02:40 AM UTC 24 415428555 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.574881029
Short name T5
Test name
Test status
Simulation time 341532161 ps
CPU time 6.5 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:56:58 AM UTC 24
Peak memory 218368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574881029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.574881029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.2849174852
Short name T78
Test name
Test status
Simulation time 1591391137 ps
CPU time 63.74 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:57:59 AM UTC 24
Peak memory 232532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849174852 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2849174852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.2102836187
Short name T6
Test name
Test status
Simulation time 554545503 ps
CPU time 10.16 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:57:05 AM UTC 24
Peak memory 232612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2102836187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr
_stress_all_with_rand_reset.2102836187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.3174479534
Short name T12
Test name
Test status
Simulation time 4979185656 ps
CPU time 12 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:57:07 AM UTC 24
Peak memory 254440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174479534 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3174479534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.329259255
Short name T77
Test name
Test status
Simulation time 944253717 ps
CPU time 21.21 seconds
Started Sep 04 02:57:27 AM UTC 24
Finished Sep 04 02:57:49 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329259255 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.329259255
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.1996670329
Short name T21
Test name
Test status
Simulation time 220233675 ps
CPU time 5.72 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:57:00 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996670329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1996670329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.3321514597
Short name T92
Test name
Test status
Simulation time 591218963 ps
CPU time 27.15 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:57:18 AM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321514597 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3321514597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.356875732
Short name T74
Test name
Test status
Simulation time 58861431 ps
CPU time 2.45 seconds
Started Sep 04 02:57:00 AM UTC 24
Finished Sep 04 02:57:04 AM UTC 24
Peak memory 223972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356875732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.356875732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all_with_rand_reset.4200747227
Short name T102
Test name
Test status
Simulation time 1594301653 ps
CPU time 28.08 seconds
Started Sep 04 02:58:49 AM UTC 24
Finished Sep 04 02:59:18 AM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4200747227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymg
r_stress_all_with_rand_reset.4200747227
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.137319998
Short name T20
Test name
Test status
Simulation time 149817126 ps
CPU time 5.01 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:56:59 AM UTC 24
Peak memory 224420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137319998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.137319998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.3823892291
Short name T211
Test name
Test status
Simulation time 10701051007 ps
CPU time 75.42 seconds
Started Sep 04 02:57:01 AM UTC 24
Finished Sep 04 02:58:19 AM UTC 24
Peak memory 232352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823892291 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3823892291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1985315883
Short name T86
Test name
Test status
Simulation time 195778115 ps
CPU time 5.47 seconds
Started Sep 04 03:01:50 AM UTC 24
Finished Sep 04 03:01:57 AM UTC 24
Peak memory 232752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985315883 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.1985315883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.1674903937
Short name T9
Test name
Test status
Simulation time 225135584 ps
CPU time 3.27 seconds
Started Sep 04 02:57:26 AM UTC 24
Finished Sep 04 02:57:31 AM UTC 24
Peak memory 230576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674903937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1674903937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.902109700
Short name T112
Test name
Test status
Simulation time 805789999 ps
CPU time 13.27 seconds
Started Sep 04 02:57:05 AM UTC 24
Finished Sep 04 02:57:20 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902109700 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.902109700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.544249670
Short name T253
Test name
Test status
Simulation time 1392749765 ps
CPU time 71.21 seconds
Started Sep 04 02:58:20 AM UTC 24
Finished Sep 04 02:59:33 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544249670 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.544249670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.4015180950
Short name T72
Test name
Test status
Simulation time 2130302995 ps
CPU time 11.89 seconds
Started Sep 04 02:57:09 AM UTC 24
Finished Sep 04 02:57:22 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015180950 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.4015180950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.2138546757
Short name T58
Test name
Test status
Simulation time 131745656 ps
CPU time 4.51 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:48 AM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138546757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2138546757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.1159197020
Short name T91
Test name
Test status
Simulation time 245629216 ps
CPU time 6.08 seconds
Started Sep 04 02:56:59 AM UTC 24
Finished Sep 04 02:57:06 AM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159197020 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1159197020
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3761595890
Short name T87
Test name
Test status
Simulation time 178717475 ps
CPU time 3.88 seconds
Started Sep 04 03:01:56 AM UTC 24
Finished Sep 04 03:02:00 AM UTC 24
Peak memory 226496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761595890 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.3761595890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.2366299738
Short name T71
Test name
Test status
Simulation time 58245072 ps
CPU time 4.27 seconds
Started Sep 04 02:57:00 AM UTC 24
Finished Sep 04 02:57:06 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366299738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2366299738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.1250331481
Short name T423
Test name
Test status
Simulation time 604014302 ps
CPU time 15.54 seconds
Started Sep 04 03:01:33 AM UTC 24
Finished Sep 04 03:01:50 AM UTC 24
Peak memory 225480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250331481 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1250331481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.88101559
Short name T231
Test name
Test status
Simulation time 522003408 ps
CPU time 20.49 seconds
Started Sep 04 02:58:08 AM UTC 24
Finished Sep 04 02:58:30 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88101559 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.88101559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.394864585
Short name T163
Test name
Test status
Simulation time 6579027503 ps
CPU time 71.62 seconds
Started Sep 04 02:57:13 AM UTC 24
Finished Sep 04 02:58:27 AM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394864585 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.394864585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.1781143795
Short name T277
Test name
Test status
Simulation time 360230508 ps
CPU time 9.81 seconds
Started Sep 04 02:58:51 AM UTC 24
Finished Sep 04 02:59:02 AM UTC 24
Peak memory 226536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781143795 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1781143795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.1112388161
Short name T40
Test name
Test status
Simulation time 158569717 ps
CPU time 3.5 seconds
Started Sep 04 02:57:17 AM UTC 24
Finished Sep 04 02:57:21 AM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112388161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1112388161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.1556671114
Short name T51
Test name
Test status
Simulation time 49893138 ps
CPU time 3.07 seconds
Started Sep 04 02:57:07 AM UTC 24
Finished Sep 04 02:57:11 AM UTC 24
Peak memory 226044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556671114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1556671114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.602029136
Short name T22
Test name
Test status
Simulation time 768696333 ps
CPU time 9.5 seconds
Started Sep 04 02:58:47 AM UTC 24
Finished Sep 04 02:58:58 AM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602029136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.602029136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.3511189541
Short name T137
Test name
Test status
Simulation time 2049599394 ps
CPU time 63.97 seconds
Started Sep 04 02:57:57 AM UTC 24
Finished Sep 04 02:59:03 AM UTC 24
Peak memory 231996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511189541 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3511189541
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.3875301124
Short name T15
Test name
Test status
Simulation time 19831415 ps
CPU time 1.22 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:56:56 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875301124 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3875301124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.1051196550
Short name T32
Test name
Test status
Simulation time 313267069 ps
CPU time 3.34 seconds
Started Sep 04 02:57:07 AM UTC 24
Finished Sep 04 02:57:11 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051196550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1051196550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.306628137
Short name T23
Test name
Test status
Simulation time 638588036 ps
CPU time 5.13 seconds
Started Sep 04 02:59:37 AM UTC 24
Finished Sep 04 02:59:43 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306628137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.306628137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.1820538229
Short name T19
Test name
Test status
Simulation time 106674323 ps
CPU time 4.17 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:56:59 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820538229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1820538229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.4256103674
Short name T393
Test name
Test status
Simulation time 539805630 ps
CPU time 7.1 seconds
Started Sep 04 02:59:21 AM UTC 24
Finished Sep 04 02:59:29 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256103674 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4256103674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all_with_rand_reset.276760832
Short name T98
Test name
Test status
Simulation time 5876347513 ps
CPU time 33.6 seconds
Started Sep 04 02:58:09 AM UTC 24
Finished Sep 04 02:58:44 AM UTC 24
Peak memory 232368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=276760832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr
_stress_all_with_rand_reset.276760832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.2801189697
Short name T126
Test name
Test status
Simulation time 58346750 ps
CPU time 3.73 seconds
Started Sep 04 02:57:24 AM UTC 24
Finished Sep 04 02:57:29 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801189697 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2801189697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.96048327
Short name T248
Test name
Test status
Simulation time 120838735 ps
CPU time 4.55 seconds
Started Sep 04 02:58:02 AM UTC 24
Finished Sep 04 02:58:07 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96048327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.96048327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.3286863096
Short name T110
Test name
Test status
Simulation time 701174203 ps
CPU time 11.38 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:57:02 AM UTC 24
Peak memory 217872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286863096 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3286863096
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.1071334521
Short name T178
Test name
Test status
Simulation time 458847086 ps
CPU time 7.07 seconds
Started Sep 04 03:02:10 AM UTC 24
Finished Sep 04 03:02:19 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071334521 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.1071334521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.1269798625
Short name T251
Test name
Test status
Simulation time 1803005810 ps
CPU time 40.07 seconds
Started Sep 04 02:57:32 AM UTC 24
Finished Sep 04 02:58:13 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269798625 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1269798625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.2203579146
Short name T114
Test name
Test status
Simulation time 152771735 ps
CPU time 8.86 seconds
Started Sep 04 02:57:48 AM UTC 24
Finished Sep 04 02:57:58 AM UTC 24
Peak memory 226428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203579146 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2203579146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.3542658019
Short name T29
Test name
Test status
Simulation time 442109396 ps
CPU time 6.08 seconds
Started Sep 04 02:58:08 AM UTC 24
Finished Sep 04 02:58:15 AM UTC 24
Peak memory 232844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542658019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3542658019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.1246471759
Short name T232
Test name
Test status
Simulation time 2398834367 ps
CPU time 27.68 seconds
Started Sep 04 02:59:23 AM UTC 24
Finished Sep 04 02:59:52 AM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246471759 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1246471759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.737959373
Short name T116
Test name
Test status
Simulation time 171491661 ps
CPU time 5.84 seconds
Started Sep 04 02:58:13 AM UTC 24
Finished Sep 04 02:58:20 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737959373 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.737959373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.3187624053
Short name T8
Test name
Test status
Simulation time 130168638 ps
CPU time 2.72 seconds
Started Sep 04 02:57:33 AM UTC 24
Finished Sep 04 02:57:37 AM UTC 24
Peak memory 224480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187624053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3187624053
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.274627411
Short name T44
Test name
Test status
Simulation time 36942290 ps
CPU time 3.11 seconds
Started Sep 04 02:57:33 AM UTC 24
Finished Sep 04 02:57:37 AM UTC 24
Peak memory 219948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274627411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.274627411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.2754793523
Short name T337
Test name
Test status
Simulation time 102104623 ps
CPU time 2.99 seconds
Started Sep 04 02:59:27 AM UTC 24
Finished Sep 04 02:59:31 AM UTC 24
Peak memory 223972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754793523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2754793523
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.3998870964
Short name T306
Test name
Test status
Simulation time 1285368028 ps
CPU time 37.07 seconds
Started Sep 04 02:57:40 AM UTC 24
Finished Sep 04 02:58:18 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998870964 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3998870964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.208515282
Short name T180
Test name
Test status
Simulation time 55094773 ps
CPU time 2.82 seconds
Started Sep 04 03:02:17 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208515282 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.208515282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.3265039977
Short name T25
Test name
Test status
Simulation time 69743556 ps
CPU time 3.78 seconds
Started Sep 04 02:58:21 AM UTC 24
Finished Sep 04 02:58:26 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265039977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3265039977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.2451494971
Short name T426
Test name
Test status
Simulation time 161686465 ps
CPU time 10.86 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:54 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451494971 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2451494971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.553121248
Short name T357
Test name
Test status
Simulation time 209426992 ps
CPU time 6.44 seconds
Started Sep 04 02:59:48 AM UTC 24
Finished Sep 04 02:59:55 AM UTC 24
Peak memory 232112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553121248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.553121248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.2095943183
Short name T204
Test name
Test status
Simulation time 2702626350 ps
CPU time 46.35 seconds
Started Sep 04 03:00:48 AM UTC 24
Finished Sep 04 03:01:36 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095943183 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2095943183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.2069040963
Short name T271
Test name
Test status
Simulation time 1134773338 ps
CPU time 4.49 seconds
Started Sep 04 02:57:47 AM UTC 24
Finished Sep 04 02:57:53 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069040963 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2069040963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all_with_rand_reset.1159707334
Short name T99
Test name
Test status
Simulation time 633544343 ps
CPU time 18.95 seconds
Started Sep 04 02:58:36 AM UTC 24
Finished Sep 04 02:58:56 AM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1159707334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymg
r_stress_all_with_rand_reset.1159707334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_sync_async_fault_cross.280777440
Short name T184
Test name
Test status
Simulation time 833990096 ps
CPU time 6.46 seconds
Started Sep 04 02:59:18 AM UTC 24
Finished Sep 04 02:59:26 AM UTC 24
Peak memory 220076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280777440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.280777440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.1562052031
Short name T190
Test name
Test status
Simulation time 273485317 ps
CPU time 3.86 seconds
Started Sep 04 02:59:12 AM UTC 24
Finished Sep 04 02:59:17 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562052031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1562052031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.4075851298
Short name T194
Test name
Test status
Simulation time 171760966 ps
CPU time 7.5 seconds
Started Sep 04 03:00:14 AM UTC 24
Finished Sep 04 03:00:23 AM UTC 24
Peak memory 228792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075851298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4075851298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.574830685
Short name T305
Test name
Test status
Simulation time 136775858 ps
CPU time 9.2 seconds
Started Sep 04 02:58:07 AM UTC 24
Finished Sep 04 02:58:17 AM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574830685 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.574830685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.2912764405
Short name T343
Test name
Test status
Simulation time 3231714885 ps
CPU time 31.7 seconds
Started Sep 04 02:59:55 AM UTC 24
Finished Sep 04 03:00:28 AM UTC 24
Peak memory 228264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912764405 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2912764405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.2851542883
Short name T624
Test name
Test status
Simulation time 292298546 ps
CPU time 4.41 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:06 AM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851542883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2851542883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1424121172
Short name T169
Test name
Test status
Simulation time 1680815125 ps
CPU time 5.63 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:20 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424121172 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.1424121172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.787974195
Short name T177
Test name
Test status
Simulation time 100476664 ps
CPU time 5.71 seconds
Started Sep 04 03:02:07 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 216004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787974195 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.787974195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sync_async_fault_cross.3731592822
Short name T39
Test name
Test status
Simulation time 53065991 ps
CPU time 3.09 seconds
Started Sep 04 02:57:01 AM UTC 24
Finished Sep 04 02:57:05 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731592822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3731592822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.969407455
Short name T234
Test name
Test status
Simulation time 6389811551 ps
CPU time 189.57 seconds
Started Sep 04 02:58:31 AM UTC 24
Finished Sep 04 03:01:44 AM UTC 24
Peak memory 232284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969407455 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.969407455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.2300134693
Short name T117
Test name
Test status
Simulation time 42112810 ps
CPU time 3.8 seconds
Started Sep 04 02:58:40 AM UTC 24
Finished Sep 04 02:58:45 AM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300134693 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2300134693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.2187469920
Short name T153
Test name
Test status
Simulation time 12867634349 ps
CPU time 41.34 seconds
Started Sep 04 03:00:01 AM UTC 24
Finished Sep 04 03:00:47 AM UTC 24
Peak memory 230340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187469920 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2187469920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.2033559373
Short name T238
Test name
Test status
Simulation time 302132777 ps
CPU time 15.34 seconds
Started Sep 04 03:00:02 AM UTC 24
Finished Sep 04 03:00:21 AM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2033559373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymg
r_stress_all_with_rand_reset.2033559373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.2230850726
Short name T420
Test name
Test status
Simulation time 830440262 ps
CPU time 39.85 seconds
Started Sep 04 03:00:36 AM UTC 24
Finished Sep 04 03:01:17 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230850726 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2230850726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.830522126
Short name T437
Test name
Test status
Simulation time 1706710377 ps
CPU time 83.18 seconds
Started Sep 04 03:01:37 AM UTC 24
Finished Sep 04 03:03:02 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830522126 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.830522126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.1822795464
Short name T258
Test name
Test status
Simulation time 164654065 ps
CPU time 4.79 seconds
Started Sep 04 02:57:33 AM UTC 24
Finished Sep 04 02:57:39 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822795464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1822795464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.1944115911
Short name T176
Test name
Test status
Simulation time 195585158 ps
CPU time 2.63 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:03 AM UTC 24
Peak memory 226200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944115911 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.1944115911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.2354332492
Short name T145
Test name
Test status
Simulation time 172994634 ps
CPU time 4.57 seconds
Started Sep 04 02:58:28 AM UTC 24
Finished Sep 04 02:58:33 AM UTC 24
Peak memory 230620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354332492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2354332492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.2274752866
Short name T191
Test name
Test status
Simulation time 500102764 ps
CPU time 4.69 seconds
Started Sep 04 02:59:48 AM UTC 24
Finished Sep 04 02:59:54 AM UTC 24
Peak memory 232644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274752866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2274752866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.3031927860
Short name T192
Test name
Test status
Simulation time 48414420 ps
CPU time 3.49 seconds
Started Sep 04 03:00:43 AM UTC 24
Finished Sep 04 03:00:47 AM UTC 24
Peak memory 232352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031927860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3031927860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.3419944527
Short name T193
Test name
Test status
Simulation time 160925473 ps
CPU time 3.68 seconds
Started Sep 04 03:01:38 AM UTC 24
Finished Sep 04 03:01:43 AM UTC 24
Peak memory 228732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419944527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3419944527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.1418653
Short name T17
Test name
Test status
Simulation time 66483996 ps
CPU time 4.15 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:56:58 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1418653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.178596068
Short name T67
Test name
Test status
Simulation time 1263215183 ps
CPU time 3.91 seconds
Started Sep 04 02:56:56 AM UTC 24
Finished Sep 04 02:57:01 AM UTC 24
Peak memory 216096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178596068 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.178596068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.445975058
Short name T333
Test name
Test status
Simulation time 1584993651 ps
CPU time 18.92 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:54 AM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445975058 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.445975058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.1245327897
Short name T313
Test name
Test status
Simulation time 230418375 ps
CPU time 3.28 seconds
Started Sep 04 02:58:42 AM UTC 24
Finished Sep 04 02:58:46 AM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245327897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1245327897
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_lc_disable.2738742202
Short name T227
Test name
Test status
Simulation time 247889549 ps
CPU time 16.1 seconds
Started Sep 04 02:59:30 AM UTC 24
Finished Sep 04 02:59:48 AM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738742202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2738742202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.1546844158
Short name T366
Test name
Test status
Simulation time 3140699581 ps
CPU time 46.26 seconds
Started Sep 04 02:59:32 AM UTC 24
Finished Sep 04 03:00:20 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546844158 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1546844158
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.1849182342
Short name T205
Test name
Test status
Simulation time 4504677429 ps
CPU time 40.33 seconds
Started Sep 04 03:00:58 AM UTC 24
Finished Sep 04 03:01:39 AM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849182342 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1849182342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.3019468856
Short name T150
Test name
Test status
Simulation time 1536970060 ps
CPU time 37.27 seconds
Started Sep 04 02:57:52 AM UTC 24
Finished Sep 04 02:58:31 AM UTC 24
Peak memory 228456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019468856 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3019468856
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.1724884952
Short name T26
Test name
Test status
Simulation time 3560211466 ps
CPU time 35.6 seconds
Started Sep 04 02:57:56 AM UTC 24
Finished Sep 04 02:58:33 AM UTC 24
Peak memory 232272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724884952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1724884952
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.2410795484
Short name T173
Test name
Test status
Simulation time 315276979 ps
CPU time 3.43 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:20 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410795484 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.2410795484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.2943779399
Short name T182
Test name
Test status
Simulation time 533046388 ps
CPU time 9.89 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:32 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943779399 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.2943779399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.2769066409
Short name T186
Test name
Test status
Simulation time 476231511 ps
CPU time 10.55 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:35 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769066409 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.2769066409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.1840804223
Short name T172
Test name
Test status
Simulation time 284771722 ps
CPU time 4.57 seconds
Started Sep 04 03:02:01 AM UTC 24
Finished Sep 04 03:02:07 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840804223 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.1840804223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.644513318
Short name T175
Test name
Test status
Simulation time 50579475 ps
CPU time 2.87 seconds
Started Sep 04 03:02:04 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644513318 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.644513318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.3599052626
Short name T57
Test name
Test status
Simulation time 890591269 ps
CPU time 29.08 seconds
Started Sep 04 02:58:08 AM UTC 24
Finished Sep 04 02:58:39 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599052626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3599052626
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.1378339744
Short name T47
Test name
Test status
Simulation time 5390914153 ps
CPU time 8.19 seconds
Started Sep 04 02:57:20 AM UTC 24
Finished Sep 04 02:57:29 AM UTC 24
Peak memory 256508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378339744 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1378339744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.2263646009
Short name T189
Test name
Test status
Simulation time 350577273 ps
CPU time 4.01 seconds
Started Sep 04 02:58:15 AM UTC 24
Finished Sep 04 02:58:19 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263646009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2263646009
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.3206070469
Short name T56
Test name
Test status
Simulation time 124690493 ps
CPU time 4.38 seconds
Started Sep 04 02:57:00 AM UTC 24
Finished Sep 04 02:57:05 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206070469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3206070469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_random.2281316298
Short name T104
Test name
Test status
Simulation time 123154994 ps
CPU time 6.76 seconds
Started Sep 04 02:56:58 AM UTC 24
Finished Sep 04 02:57:06 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281316298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2281316298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.2455427993
Short name T140
Test name
Test status
Simulation time 46217535 ps
CPU time 2.52 seconds
Started Sep 04 02:58:07 AM UTC 24
Finished Sep 04 02:58:10 AM UTC 24
Peak memory 230512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455427993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2455427993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.2696670654
Short name T388
Test name
Test status
Simulation time 186601577 ps
CPU time 4.13 seconds
Started Sep 04 02:58:54 AM UTC 24
Finished Sep 04 02:58:59 AM UTC 24
Peak memory 223972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696670654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2696670654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.2207060660
Short name T292
Test name
Test status
Simulation time 13279020 ps
CPU time 1.7 seconds
Started Sep 04 02:59:11 AM UTC 24
Finished Sep 04 02:59:14 AM UTC 24
Peak memory 216220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207060660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2207060660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.19526442
Short name T360
Test name
Test status
Simulation time 115148711 ps
CPU time 4.66 seconds
Started Sep 04 02:59:17 AM UTC 24
Finished Sep 04 02:59:23 AM UTC 24
Peak memory 232224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19526442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.19526442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.334845749
Short name T323
Test name
Test status
Simulation time 46811718 ps
CPU time 2.78 seconds
Started Sep 04 02:59:54 AM UTC 24
Finished Sep 04 02:59:59 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334845749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.334845749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.1637188572
Short name T304
Test name
Test status
Simulation time 62947878 ps
CPU time 3.76 seconds
Started Sep 04 03:00:07 AM UTC 24
Finished Sep 04 03:00:12 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637188572 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1637188572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.2144888724
Short name T229
Test name
Test status
Simulation time 117149687 ps
CPU time 2.96 seconds
Started Sep 04 03:00:27 AM UTC 24
Finished Sep 04 03:00:31 AM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144888724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2144888724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.2766436917
Short name T434
Test name
Test status
Simulation time 1200147618 ps
CPU time 51.2 seconds
Started Sep 04 03:00:50 AM UTC 24
Finished Sep 04 03:01:43 AM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766436917 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2766436917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.3678116090
Short name T334
Test name
Test status
Simulation time 558511732 ps
CPU time 4.19 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:01 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678116090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3678116090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.2048722874
Short name T394
Test name
Test status
Simulation time 1211690185 ps
CPU time 26.26 seconds
Started Sep 04 03:01:06 AM UTC 24
Finished Sep 04 03:01:34 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048722874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2048722874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.959614214
Short name T235
Test name
Test status
Simulation time 125150567 ps
CPU time 4.03 seconds
Started Sep 04 03:01:11 AM UTC 24
Finished Sep 04 03:01:16 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959614214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.959614214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.995057503
Short name T199
Test name
Test status
Simulation time 1241022034 ps
CPU time 16.47 seconds
Started Sep 04 03:01:50 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 232316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=995057503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr
_stress_all_with_rand_reset.995057503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.523899788
Short name T69
Test name
Test status
Simulation time 464674293 ps
CPU time 7.12 seconds
Started Sep 04 02:57:56 AM UTC 24
Finished Sep 04 02:58:04 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523899788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.523899788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.3913964208
Short name T121
Test name
Test status
Simulation time 254901235 ps
CPU time 6.96 seconds
Started Sep 04 03:01:53 AM UTC 24
Finished Sep 04 03:02:01 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913964208 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3913964208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.928103220
Short name T934
Test name
Test status
Simulation time 2686263424 ps
CPU time 10.85 seconds
Started Sep 04 03:01:53 AM UTC 24
Finished Sep 04 03:02:05 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928103220 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.928103220
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.112023807
Short name T166
Test name
Test status
Simulation time 504191994 ps
CPU time 2.14 seconds
Started Sep 04 03:01:51 AM UTC 24
Finished Sep 04 03:01:54 AM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112023807 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.112023807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4288414836
Short name T398
Test name
Test status
Simulation time 16708108 ps
CPU time 1.35 seconds
Started Sep 04 03:01:54 AM UTC 24
Finished Sep 04 03:01:56 AM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4288414836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_w
ith_rand_reset.4288414836
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.459520204
Short name T118
Test name
Test status
Simulation time 80726361 ps
CPU time 1.36 seconds
Started Sep 04 03:01:53 AM UTC 24
Finished Sep 04 03:01:55 AM UTC 24
Peak memory 213644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459520204 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.459520204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.3379319376
Short name T919
Test name
Test status
Simulation time 11699313 ps
CPU time 1.31 seconds
Started Sep 04 03:01:51 AM UTC 24
Finished Sep 04 03:01:54 AM UTC 24
Peak memory 214876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379319376 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3379319376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3039717025
Short name T119
Test name
Test status
Simulation time 109280388 ps
CPU time 2.07 seconds
Started Sep 04 03:01:53 AM UTC 24
Finished Sep 04 03:01:56 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039717025 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.3039717025
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4157816570
Short name T93
Test name
Test status
Simulation time 93926599 ps
CPU time 2.78 seconds
Started Sep 04 03:01:50 AM UTC 24
Finished Sep 04 03:01:54 AM UTC 24
Peak memory 230776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157816570 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.4157816570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.627191105
Short name T200
Test name
Test status
Simulation time 496671017 ps
CPU time 5.04 seconds
Started Sep 04 03:01:51 AM UTC 24
Finished Sep 04 03:01:57 AM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627191105 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.627191105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.4111203967
Short name T179
Test name
Test status
Simulation time 558742478 ps
CPU time 6.32 seconds
Started Sep 04 03:01:51 AM UTC 24
Finished Sep 04 03:01:59 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111203967 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.4111203967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.2532095894
Short name T940
Test name
Test status
Simulation time 507599336 ps
CPU time 10.24 seconds
Started Sep 04 03:01:55 AM UTC 24
Finished Sep 04 03:02:07 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532095894 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2532095894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3011166279
Short name T971
Test name
Test status
Simulation time 2955573819 ps
CPU time 17.07 seconds
Started Sep 04 03:01:55 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 216068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011166279 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3011166279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2445692957
Short name T921
Test name
Test status
Simulation time 42181033 ps
CPU time 1.8 seconds
Started Sep 04 03:01:54 AM UTC 24
Finished Sep 04 03:01:57 AM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445692957 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2445692957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.975840089
Short name T400
Test name
Test status
Simulation time 26636284 ps
CPU time 2.16 seconds
Started Sep 04 03:01:55 AM UTC 24
Finished Sep 04 03:01:59 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=975840089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_wi
th_rand_reset.975840089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.3288247517
Short name T399
Test name
Test status
Simulation time 29175058 ps
CPU time 1.11 seconds
Started Sep 04 03:01:55 AM UTC 24
Finished Sep 04 03:01:57 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288247517 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3288247517
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.2436679810
Short name T920
Test name
Test status
Simulation time 25317441 ps
CPU time 1.24 seconds
Started Sep 04 03:01:54 AM UTC 24
Finished Sep 04 03:01:56 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436679810 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2436679810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4133824382
Short name T120
Test name
Test status
Simulation time 46512787 ps
CPU time 1.65 seconds
Started Sep 04 03:01:55 AM UTC 24
Finished Sep 04 03:01:58 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133824382 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.4133824382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3029690423
Short name T94
Test name
Test status
Simulation time 151403479 ps
CPU time 3.55 seconds
Started Sep 04 03:01:54 AM UTC 24
Finished Sep 04 03:01:58 AM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029690423 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.3029690423
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1440121268
Short name T88
Test name
Test status
Simulation time 572479406 ps
CPU time 8.84 seconds
Started Sep 04 03:01:54 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440121268 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.1440121268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.2958287079
Short name T922
Test name
Test status
Simulation time 89508725 ps
CPU time 2.72 seconds
Started Sep 04 03:01:54 AM UTC 24
Finished Sep 04 03:01:58 AM UTC 24
Peak memory 226244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958287079 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2958287079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.521923154
Short name T396
Test name
Test status
Simulation time 60882974 ps
CPU time 2.62 seconds
Started Sep 04 03:01:54 AM UTC 24
Finished Sep 04 03:01:58 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521923154 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.521923154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1471117671
Short name T984
Test name
Test status
Simulation time 34133172 ps
CPU time 1.59 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:16 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1471117671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_
with_rand_reset.1471117671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.1239977981
Short name T982
Test name
Test status
Simulation time 38307974 ps
CPU time 1.31 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:16 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239977981 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1239977981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.1571992148
Short name T981
Test name
Test status
Simulation time 108549536 ps
CPU time 0.98 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:15 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571992148 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1571992148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.420901953
Short name T986
Test name
Test status
Simulation time 345919484 ps
CPU time 2.35 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:17 AM UTC 24
Peak memory 216172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420901953 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.420901953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.454890477
Short name T983
Test name
Test status
Simulation time 73929897 ps
CPU time 2.81 seconds
Started Sep 04 03:02:12 AM UTC 24
Finished Sep 04 03:02:16 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454890477 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.454890477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.56210495
Short name T1005
Test name
Test status
Simulation time 151532328 ps
CPU time 7.74 seconds
Started Sep 04 03:02:12 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56210495 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.56210495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.696378178
Short name T989
Test name
Test status
Simulation time 320586456 ps
CPU time 2.95 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:17 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696378178 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.696378178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3615925601
Short name T992
Test name
Test status
Simulation time 26468040 ps
CPU time 1.44 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:18 AM UTC 24
Peak memory 225872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3615925601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_
with_rand_reset.3615925601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.3869349715
Short name T991
Test name
Test status
Simulation time 18437120 ps
CPU time 1.29 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:18 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869349715 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3869349715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.160598860
Short name T988
Test name
Test status
Simulation time 58005729 ps
CPU time 0.79 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:17 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160598860 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.160598860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1515014928
Short name T1008
Test name
Test status
Simulation time 467415291 ps
CPU time 4.66 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515014928 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.1515014928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1134699174
Short name T1000
Test name
Test status
Simulation time 627661074 ps
CPU time 4.77 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:19 AM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134699174 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.1134699174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.527046006
Short name T997
Test name
Test status
Simulation time 150981311 ps
CPU time 4.23 seconds
Started Sep 04 03:02:13 AM UTC 24
Finished Sep 04 03:02:19 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527046006 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.527046006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.1807496030
Short name T985
Test name
Test status
Simulation time 46255043 ps
CPU time 1.85 seconds
Started Sep 04 03:02:14 AM UTC 24
Finished Sep 04 03:02:16 AM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807496030 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1807496030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.4018889081
Short name T188
Test name
Test status
Simulation time 1340089675 ps
CPU time 8.85 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:25 AM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018889081 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.4018889081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2419734563
Short name T995
Test name
Test status
Simulation time 17339295 ps
CPU time 1.85 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:19 AM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2419734563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_
with_rand_reset.2419734563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.2203759609
Short name T993
Test name
Test status
Simulation time 95446628 ps
CPU time 1.32 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:18 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203759609 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2203759609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.3954392130
Short name T990
Test name
Test status
Simulation time 11656459 ps
CPU time 0.83 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:17 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954392130 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3954392130
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3151138118
Short name T1011
Test name
Test status
Simulation time 465420001 ps
CPU time 4.62 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151138118 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.3151138118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2679677231
Short name T996
Test name
Test status
Simulation time 347570430 ps
CPU time 2.4 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:19 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679677231 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.2679677231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.291865333
Short name T1017
Test name
Test status
Simulation time 2670744530 ps
CPU time 6.18 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:23 AM UTC 24
Peak memory 226624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291865333 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.291865333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.1113177608
Short name T994
Test name
Test status
Simulation time 74066792 ps
CPU time 1.81 seconds
Started Sep 04 03:02:15 AM UTC 24
Finished Sep 04 03:02:18 AM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113177608 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1113177608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2748877430
Short name T1007
Test name
Test status
Simulation time 48033603 ps
CPU time 2.52 seconds
Started Sep 04 03:02:17 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 226304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2748877430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_
with_rand_reset.2748877430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.2786337365
Short name T1002
Test name
Test status
Simulation time 22720613 ps
CPU time 1.41 seconds
Started Sep 04 03:02:17 AM UTC 24
Finished Sep 04 03:02:20 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786337365 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2786337365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.3409991954
Short name T998
Test name
Test status
Simulation time 16087062 ps
CPU time 0.95 seconds
Started Sep 04 03:02:17 AM UTC 24
Finished Sep 04 03:02:19 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409991954 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3409991954
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.362353758
Short name T1004
Test name
Test status
Simulation time 36164538 ps
CPU time 2.16 seconds
Started Sep 04 03:02:17 AM UTC 24
Finished Sep 04 03:02:20 AM UTC 24
Peak memory 215964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362353758 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.362353758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2514064793
Short name T1001
Test name
Test status
Simulation time 274492861 ps
CPU time 2.8 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:20 AM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514064793 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.2514064793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3831216282
Short name T1076
Test name
Test status
Simulation time 643513892 ps
CPU time 16.8 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831216282 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.3831216282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.3335714367
Short name T1003
Test name
Test status
Simulation time 526794084 ps
CPU time 3.3 seconds
Started Sep 04 03:02:16 AM UTC 24
Finished Sep 04 03:02:20 AM UTC 24
Peak memory 226460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335714367 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3335714367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1623671389
Short name T1012
Test name
Test status
Simulation time 36271750 ps
CPU time 1.52 seconds
Started Sep 04 03:02:19 AM UTC 24
Finished Sep 04 03:02:22 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1623671389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_
with_rand_reset.1623671389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.3180690803
Short name T1010
Test name
Test status
Simulation time 121312218 ps
CPU time 1.34 seconds
Started Sep 04 03:02:19 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180690803 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3180690803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.4132003209
Short name T1009
Test name
Test status
Simulation time 33752038 ps
CPU time 1.13 seconds
Started Sep 04 03:02:19 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132003209 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4132003209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2350288563
Short name T1013
Test name
Test status
Simulation time 45703687 ps
CPU time 1.91 seconds
Started Sep 04 03:02:19 AM UTC 24
Finished Sep 04 03:02:22 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350288563 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.2350288563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4048345594
Short name T1006
Test name
Test status
Simulation time 157049338 ps
CPU time 2.41 seconds
Started Sep 04 03:02:17 AM UTC 24
Finished Sep 04 03:02:21 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048345594 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.4048345594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.793579079
Short name T1016
Test name
Test status
Simulation time 81721749 ps
CPU time 3.93 seconds
Started Sep 04 03:02:18 AM UTC 24
Finished Sep 04 03:02:23 AM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793579079 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.793579079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1393542806
Short name T1015
Test name
Test status
Simulation time 64721621 ps
CPU time 2.28 seconds
Started Sep 04 03:02:19 AM UTC 24
Finished Sep 04 03:02:22 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393542806 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1393542806
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.3119686436
Short name T187
Test name
Test status
Simulation time 127178923 ps
CPU time 3.86 seconds
Started Sep 04 03:02:19 AM UTC 24
Finished Sep 04 03:02:24 AM UTC 24
Peak memory 226348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119686436 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.3119686436
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1449981681
Short name T1022
Test name
Test status
Simulation time 81390086 ps
CPU time 2.11 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:24 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1449981681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_
with_rand_reset.1449981681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.2383825946
Short name T1021
Test name
Test status
Simulation time 29798202 ps
CPU time 1.51 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:24 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383825946 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2383825946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.4060771105
Short name T1018
Test name
Test status
Simulation time 13036278 ps
CPU time 0.92 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:23 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060771105 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4060771105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1754960946
Short name T1026
Test name
Test status
Simulation time 175358022 ps
CPU time 2.67 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:25 AM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754960946 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.1754960946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3791716460
Short name T1014
Test name
Test status
Simulation time 64937936 ps
CPU time 1.98 seconds
Started Sep 04 03:02:19 AM UTC 24
Finished Sep 04 03:02:22 AM UTC 24
Peak memory 226192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791716460 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.3791716460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1839889285
Short name T1059
Test name
Test status
Simulation time 306334852 ps
CPU time 8.21 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839889285 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.1839889285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3695054918
Short name T1024
Test name
Test status
Simulation time 127043825 ps
CPU time 2.64 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:25 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695054918 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3695054918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.1009775739
Short name T170
Test name
Test status
Simulation time 118571641 ps
CPU time 4.14 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:26 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009775739 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.1009775739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3176922077
Short name T1030
Test name
Test status
Simulation time 21616862 ps
CPU time 1.46 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:25 AM UTC 24
Peak memory 226280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3176922077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_
with_rand_reset.3176922077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.581730026
Short name T1020
Test name
Test status
Simulation time 51156068 ps
CPU time 1.06 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:23 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581730026 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.581730026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.645504079
Short name T1019
Test name
Test status
Simulation time 17241156 ps
CPU time 0.98 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:23 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645504079 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.645504079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2991903543
Short name T1028
Test name
Test status
Simulation time 96833194 ps
CPU time 2.65 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:25 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991903543 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.2991903543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1319523444
Short name T1027
Test name
Test status
Simulation time 275356801 ps
CPU time 2.62 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:25 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319523444 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.1319523444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3954620943
Short name T1082
Test name
Test status
Simulation time 1663498302 ps
CPU time 14.56 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:37 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954620943 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.3954620943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.4027491954
Short name T1023
Test name
Test status
Simulation time 544997097 ps
CPU time 2.1 seconds
Started Sep 04 03:02:21 AM UTC 24
Finished Sep 04 03:02:24 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027491954 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4027491954
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3592319163
Short name T987
Test name
Test status
Simulation time 122614001 ps
CPU time 1.52 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:26 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3592319163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_
with_rand_reset.3592319163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.1811175803
Short name T1031
Test name
Test status
Simulation time 19415890 ps
CPU time 1.33 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:26 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811175803 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1811175803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.445543122
Short name T1029
Test name
Test status
Simulation time 11628047 ps
CPU time 1.04 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:25 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445543122 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.445543122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4076424675
Short name T1034
Test name
Test status
Simulation time 36391340 ps
CPU time 1.62 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:26 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076424675 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.4076424675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.801204237
Short name T1033
Test name
Test status
Simulation time 102411208 ps
CPU time 1.9 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:26 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801204237 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.801204237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.981258309
Short name T1062
Test name
Test status
Simulation time 345042392 ps
CPU time 6.73 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:31 AM UTC 24
Peak memory 226676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981258309 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.981258309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.586118852
Short name T1025
Test name
Test status
Simulation time 197035421 ps
CPU time 2.34 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:26 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586118852 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.586118852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3708449596
Short name T1040
Test name
Test status
Simulation time 114424089 ps
CPU time 1.77 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:28 AM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3708449596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_
with_rand_reset.3708449596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.1698851400
Short name T1035
Test name
Test status
Simulation time 11493321 ps
CPU time 1.03 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:27 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698851400 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1698851400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.105722070
Short name T1037
Test name
Test status
Simulation time 100429825 ps
CPU time 0.85 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:27 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105722070 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.105722070
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2544584613
Short name T1058
Test name
Test status
Simulation time 315975985 ps
CPU time 3.85 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 215940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544584613 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.2544584613
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3337820426
Short name T1036
Test name
Test status
Simulation time 84729646 ps
CPU time 2.35 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:27 AM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337820426 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.3337820426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2596057876
Short name T1044
Test name
Test status
Simulation time 119614377 ps
CPU time 4.89 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:29 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596057876 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.2596057876
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.3821519875
Short name T1042
Test name
Test status
Simulation time 692155068 ps
CPU time 4.81 seconds
Started Sep 04 03:02:23 AM UTC 24
Finished Sep 04 03:02:29 AM UTC 24
Peak memory 228244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821519875 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3821519875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.1058996470
Short name T171
Test name
Test status
Simulation time 278995926 ps
CPU time 4.45 seconds
Started Sep 04 03:02:24 AM UTC 24
Finished Sep 04 03:02:29 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058996470 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.1058996470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4037959606
Short name T1061
Test name
Test status
Simulation time 53938275 ps
CPU time 1.87 seconds
Started Sep 04 03:02:27 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4037959606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_
with_rand_reset.4037959606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.4127183594
Short name T1039
Test name
Test status
Simulation time 24451112 ps
CPU time 1.12 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:28 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127183594 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4127183594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1208525273
Short name T1038
Test name
Test status
Simulation time 39890387 ps
CPU time 0.76 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:27 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208525273 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1208525273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4055894168
Short name T1051
Test name
Test status
Simulation time 21933499 ps
CPU time 1.55 seconds
Started Sep 04 03:02:27 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055894168 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.4055894168
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3091019752
Short name T1047
Test name
Test status
Simulation time 129516014 ps
CPU time 3.37 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091019752 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.3091019752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2574981935
Short name T1083
Test name
Test status
Simulation time 415428555 ps
CPU time 13.3 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:40 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574981935 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.2574981935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3890816309
Short name T1063
Test name
Test status
Simulation time 1159009749 ps
CPU time 4.5 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:31 AM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890816309 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3890816309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.1696359343
Short name T1081
Test name
Test status
Simulation time 2485098568 ps
CPU time 8.74 seconds
Started Sep 04 03:02:25 AM UTC 24
Finished Sep 04 03:02:35 AM UTC 24
Peak memory 216236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696359343 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.1696359343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.253879616
Short name T125
Test name
Test status
Simulation time 310486993 ps
CPU time 4.77 seconds
Started Sep 04 03:01:58 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253879616 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.253879616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3405988094
Short name T944
Test name
Test status
Simulation time 1398371045 ps
CPU time 9.56 seconds
Started Sep 04 03:01:57 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405988094 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3405988094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1240523052
Short name T924
Test name
Test status
Simulation time 56472889 ps
CPU time 1.34 seconds
Started Sep 04 03:01:57 AM UTC 24
Finished Sep 04 03:01:59 AM UTC 24
Peak memory 213656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240523052 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1240523052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2618179699
Short name T926
Test name
Test status
Simulation time 186018580 ps
CPU time 1.42 seconds
Started Sep 04 03:01:58 AM UTC 24
Finished Sep 04 03:02:01 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2618179699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w
ith_rand_reset.2618179699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.2299141754
Short name T925
Test name
Test status
Simulation time 22510644 ps
CPU time 1.58 seconds
Started Sep 04 03:01:57 AM UTC 24
Finished Sep 04 03:02:00 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299141754 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2299141754
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.3783610992
Short name T923
Test name
Test status
Simulation time 19241670 ps
CPU time 1.22 seconds
Started Sep 04 03:01:57 AM UTC 24
Finished Sep 04 03:01:59 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783610992 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3783610992
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.986983313
Short name T122
Test name
Test status
Simulation time 86141475 ps
CPU time 2.18 seconds
Started Sep 04 03:01:58 AM UTC 24
Finished Sep 04 03:02:01 AM UTC 24
Peak memory 215952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986983313 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.986983313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.970650323
Short name T963
Test name
Test status
Simulation time 463665938 ps
CPU time 15.56 seconds
Started Sep 04 03:01:56 AM UTC 24
Finished Sep 04 03:02:12 AM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970650323 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.970650323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.2310887298
Short name T201
Test name
Test status
Simulation time 121692387 ps
CPU time 3.08 seconds
Started Sep 04 03:01:56 AM UTC 24
Finished Sep 04 03:02:00 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310887298 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2310887298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.1436786181
Short name T183
Test name
Test status
Simulation time 144625685 ps
CPU time 5.44 seconds
Started Sep 04 03:01:56 AM UTC 24
Finished Sep 04 03:02:02 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436786181 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.1436786181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1801900816
Short name T1041
Test name
Test status
Simulation time 34852738 ps
CPU time 0.98 seconds
Started Sep 04 03:02:27 AM UTC 24
Finished Sep 04 03:02:29 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801900816 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1801900816
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2355641630
Short name T1043
Test name
Test status
Simulation time 20823506 ps
CPU time 0.93 seconds
Started Sep 04 03:02:27 AM UTC 24
Finished Sep 04 03:02:29 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355641630 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2355641630
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.2409356586
Short name T1045
Test name
Test status
Simulation time 15294694 ps
CPU time 0.99 seconds
Started Sep 04 03:02:27 AM UTC 24
Finished Sep 04 03:02:29 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409356586 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2409356586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.2954480652
Short name T1056
Test name
Test status
Simulation time 14644881 ps
CPU time 1.33 seconds
Started Sep 04 03:02:27 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954480652 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2954480652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.1008950578
Short name T1048
Test name
Test status
Simulation time 38332760 ps
CPU time 1.06 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008950578 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1008950578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.4129104438
Short name T1046
Test name
Test status
Simulation time 30564247 ps
CPU time 0.93 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129104438 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4129104438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.1674562299
Short name T1054
Test name
Test status
Simulation time 10698865 ps
CPU time 1.12 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674562299 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1674562299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.1005915939
Short name T1049
Test name
Test status
Simulation time 13404716 ps
CPU time 0.96 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005915939 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1005915939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.2957264173
Short name T1050
Test name
Test status
Simulation time 51198674 ps
CPU time 0.91 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957264173 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2957264173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.131492722
Short name T1052
Test name
Test status
Simulation time 11979760 ps
CPU time 1.01 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131492722 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.131492722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.1137298102
Short name T941
Test name
Test status
Simulation time 99538345 ps
CPU time 6.18 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:07 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137298102 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1137298102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.622240146
Short name T952
Test name
Test status
Simulation time 1446867281 ps
CPU time 8.57 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:10 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622240146 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.622240146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3848626708
Short name T928
Test name
Test status
Simulation time 55193691 ps
CPU time 1.65 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:02 AM UTC 24
Peak memory 213128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848626708 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3848626708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4061981555
Short name T929
Test name
Test status
Simulation time 29556393 ps
CPU time 1.54 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:03 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4061981555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w
ith_rand_reset.4061981555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.1145593791
Short name T123
Test name
Test status
Simulation time 89278259 ps
CPU time 1.75 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:03 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145593791 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1145593791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.3930773462
Short name T927
Test name
Test status
Simulation time 44686142 ps
CPU time 1.17 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:02 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930773462 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3930773462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1981756834
Short name T935
Test name
Test status
Simulation time 487259567 ps
CPU time 4.83 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:06 AM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981756834 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.1981756834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2649070077
Short name T97
Test name
Test status
Simulation time 74498942 ps
CPU time 2.17 seconds
Started Sep 04 03:01:58 AM UTC 24
Finished Sep 04 03:02:02 AM UTC 24
Peak memory 226496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649070077 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.2649070077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4149463196
Short name T964
Test name
Test status
Simulation time 1312031738 ps
CPU time 12.82 seconds
Started Sep 04 03:01:58 AM UTC 24
Finished Sep 04 03:02:12 AM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149463196 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.4149463196
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.3486720661
Short name T930
Test name
Test status
Simulation time 152083497 ps
CPU time 3.67 seconds
Started Sep 04 03:01:58 AM UTC 24
Finished Sep 04 03:02:03 AM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486720661 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3486720661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2756183559
Short name T1053
Test name
Test status
Simulation time 14406377 ps
CPU time 0.96 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756183559 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2756183559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.1852680984
Short name T1057
Test name
Test status
Simulation time 30803288 ps
CPU time 1.02 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852680984 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1852680984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.1339406595
Short name T1055
Test name
Test status
Simulation time 23212082 ps
CPU time 0.87 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339406595 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1339406595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.787752796
Short name T1060
Test name
Test status
Simulation time 14058920 ps
CPU time 1.1 seconds
Started Sep 04 03:02:28 AM UTC 24
Finished Sep 04 03:02:30 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787752796 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.787752796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.1678816184
Short name T1066
Test name
Test status
Simulation time 51506645 ps
CPU time 1 seconds
Started Sep 04 03:02:29 AM UTC 24
Finished Sep 04 03:02:31 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678816184 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1678816184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.727315310
Short name T1065
Test name
Test status
Simulation time 13869966 ps
CPU time 0.99 seconds
Started Sep 04 03:02:29 AM UTC 24
Finished Sep 04 03:02:31 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727315310 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.727315310
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.137575368
Short name T1067
Test name
Test status
Simulation time 28357889 ps
CPU time 1.04 seconds
Started Sep 04 03:02:29 AM UTC 24
Finished Sep 04 03:02:31 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137575368 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.137575368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.4211383511
Short name T1064
Test name
Test status
Simulation time 9001815 ps
CPU time 0.72 seconds
Started Sep 04 03:02:29 AM UTC 24
Finished Sep 04 03:02:31 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211383511 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4211383511
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.3893404481
Short name T1070
Test name
Test status
Simulation time 11877706 ps
CPU time 0.9 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893404481 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3893404481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2830285076
Short name T1068
Test name
Test status
Simulation time 9919798 ps
CPU time 0.65 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:33 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830285076 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2830285076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.1601682432
Short name T976
Test name
Test status
Simulation time 1647370295 ps
CPU time 10.02 seconds
Started Sep 04 03:02:03 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601682432 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1601682432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.32122435
Short name T973
Test name
Test status
Simulation time 661582952 ps
CPU time 9.74 seconds
Started Sep 04 03:02:03 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 215936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32122435 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.32122435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3568257476
Short name T932
Test name
Test status
Simulation time 59199691 ps
CPU time 1.29 seconds
Started Sep 04 03:02:02 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 213128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568257476 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3568257476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1365331343
Short name T936
Test name
Test status
Simulation time 18622615 ps
CPU time 2.06 seconds
Started Sep 04 03:02:03 AM UTC 24
Finished Sep 04 03:02:06 AM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1365331343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_w
ith_rand_reset.1365331343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.3322382013
Short name T124
Test name
Test status
Simulation time 30844390 ps
CPU time 1.35 seconds
Started Sep 04 03:02:02 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322382013 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3322382013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.3345200440
Short name T931
Test name
Test status
Simulation time 12433983 ps
CPU time 1.17 seconds
Started Sep 04 03:02:01 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345200440 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3345200440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3601012146
Short name T938
Test name
Test status
Simulation time 41580086 ps
CPU time 2.55 seconds
Started Sep 04 03:02:03 AM UTC 24
Finished Sep 04 03:02:07 AM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601012146 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.3601012146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1758854135
Short name T95
Test name
Test status
Simulation time 807208969 ps
CPU time 3.09 seconds
Started Sep 04 03:02:00 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758854135 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.1758854135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3204203186
Short name T949
Test name
Test status
Simulation time 188856886 ps
CPU time 6.29 seconds
Started Sep 04 03:02:01 AM UTC 24
Finished Sep 04 03:02:09 AM UTC 24
Peak memory 232680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204203186 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.3204203186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.655314713
Short name T933
Test name
Test status
Simulation time 37344325 ps
CPU time 1.9 seconds
Started Sep 04 03:02:01 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655314713 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.655314713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.1700088585
Short name T1069
Test name
Test status
Simulation time 42937082 ps
CPU time 0.79 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:33 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700088585 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1700088585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.439377864
Short name T1073
Test name
Test status
Simulation time 37899979 ps
CPU time 0.87 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439377864 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.439377864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.986620125
Short name T1071
Test name
Test status
Simulation time 12793059 ps
CPU time 0.75 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986620125 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.986620125
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.3559436201
Short name T1072
Test name
Test status
Simulation time 11444688 ps
CPU time 0.75 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559436201 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3559436201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.3557218917
Short name T1074
Test name
Test status
Simulation time 45643432 ps
CPU time 0.8 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557218917 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3557218917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.3354843546
Short name T1077
Test name
Test status
Simulation time 17747088 ps
CPU time 0.95 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354843546 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3354843546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.4254272855
Short name T1078
Test name
Test status
Simulation time 11664589 ps
CPU time 0.9 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254272855 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4254272855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.1222863433
Short name T1075
Test name
Test status
Simulation time 21160729 ps
CPU time 0.83 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222863433 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1222863433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.1923716550
Short name T1079
Test name
Test status
Simulation time 8528056 ps
CPU time 0.83 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923716550 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1923716550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.2702327981
Short name T1080
Test name
Test status
Simulation time 33161080 ps
CPU time 0.81 seconds
Started Sep 04 03:02:32 AM UTC 24
Finished Sep 04 03:02:34 AM UTC 24
Peak memory 213580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702327981 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2702327981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1211964600
Short name T947
Test name
Test status
Simulation time 104765056 ps
CPU time 1.68 seconds
Started Sep 04 03:02:06 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1211964600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w
ith_rand_reset.1211964600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.291260283
Short name T939
Test name
Test status
Simulation time 41824013 ps
CPU time 1.36 seconds
Started Sep 04 03:02:04 AM UTC 24
Finished Sep 04 03:02:07 AM UTC 24
Peak memory 213640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291260283 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.291260283
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.2383247292
Short name T937
Test name
Test status
Simulation time 15382678 ps
CPU time 0.99 seconds
Started Sep 04 03:02:04 AM UTC 24
Finished Sep 04 03:02:06 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383247292 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2383247292
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.338414139
Short name T943
Test name
Test status
Simulation time 37377999 ps
CPU time 2.5 seconds
Started Sep 04 03:02:04 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338414139 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.338414139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2730033632
Short name T96
Test name
Test status
Simulation time 80498150 ps
CPU time 2.53 seconds
Started Sep 04 03:02:03 AM UTC 24
Finished Sep 04 03:02:07 AM UTC 24
Peak memory 226496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730033632 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.2730033632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.401671037
Short name T954
Test name
Test status
Simulation time 651587206 ps
CPU time 4.8 seconds
Started Sep 04 03:02:04 AM UTC 24
Finished Sep 04 03:02:10 AM UTC 24
Peak memory 232948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401671037 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.401671037
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.573249677
Short name T942
Test name
Test status
Simulation time 51288126 ps
CPU time 2.53 seconds
Started Sep 04 03:02:04 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573249677 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.573249677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3787775971
Short name T951
Test name
Test status
Simulation time 45054616 ps
CPU time 1.57 seconds
Started Sep 04 03:02:07 AM UTC 24
Finished Sep 04 03:02:10 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3787775971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w
ith_rand_reset.3787775971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.3544196385
Short name T945
Test name
Test status
Simulation time 88277379 ps
CPU time 1.18 seconds
Started Sep 04 03:02:06 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 213120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544196385 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3544196385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.4225157674
Short name T946
Test name
Test status
Simulation time 23072791 ps
CPU time 1.27 seconds
Started Sep 04 03:02:06 AM UTC 24
Finished Sep 04 03:02:08 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225157674 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4225157674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2641280376
Short name T953
Test name
Test status
Simulation time 107290645 ps
CPU time 1.76 seconds
Started Sep 04 03:02:07 AM UTC 24
Finished Sep 04 03:02:10 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641280376 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.2641280376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1882733920
Short name T955
Test name
Test status
Simulation time 173277390 ps
CPU time 3.57 seconds
Started Sep 04 03:02:06 AM UTC 24
Finished Sep 04 03:02:10 AM UTC 24
Peak memory 226496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882733920 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.1882733920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3994595282
Short name T967
Test name
Test status
Simulation time 212298146 ps
CPU time 6.09 seconds
Started Sep 04 03:02:06 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 232560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994595282 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.3994595282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.4021725218
Short name T950
Test name
Test status
Simulation time 263733620 ps
CPU time 2.33 seconds
Started Sep 04 03:02:06 AM UTC 24
Finished Sep 04 03:02:09 AM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021725218 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4021725218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.1831099696
Short name T181
Test name
Test status
Simulation time 1729932093 ps
CPU time 6.21 seconds
Started Sep 04 03:02:06 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831099696 -assert nopostproc +UVM_TESTN
AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.1831099696
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2756744240
Short name T958
Test name
Test status
Simulation time 255185874 ps
CPU time 1.87 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:11 AM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2756744240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_w
ith_rand_reset.2756744240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.2388062666
Short name T957
Test name
Test status
Simulation time 15759034 ps
CPU time 1.3 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:11 AM UTC 24
Peak memory 213200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388062666 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2388062666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.349981561
Short name T956
Test name
Test status
Simulation time 92563722 ps
CPU time 1.26 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:11 AM UTC 24
Peak memory 212472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349981561 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.349981561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4227766065
Short name T966
Test name
Test status
Simulation time 1242989520 ps
CPU time 3.01 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 215604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227766065 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.4227766065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.372328307
Short name T962
Test name
Test status
Simulation time 108294228 ps
CPU time 4.15 seconds
Started Sep 04 03:02:07 AM UTC 24
Finished Sep 04 03:02:12 AM UTC 24
Peak memory 226552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372328307 -assert nopostproc +UVM_
TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.372328307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3324918035
Short name T961
Test name
Test status
Simulation time 154861827 ps
CPU time 3.58 seconds
Started Sep 04 03:02:07 AM UTC 24
Finished Sep 04 03:02:12 AM UTC 24
Peak memory 226680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324918035 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.3324918035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.3922508765
Short name T959
Test name
Test status
Simulation time 183944973 ps
CPU time 3.26 seconds
Started Sep 04 03:02:07 AM UTC 24
Finished Sep 04 03:02:11 AM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922508765 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3922508765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1315881976
Short name T968
Test name
Test status
Simulation time 49549532 ps
CPU time 1.79 seconds
Started Sep 04 03:02:10 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 223824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1315881976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w
ith_rand_reset.1315881976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.1892869988
Short name T960
Test name
Test status
Simulation time 25594116 ps
CPU time 1.64 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:12 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892869988 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1892869988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.4169957404
Short name T948
Test name
Test status
Simulation time 41021155 ps
CPU time 0.99 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:11 AM UTC 24
Peak memory 213044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169957404 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4169957404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3072764451
Short name T970
Test name
Test status
Simulation time 142126404 ps
CPU time 3.32 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 216044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072764451 -assert nopostproc +
UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.3072764451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3794118957
Short name T980
Test name
Test status
Simulation time 873822416 ps
CPU time 4.99 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:15 AM UTC 24
Peak memory 226624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794118957 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.3794118957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1024701847
Short name T999
Test name
Test status
Simulation time 482881162 ps
CPU time 9.18 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:19 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024701847 -assert nop
ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.1024701847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.2051806258
Short name T969
Test name
Test status
Simulation time 36674932 ps
CPU time 3.19 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 228004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051806258 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2051806258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.352132516
Short name T977
Test name
Test status
Simulation time 1351977301 ps
CPU time 4.15 seconds
Started Sep 04 03:02:09 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352132516 -assert nopostproc +UVM_TESTNA
ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.352132516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.446435750
Short name T978
Test name
Test status
Simulation time 50602834 ps
CPU time 1.5 seconds
Started Sep 04 03:02:12 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 213588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=446435750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_wi
th_rand_reset.446435750
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.3624580570
Short name T975
Test name
Test status
Simulation time 24654309 ps
CPU time 1.3 seconds
Started Sep 04 03:02:12 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 213084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624580570 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3624580570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.731866182
Short name T965
Test name
Test status
Simulation time 34184442 ps
CPU time 1.05 seconds
Started Sep 04 03:02:10 AM UTC 24
Finished Sep 04 03:02:13 AM UTC 24
Peak memory 213584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731866182 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.731866182
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.693813632
Short name T979
Test name
Test status
Simulation time 51037530 ps
CPU time 1.75 seconds
Started Sep 04 03:02:12 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 213548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693813632 -assert nopostproc +U
VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.693813632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1751360971
Short name T974
Test name
Test status
Simulation time 291667714 ps
CPU time 2.34 seconds
Started Sep 04 03:02:10 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751360971 -assert nopostproc +UVM
_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.1751360971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.386249128
Short name T1032
Test name
Test status
Simulation time 448753318 ps
CPU time 14.25 seconds
Started Sep 04 03:02:10 AM UTC 24
Finished Sep 04 03:02:26 AM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386249128 -assert nopo
stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.386249128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.3066952161
Short name T972
Test name
Test status
Simulation time 30951212 ps
CPU time 2.2 seconds
Started Sep 04 03:02:10 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066952161 -assert nopostproc +UVM_TESTNAME=keymgr_b
ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3066952161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.179193039
Short name T2
Test name
Test status
Simulation time 102422891 ps
CPU time 3.29 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:56:54 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179193039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.179193039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.1429766791
Short name T3
Test name
Test status
Simulation time 233951724 ps
CPU time 3.34 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:56:54 AM UTC 24
Peak memory 213800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429766791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1429766791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_random.456617484
Short name T27
Test name
Test status
Simulation time 534955979 ps
CPU time 8.73 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:57:00 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456617484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.456617484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.125649424
Short name T16
Test name
Test status
Simulation time 241669976 ps
CPU time 7.07 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:56:58 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125649424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.125649424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.349387228
Short name T4
Test name
Test status
Simulation time 146594914 ps
CPU time 5.25 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:56:56 AM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349387228 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.349387228
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.4057715454
Short name T37
Test name
Test status
Simulation time 728407234 ps
CPU time 7.97 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:56:59 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057715454 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4057715454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.731440798
Short name T18
Test name
Test status
Simulation time 439014596 ps
CPU time 4.31 seconds
Started Sep 04 02:56:53 AM UTC 24
Finished Sep 04 02:56:59 AM UTC 24
Peak memory 218240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731440798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.731440798
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.3202212456
Short name T1
Test name
Test status
Simulation time 146332195 ps
CPU time 2.78 seconds
Started Sep 04 02:56:50 AM UTC 24
Finished Sep 04 02:56:54 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202212456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3202212456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/0.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.2620995623
Short name T65
Test name
Test status
Simulation time 11238704 ps
CPU time 0.82 seconds
Started Sep 04 02:57:03 AM UTC 24
Finished Sep 04 02:57:04 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620995623 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2620995623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.438468759
Short name T111
Test name
Test status
Simulation time 157302438 ps
CPU time 3.18 seconds
Started Sep 04 02:56:59 AM UTC 24
Finished Sep 04 02:57:03 AM UTC 24
Peak memory 227996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438468759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.438468759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.3975546884
Short name T70
Test name
Test status
Simulation time 358162416 ps
CPU time 3.79 seconds
Started Sep 04 02:56:59 AM UTC 24
Finished Sep 04 02:57:04 AM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975546884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3975546884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.3239546928
Short name T13
Test name
Test status
Simulation time 837559522 ps
CPU time 9.48 seconds
Started Sep 04 02:57:03 AM UTC 24
Finished Sep 04 02:57:13 AM UTC 24
Peak memory 252212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239546928 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3239546928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.1980337911
Short name T38
Test name
Test status
Simulation time 51470361 ps
CPU time 3.35 seconds
Started Sep 04 02:56:54 AM UTC 24
Finished Sep 04 02:56:59 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980337911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1980337911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.1408744745
Short name T48
Test name
Test status
Simulation time 89767367 ps
CPU time 4.21 seconds
Started Sep 04 02:56:55 AM UTC 24
Finished Sep 04 02:57:01 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408744745 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1408744745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.4271753974
Short name T109
Test name
Test status
Simulation time 193884157 ps
CPU time 3.9 seconds
Started Sep 04 02:56:57 AM UTC 24
Finished Sep 04 02:57:02 AM UTC 24
Peak memory 215852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271753974 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4271753974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.575896848
Short name T165
Test name
Test status
Simulation time 61314066 ps
CPU time 2.62 seconds
Started Sep 04 02:57:00 AM UTC 24
Finished Sep 04 02:57:04 AM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575896848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.575896848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.3888782929
Short name T108
Test name
Test status
Simulation time 127633943 ps
CPU time 5.43 seconds
Started Sep 04 02:56:54 AM UTC 24
Finished Sep 04 02:57:01 AM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888782929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3888782929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.4122920619
Short name T342
Test name
Test status
Simulation time 6952476020 ps
CPU time 67.28 seconds
Started Sep 04 02:57:00 AM UTC 24
Finished Sep 04 02:58:09 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122920619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4122920619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.3970482108
Short name T449
Test name
Test status
Simulation time 12400295 ps
CPU time 1.21 seconds
Started Sep 04 02:58:09 AM UTC 24
Finished Sep 04 02:58:12 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970482108 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3970482108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.683827578
Short name T355
Test name
Test status
Simulation time 396524783 ps
CPU time 3.07 seconds
Started Sep 04 02:58:07 AM UTC 24
Finished Sep 04 02:58:11 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683827578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.683827578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.974687406
Short name T256
Test name
Test status
Simulation time 170760908 ps
CPU time 2.66 seconds
Started Sep 04 02:58:08 AM UTC 24
Finished Sep 04 02:58:12 AM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974687406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.974687406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_random.431207889
Short name T281
Test name
Test status
Simulation time 351316713 ps
CPU time 5.98 seconds
Started Sep 04 02:58:07 AM UTC 24
Finished Sep 04 02:58:14 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431207889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.431207889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.3096044246
Short name T262
Test name
Test status
Simulation time 33317708 ps
CPU time 3.26 seconds
Started Sep 04 02:58:06 AM UTC 24
Finished Sep 04 02:58:11 AM UTC 24
Peak memory 217900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096044246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3096044246
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.2891501994
Short name T345
Test name
Test status
Simulation time 80631005 ps
CPU time 3.95 seconds
Started Sep 04 02:58:07 AM UTC 24
Finished Sep 04 02:58:12 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891501994 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2891501994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.3739794672
Short name T364
Test name
Test status
Simulation time 83879179 ps
CPU time 2.95 seconds
Started Sep 04 02:58:07 AM UTC 24
Finished Sep 04 02:58:10 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739794672 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3739794672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.1766905494
Short name T448
Test name
Test status
Simulation time 21100517 ps
CPU time 2.49 seconds
Started Sep 04 02:58:07 AM UTC 24
Finished Sep 04 02:58:10 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766905494 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1766905494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.3944159456
Short name T263
Test name
Test status
Simulation time 91478093 ps
CPU time 2.6 seconds
Started Sep 04 02:58:08 AM UTC 24
Finished Sep 04 02:58:12 AM UTC 24
Peak memory 230676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944159456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3944159456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.3062044417
Short name T450
Test name
Test status
Simulation time 331522520 ps
CPU time 6.36 seconds
Started Sep 04 02:58:06 AM UTC 24
Finished Sep 04 02:58:14 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062044417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3062044417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.3089166812
Short name T451
Test name
Test status
Simulation time 1273132488 ps
CPU time 5.1 seconds
Started Sep 04 02:58:08 AM UTC 24
Finished Sep 04 02:58:14 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089166812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3089166812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.4057457892
Short name T454
Test name
Test status
Simulation time 44279354 ps
CPU time 1.39 seconds
Started Sep 04 02:58:17 AM UTC 24
Finished Sep 04 02:58:19 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057457892 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.4057457892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.164051200
Short name T452
Test name
Test status
Simulation time 41071549 ps
CPU time 2.56 seconds
Started Sep 04 02:58:13 AM UTC 24
Finished Sep 04 02:58:17 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164051200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.164051200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.1586454054
Short name T49
Test name
Test status
Simulation time 102966858 ps
CPU time 2.5 seconds
Started Sep 04 02:58:14 AM UTC 24
Finished Sep 04 02:58:18 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586454054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1586454054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.169806333
Short name T79
Test name
Test status
Simulation time 91561533 ps
CPU time 4.52 seconds
Started Sep 04 02:58:14 AM UTC 24
Finished Sep 04 02:58:20 AM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169806333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.169806333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.2435493923
Short name T115
Test name
Test status
Simulation time 745512335 ps
CPU time 4.56 seconds
Started Sep 04 02:58:13 AM UTC 24
Finished Sep 04 02:58:19 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435493923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2435493923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_random.3130985937
Short name T299
Test name
Test status
Simulation time 318165102 ps
CPU time 4.2 seconds
Started Sep 04 02:58:13 AM UTC 24
Finished Sep 04 02:58:18 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130985937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3130985937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.164064107
Short name T286
Test name
Test status
Simulation time 125472825 ps
CPU time 3.36 seconds
Started Sep 04 02:58:12 AM UTC 24
Finished Sep 04 02:58:16 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164064107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.164064107
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.2038615737
Short name T416
Test name
Test status
Simulation time 220393758 ps
CPU time 2.5 seconds
Started Sep 04 02:58:12 AM UTC 24
Finished Sep 04 02:58:15 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038615737 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2038615737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.4219132643
Short name T455
Test name
Test status
Simulation time 575492612 ps
CPU time 7.43 seconds
Started Sep 04 02:58:12 AM UTC 24
Finished Sep 04 02:58:20 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219132643 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4219132643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.4162575671
Short name T453
Test name
Test status
Simulation time 71903110 ps
CPU time 4.51 seconds
Started Sep 04 02:58:12 AM UTC 24
Finished Sep 04 02:58:17 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162575671 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4162575671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.2124695
Short name T252
Test name
Test status
Simulation time 73954751 ps
CPU time 3.41 seconds
Started Sep 04 02:58:16 AM UTC 24
Finished Sep 04 02:58:20 AM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2124695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.3784395531
Short name T409
Test name
Test status
Simulation time 147007578 ps
CPU time 4.68 seconds
Started Sep 04 02:58:11 AM UTC 24
Finished Sep 04 02:58:16 AM UTC 24
Peak memory 217820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784395531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3784395531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.1224536165
Short name T427
Test name
Test status
Simulation time 530881850 ps
CPU time 12.63 seconds
Started Sep 04 02:58:17 AM UTC 24
Finished Sep 04 02:58:31 AM UTC 24
Peak memory 220260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224536165 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1224536165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all_with_rand_reset.1864391057
Short name T89
Test name
Test status
Simulation time 361363894 ps
CPU time 13.44 seconds
Started Sep 04 02:58:17 AM UTC 24
Finished Sep 04 02:58:31 AM UTC 24
Peak memory 231292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1864391057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymg
r_stress_all_with_rand_reset.1864391057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.2669257666
Short name T403
Test name
Test status
Simulation time 337128419 ps
CPU time 5.36 seconds
Started Sep 04 02:58:13 AM UTC 24
Finished Sep 04 02:58:20 AM UTC 24
Peak memory 218208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669257666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2669257666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.811806877
Short name T456
Test name
Test status
Simulation time 217865736 ps
CPU time 3.74 seconds
Started Sep 04 02:58:16 AM UTC 24
Finished Sep 04 02:58:20 AM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811806877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.811806877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.3080270403
Short name T459
Test name
Test status
Simulation time 12043645 ps
CPU time 1.12 seconds
Started Sep 04 02:58:22 AM UTC 24
Finished Sep 04 02:58:24 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080270403 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3080270403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.2630168030
Short name T148
Test name
Test status
Simulation time 90168820 ps
CPU time 4.68 seconds
Started Sep 04 02:58:21 AM UTC 24
Finished Sep 04 02:58:27 AM UTC 24
Peak memory 232588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630168030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2630168030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.3781637223
Short name T149
Test name
Test status
Simulation time 55515022 ps
CPU time 3.03 seconds
Started Sep 04 02:58:20 AM UTC 24
Finished Sep 04 02:58:24 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781637223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3781637223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.2041763869
Short name T161
Test name
Test status
Simulation time 54218225 ps
CPU time 4.03 seconds
Started Sep 04 02:58:21 AM UTC 24
Finished Sep 04 02:58:26 AM UTC 24
Peak memory 232196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041763869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2041763869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.2244133320
Short name T159
Test name
Test status
Simulation time 62018702 ps
CPU time 4.18 seconds
Started Sep 04 02:58:20 AM UTC 24
Finished Sep 04 02:58:25 AM UTC 24
Peak memory 228208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244133320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2244133320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_random.129981653
Short name T157
Test name
Test status
Simulation time 197514854 ps
CPU time 3.63 seconds
Started Sep 04 02:58:20 AM UTC 24
Finished Sep 04 02:58:24 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129981653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.129981653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.518629167
Short name T404
Test name
Test status
Simulation time 675045172 ps
CPU time 13.35 seconds
Started Sep 04 02:58:18 AM UTC 24
Finished Sep 04 02:58:33 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518629167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.518629167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.59301601
Short name T415
Test name
Test status
Simulation time 22950781 ps
CPU time 2.11 seconds
Started Sep 04 02:58:18 AM UTC 24
Finished Sep 04 02:58:21 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59301601 -assert nopostproc +UVM_TESTNAME=keymgr_base_
test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.59301601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.2225867957
Short name T458
Test name
Test status
Simulation time 290433532 ps
CPU time 4.12 seconds
Started Sep 04 02:58:18 AM UTC 24
Finished Sep 04 02:58:23 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225867957 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2225867957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.4232546135
Short name T158
Test name
Test status
Simulation time 351055155 ps
CPU time 4.34 seconds
Started Sep 04 02:58:20 AM UTC 24
Finished Sep 04 02:58:25 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232546135 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4232546135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.3253233152
Short name T297
Test name
Test status
Simulation time 1676005311 ps
CPU time 17.29 seconds
Started Sep 04 02:58:21 AM UTC 24
Finished Sep 04 02:58:40 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253233152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3253233152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.607690784
Short name T457
Test name
Test status
Simulation time 47733054 ps
CPU time 2.69 seconds
Started Sep 04 02:58:17 AM UTC 24
Finished Sep 04 02:58:21 AM UTC 24
Peak memory 213728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607690784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.607690784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.333540739
Short name T202
Test name
Test status
Simulation time 5643203617 ps
CPU time 42.2 seconds
Started Sep 04 02:58:21 AM UTC 24
Finished Sep 04 02:59:05 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333540739 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.333540739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.30679245
Short name T164
Test name
Test status
Simulation time 79341348 ps
CPU time 4.5 seconds
Started Sep 04 02:58:21 AM UTC 24
Finished Sep 04 02:58:27 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30679245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.30679245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.4109158546
Short name T185
Test name
Test status
Simulation time 868900539 ps
CPU time 23.83 seconds
Started Sep 04 02:58:21 AM UTC 24
Finished Sep 04 02:58:47 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109158546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4109158546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.2046059020
Short name T464
Test name
Test status
Simulation time 34281780 ps
CPU time 1.1 seconds
Started Sep 04 02:58:31 AM UTC 24
Finished Sep 04 02:58:34 AM UTC 24
Peak memory 214164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046059020 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2046059020
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.1160518557
Short name T274
Test name
Test status
Simulation time 383527993 ps
CPU time 18.04 seconds
Started Sep 04 02:58:26 AM UTC 24
Finished Sep 04 02:58:46 AM UTC 24
Peak memory 224036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160518557 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1160518557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.405790301
Short name T260
Test name
Test status
Simulation time 347844663 ps
CPU time 5.17 seconds
Started Sep 04 02:58:26 AM UTC 24
Finished Sep 04 02:58:33 AM UTC 24
Peak memory 218056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405790301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.405790301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.3109328624
Short name T375
Test name
Test status
Simulation time 105327233 ps
CPU time 4.55 seconds
Started Sep 04 02:58:27 AM UTC 24
Finished Sep 04 02:58:33 AM UTC 24
Peak memory 226568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109328624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3109328624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.2895618476
Short name T301
Test name
Test status
Simulation time 59573958 ps
CPU time 3.13 seconds
Started Sep 04 02:58:28 AM UTC 24
Finished Sep 04 02:58:32 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895618476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2895618476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.1441153941
Short name T225
Test name
Test status
Simulation time 98074378 ps
CPU time 3.84 seconds
Started Sep 04 02:58:27 AM UTC 24
Finished Sep 04 02:58:32 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441153941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1441153941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_random.2940018876
Short name T330
Test name
Test status
Simulation time 79130212 ps
CPU time 3.75 seconds
Started Sep 04 02:58:26 AM UTC 24
Finished Sep 04 02:58:32 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940018876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2940018876
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.2230570590
Short name T412
Test name
Test status
Simulation time 570199865 ps
CPU time 5.64 seconds
Started Sep 04 02:58:24 AM UTC 24
Finished Sep 04 02:58:30 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230570590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2230570590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.908581909
Short name T461
Test name
Test status
Simulation time 551013286 ps
CPU time 6.32 seconds
Started Sep 04 02:58:25 AM UTC 24
Finished Sep 04 02:58:33 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908581909 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.908581909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.1886787238
Short name T460
Test name
Test status
Simulation time 40523179 ps
CPU time 3.73 seconds
Started Sep 04 02:58:25 AM UTC 24
Finished Sep 04 02:58:30 AM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886787238 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1886787238
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.486008859
Short name T462
Test name
Test status
Simulation time 172046299 ps
CPU time 7.04 seconds
Started Sep 04 02:58:25 AM UTC 24
Finished Sep 04 02:58:33 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486008859 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.486008859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.1906257443
Short name T467
Test name
Test status
Simulation time 524663147 ps
CPU time 7.17 seconds
Started Sep 04 02:58:29 AM UTC 24
Finished Sep 04 02:58:37 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906257443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1906257443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.1867714695
Short name T162
Test name
Test status
Simulation time 236636236 ps
CPU time 2.83 seconds
Started Sep 04 02:58:23 AM UTC 24
Finished Sep 04 02:58:27 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867714695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1867714695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.1968018874
Short name T371
Test name
Test status
Simulation time 747744645 ps
CPU time 6.07 seconds
Started Sep 04 02:58:27 AM UTC 24
Finished Sep 04 02:58:35 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968018874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1968018874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.2612037455
Short name T90
Test name
Test status
Simulation time 62022051 ps
CPU time 2.75 seconds
Started Sep 04 02:58:30 AM UTC 24
Finished Sep 04 02:58:34 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612037455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2612037455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.245654590
Short name T469
Test name
Test status
Simulation time 49438695 ps
CPU time 1.19 seconds
Started Sep 04 02:58:36 AM UTC 24
Finished Sep 04 02:58:38 AM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245654590 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.245654590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.3612001929
Short name T30
Test name
Test status
Simulation time 62557574 ps
CPU time 2.95 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:38 AM UTC 24
Peak memory 228532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612001929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3612001929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.2039445142
Short name T134
Test name
Test status
Simulation time 54669046 ps
CPU time 3.41 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:39 AM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039445142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2039445142
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.3638881113
Short name T319
Test name
Test status
Simulation time 164549107 ps
CPU time 4.65 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:40 AM UTC 24
Peak memory 216024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638881113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3638881113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.636497073
Short name T431
Test name
Test status
Simulation time 70356612 ps
CPU time 5.02 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:40 AM UTC 24
Peak memory 223976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636497073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.636497073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.3321498979
Short name T472
Test name
Test status
Simulation time 916786693 ps
CPU time 7.34 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:43 AM UTC 24
Peak memory 216064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321498979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3321498979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_random.2489245712
Short name T350
Test name
Test status
Simulation time 195460690 ps
CPU time 6.55 seconds
Started Sep 04 02:58:33 AM UTC 24
Finished Sep 04 02:58:41 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489245712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2489245712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.2743535217
Short name T471
Test name
Test status
Simulation time 1489183378 ps
CPU time 8.68 seconds
Started Sep 04 02:58:31 AM UTC 24
Finished Sep 04 02:58:42 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743535217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2743535217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.2836876397
Short name T463
Test name
Test status
Simulation time 448929457 ps
CPU time 6.7 seconds
Started Sep 04 02:58:33 AM UTC 24
Finished Sep 04 02:58:41 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836876397 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2836876397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.2691067010
Short name T466
Test name
Test status
Simulation time 31721350 ps
CPU time 2.5 seconds
Started Sep 04 02:58:32 AM UTC 24
Finished Sep 04 02:58:36 AM UTC 24
Peak memory 216272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691067010 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2691067010
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.4113842795
Short name T468
Test name
Test status
Simulation time 114648122 ps
CPU time 3.23 seconds
Started Sep 04 02:58:33 AM UTC 24
Finished Sep 04 02:58:37 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113842795 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4113842795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.3075838794
Short name T470
Test name
Test status
Simulation time 936000033 ps
CPU time 5.45 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:41 AM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075838794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3075838794
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.2838888738
Short name T465
Test name
Test status
Simulation time 77846533 ps
CPU time 1.98 seconds
Started Sep 04 02:58:31 AM UTC 24
Finished Sep 04 02:58:34 AM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838888738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2838888738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.2198577493
Short name T243
Test name
Test status
Simulation time 989319104 ps
CPU time 38.64 seconds
Started Sep 04 02:58:35 AM UTC 24
Finished Sep 04 02:59:16 AM UTC 24
Peak memory 230540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198577493 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2198577493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.2162275809
Short name T405
Test name
Test status
Simulation time 218202078 ps
CPU time 6.41 seconds
Started Sep 04 02:58:34 AM UTC 24
Finished Sep 04 02:58:42 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162275809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2162275809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.108584603
Short name T106
Test name
Test status
Simulation time 178432398 ps
CPU time 4 seconds
Started Sep 04 02:58:35 AM UTC 24
Finished Sep 04 02:58:41 AM UTC 24
Peak memory 219948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108584603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.108584603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.156761992
Short name T478
Test name
Test status
Simulation time 33116292 ps
CPU time 1.08 seconds
Started Sep 04 02:58:43 AM UTC 24
Finished Sep 04 02:58:45 AM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156761992 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.156761992
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.1213772190
Short name T33
Test name
Test status
Simulation time 508445490 ps
CPU time 4.47 seconds
Started Sep 04 02:58:42 AM UTC 24
Finished Sep 04 02:58:47 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213772190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1213772190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.3428533187
Short name T476
Test name
Test status
Simulation time 90403262 ps
CPU time 2.51 seconds
Started Sep 04 02:58:40 AM UTC 24
Finished Sep 04 02:58:44 AM UTC 24
Peak memory 218036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428533187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3428533187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.82039929
Short name T367
Test name
Test status
Simulation time 298379065 ps
CPU time 5.7 seconds
Started Sep 04 02:58:42 AM UTC 24
Finished Sep 04 02:58:49 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82039929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.82039929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.3237034576
Short name T480
Test name
Test status
Simulation time 52022064 ps
CPU time 3.73 seconds
Started Sep 04 02:58:42 AM UTC 24
Finished Sep 04 02:58:47 AM UTC 24
Peak memory 224060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237034576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3237034576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.1459072677
Short name T369
Test name
Test status
Simulation time 168830014 ps
CPU time 6.26 seconds
Started Sep 04 02:58:40 AM UTC 24
Finished Sep 04 02:58:48 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459072677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1459072677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_random.2200462702
Short name T477
Test name
Test status
Simulation time 75170161 ps
CPU time 4.53 seconds
Started Sep 04 02:58:39 AM UTC 24
Finished Sep 04 02:58:45 AM UTC 24
Peak memory 220380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200462702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2200462702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.125625025
Short name T316
Test name
Test status
Simulation time 96450630 ps
CPU time 3.11 seconds
Started Sep 04 02:58:38 AM UTC 24
Finished Sep 04 02:58:42 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125625025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.125625025
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.1192423058
Short name T540
Test name
Test status
Simulation time 8252070328 ps
CPU time 43.84 seconds
Started Sep 04 02:58:39 AM UTC 24
Finished Sep 04 02:59:24 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192423058 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1192423058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.1688034819
Short name T474
Test name
Test status
Simulation time 318504578 ps
CPU time 3.99 seconds
Started Sep 04 02:58:38 AM UTC 24
Finished Sep 04 02:58:43 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688034819 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1688034819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.1250014438
Short name T473
Test name
Test status
Simulation time 70192899 ps
CPU time 2.81 seconds
Started Sep 04 02:58:39 AM UTC 24
Finished Sep 04 02:58:43 AM UTC 24
Peak memory 218304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250014438 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1250014438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.4004357123
Short name T475
Test name
Test status
Simulation time 205200920 ps
CPU time 4.97 seconds
Started Sep 04 02:58:38 AM UTC 24
Finished Sep 04 02:58:44 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004357123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4004357123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.2575190983
Short name T344
Test name
Test status
Simulation time 3144674313 ps
CPU time 31.42 seconds
Started Sep 04 02:58:42 AM UTC 24
Finished Sep 04 02:59:15 AM UTC 24
Peak memory 230996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575190983 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2575190983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.2051623583
Short name T479
Test name
Test status
Simulation time 105733156 ps
CPU time 3.36 seconds
Started Sep 04 02:58:42 AM UTC 24
Finished Sep 04 02:58:46 AM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051623583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2051623583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.1780949964
Short name T413
Test name
Test status
Simulation time 113833733 ps
CPU time 3.36 seconds
Started Sep 04 02:58:42 AM UTC 24
Finished Sep 04 02:58:46 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780949964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1780949964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.1961903275
Short name T485
Test name
Test status
Simulation time 14891188 ps
CPU time 1.15 seconds
Started Sep 04 02:58:49 AM UTC 24
Finished Sep 04 02:58:51 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961903275 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1961903275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.666465419
Short name T401
Test name
Test status
Simulation time 66325490 ps
CPU time 5.87 seconds
Started Sep 04 02:58:46 AM UTC 24
Finished Sep 04 02:58:53 AM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666465419 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.666465419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.3093470355
Short name T41
Test name
Test status
Simulation time 159555543 ps
CPU time 4.76 seconds
Started Sep 04 02:58:47 AM UTC 24
Finished Sep 04 02:58:53 AM UTC 24
Peak memory 218284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093470355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3093470355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.1687380829
Short name T356
Test name
Test status
Simulation time 46722154 ps
CPU time 2.66 seconds
Started Sep 04 02:58:46 AM UTC 24
Finished Sep 04 02:58:50 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687380829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1687380829
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.2306622125
Short name T391
Test name
Test status
Simulation time 525659978 ps
CPU time 4.38 seconds
Started Sep 04 02:58:47 AM UTC 24
Finished Sep 04 02:58:53 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306622125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2306622125
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.3968564974
Short name T487
Test name
Test status
Simulation time 69791850 ps
CPU time 4.08 seconds
Started Sep 04 02:58:46 AM UTC 24
Finished Sep 04 02:58:51 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968564974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3968564974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_random.3448470325
Short name T379
Test name
Test status
Simulation time 611900908 ps
CPU time 10.3 seconds
Started Sep 04 02:58:45 AM UTC 24
Finished Sep 04 02:58:56 AM UTC 24
Peak memory 218156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448470325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3448470325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.2101296160
Short name T482
Test name
Test status
Simulation time 55734027 ps
CPU time 3.06 seconds
Started Sep 04 02:58:44 AM UTC 24
Finished Sep 04 02:58:48 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101296160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2101296160
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.1840982075
Short name T488
Test name
Test status
Simulation time 157002373 ps
CPU time 6.28 seconds
Started Sep 04 02:58:44 AM UTC 24
Finished Sep 04 02:58:52 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840982075 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1840982075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.3618366925
Short name T484
Test name
Test status
Simulation time 439901731 ps
CPU time 4.79 seconds
Started Sep 04 02:58:44 AM UTC 24
Finished Sep 04 02:58:50 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618366925 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3618366925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.1147383707
Short name T483
Test name
Test status
Simulation time 699334631 ps
CPU time 3.89 seconds
Started Sep 04 02:58:45 AM UTC 24
Finished Sep 04 02:58:50 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147383707 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1147383707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.492279572
Short name T490
Test name
Test status
Simulation time 51205920 ps
CPU time 3.65 seconds
Started Sep 04 02:58:47 AM UTC 24
Finished Sep 04 02:58:52 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492279572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.492279572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.3119461776
Short name T481
Test name
Test status
Simulation time 364522510 ps
CPU time 2.56 seconds
Started Sep 04 02:58:43 AM UTC 24
Finished Sep 04 02:58:47 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119461776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3119461776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.2641413223
Short name T139
Test name
Test status
Simulation time 5081814874 ps
CPU time 81.24 seconds
Started Sep 04 02:58:47 AM UTC 24
Finished Sep 04 03:00:11 AM UTC 24
Peak memory 232332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641413223 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2641413223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.774396565
Short name T489
Test name
Test status
Simulation time 108074546 ps
CPU time 5.05 seconds
Started Sep 04 02:58:46 AM UTC 24
Finished Sep 04 02:58:52 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774396565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.774396565
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.3687844485
Short name T486
Test name
Test status
Simulation time 37437010 ps
CPU time 2.41 seconds
Started Sep 04 02:58:47 AM UTC 24
Finished Sep 04 02:58:51 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687844485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3687844485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.2401691752
Short name T496
Test name
Test status
Simulation time 20671086 ps
CPU time 1.08 seconds
Started Sep 04 02:58:55 AM UTC 24
Finished Sep 04 02:58:57 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401691752 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2401691752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.3605829327
Short name T11
Test name
Test status
Simulation time 386719807 ps
CPU time 6.02 seconds
Started Sep 04 02:58:54 AM UTC 24
Finished Sep 04 02:59:01 AM UTC 24
Peak memory 224304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605829327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3605829327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.3230974952
Short name T491
Test name
Test status
Simulation time 75360962 ps
CPU time 2.51 seconds
Started Sep 04 02:58:52 AM UTC 24
Finished Sep 04 02:58:56 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230974952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3230974952
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.3589266145
Short name T495
Test name
Test status
Simulation time 248204675 ps
CPU time 3.28 seconds
Started Sep 04 02:58:52 AM UTC 24
Finished Sep 04 02:58:57 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589266145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3589266145
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.2426846078
Short name T347
Test name
Test status
Simulation time 161909289 ps
CPU time 4.04 seconds
Started Sep 04 02:58:52 AM UTC 24
Finished Sep 04 02:58:57 AM UTC 24
Peak memory 230264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426846078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2426846078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_random.4115676500
Short name T526
Test name
Test status
Simulation time 1024691455 ps
CPU time 25.46 seconds
Started Sep 04 02:58:51 AM UTC 24
Finished Sep 04 02:59:18 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115676500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.4115676500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.3436481173
Short name T287
Test name
Test status
Simulation time 62243444 ps
CPU time 4.48 seconds
Started Sep 04 02:58:49 AM UTC 24
Finished Sep 04 02:58:54 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436481173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3436481173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.310406765
Short name T493
Test name
Test status
Simulation time 117777157 ps
CPU time 5.31 seconds
Started Sep 04 02:58:50 AM UTC 24
Finished Sep 04 02:58:56 AM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310406765 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.310406765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.1150687877
Short name T567
Test name
Test status
Simulation time 3285579385 ps
CPU time 43.59 seconds
Started Sep 04 02:58:50 AM UTC 24
Finished Sep 04 02:59:35 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150687877 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1150687877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.787638347
Short name T492
Test name
Test status
Simulation time 273160127 ps
CPU time 3.67 seconds
Started Sep 04 02:58:51 AM UTC 24
Finished Sep 04 02:58:56 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787638347 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.787638347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.62231565
Short name T494
Test name
Test status
Simulation time 27776188 ps
CPU time 1.91 seconds
Started Sep 04 02:58:54 AM UTC 24
Finished Sep 04 02:58:57 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62231565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.62231565
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.3710517048
Short name T408
Test name
Test status
Simulation time 680914709 ps
CPU time 7.42 seconds
Started Sep 04 02:58:49 AM UTC 24
Finished Sep 04 02:58:57 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710517048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3710517048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.395646573
Short name T236
Test name
Test status
Simulation time 1189594634 ps
CPU time 37.76 seconds
Started Sep 04 02:58:54 AM UTC 24
Finished Sep 04 02:59:33 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395646573 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.395646573
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.2429629414
Short name T378
Test name
Test status
Simulation time 262537175 ps
CPU time 6.59 seconds
Started Sep 04 02:58:52 AM UTC 24
Finished Sep 04 02:59:00 AM UTC 24
Peak memory 219928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429629414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2429629414
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.2664664542
Short name T100
Test name
Test status
Simulation time 358232691 ps
CPU time 3.65 seconds
Started Sep 04 02:58:54 AM UTC 24
Finished Sep 04 02:58:58 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664664542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2664664542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.88510897
Short name T503
Test name
Test status
Simulation time 50912400 ps
CPU time 1.11 seconds
Started Sep 04 02:59:01 AM UTC 24
Finished Sep 04 02:59:03 AM UTC 24
Peak memory 213536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88510897 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.88510897
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.1786715250
Short name T435
Test name
Test status
Simulation time 39512497 ps
CPU time 3.93 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:03 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786715250 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1786715250
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.3558176728
Short name T146
Test name
Test status
Simulation time 183404575 ps
CPU time 3.04 seconds
Started Sep 04 02:58:59 AM UTC 24
Finished Sep 04 02:59:03 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558176728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3558176728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.3659454451
Short name T372
Test name
Test status
Simulation time 123065428 ps
CPU time 3.31 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:02 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659454451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3659454451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.1381137277
Short name T499
Test name
Test status
Simulation time 86911422 ps
CPU time 2.99 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:02 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381137277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1381137277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.822038284
Short name T520
Test name
Test status
Simulation time 1294094022 ps
CPU time 13.54 seconds
Started Sep 04 02:58:59 AM UTC 24
Finished Sep 04 02:59:14 AM UTC 24
Peak memory 232160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822038284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.822038284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.2783591752
Short name T406
Test name
Test status
Simulation time 933635904 ps
CPU time 5.24 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:04 AM UTC 24
Peak memory 229548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783591752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2783591752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_random.4148235726
Short name T505
Test name
Test status
Simulation time 468719812 ps
CPU time 4.85 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:04 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148235726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.4148235726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.2218494584
Short name T504
Test name
Test status
Simulation time 85263301 ps
CPU time 5.41 seconds
Started Sep 04 02:58:56 AM UTC 24
Finished Sep 04 02:59:03 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218494584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2218494584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.3316899905
Short name T508
Test name
Test status
Simulation time 330178936 ps
CPU time 6.67 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:05 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316899905 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3316899905
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.4076020212
Short name T498
Test name
Test status
Simulation time 91284107 ps
CPU time 2.14 seconds
Started Sep 04 02:58:56 AM UTC 24
Finished Sep 04 02:58:59 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076020212 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4076020212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.1767165623
Short name T502
Test name
Test status
Simulation time 73208981 ps
CPU time 3.67 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:02 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767165623 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1767165623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.4183952228
Short name T506
Test name
Test status
Simulation time 354322305 ps
CPU time 3.53 seconds
Started Sep 04 02:58:59 AM UTC 24
Finished Sep 04 02:59:04 AM UTC 24
Peak memory 230276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183952228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4183952228
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.3034749309
Short name T497
Test name
Test status
Simulation time 77338293 ps
CPU time 2.57 seconds
Started Sep 04 02:58:55 AM UTC 24
Finished Sep 04 02:58:59 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034749309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3034749309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.1907270024
Short name T254
Test name
Test status
Simulation time 715397122 ps
CPU time 29.29 seconds
Started Sep 04 02:59:00 AM UTC 24
Finished Sep 04 02:59:30 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907270024 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1907270024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.547898590
Short name T101
Test name
Test status
Simulation time 600090729 ps
CPU time 9.87 seconds
Started Sep 04 02:59:01 AM UTC 24
Finished Sep 04 02:59:12 AM UTC 24
Peak memory 232352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=547898590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr
_stress_all_with_rand_reset.547898590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.3662129256
Short name T501
Test name
Test status
Simulation time 1273236085 ps
CPU time 10.84 seconds
Started Sep 04 02:58:58 AM UTC 24
Finished Sep 04 02:59:10 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662129256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3662129256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.1911177543
Short name T500
Test name
Test status
Simulation time 58728580 ps
CPU time 1.83 seconds
Started Sep 04 02:58:59 AM UTC 24
Finished Sep 04 02:59:02 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911177543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1911177543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.1035403
Short name T509
Test name
Test status
Simulation time 126692806 ps
CPU time 1.27 seconds
Started Sep 04 02:59:06 AM UTC 24
Finished Sep 04 02:59:09 AM UTC 24
Peak memory 213660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035403 -assert nopostproc +UVM_TESTNAME=keymgr
_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1035403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.4038767029
Short name T419
Test name
Test status
Simulation time 7680365899 ps
CPU time 96.67 seconds
Started Sep 04 02:59:03 AM UTC 24
Finished Sep 04 03:00:42 AM UTC 24
Peak memory 224092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038767029 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4038767029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.2891355761
Short name T514
Test name
Test status
Simulation time 606796780 ps
CPU time 5.49 seconds
Started Sep 04 02:59:05 AM UTC 24
Finished Sep 04 02:59:11 AM UTC 24
Peak memory 228788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891355761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2891355761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.3298834089
Short name T373
Test name
Test status
Simulation time 130865824 ps
CPU time 3.43 seconds
Started Sep 04 02:59:03 AM UTC 24
Finished Sep 04 02:59:08 AM UTC 24
Peak memory 218324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298834089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3298834089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.3044424886
Short name T302
Test name
Test status
Simulation time 297761009 ps
CPU time 2.96 seconds
Started Sep 04 02:59:05 AM UTC 24
Finished Sep 04 02:59:09 AM UTC 24
Peak memory 215884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044424886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3044424886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.2901419883
Short name T512
Test name
Test status
Simulation time 271342837 ps
CPU time 4.83 seconds
Started Sep 04 02:59:05 AM UTC 24
Finished Sep 04 02:59:10 AM UTC 24
Peak memory 224176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901419883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2901419883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_random.4218159615
Short name T519
Test name
Test status
Simulation time 797394287 ps
CPU time 9.22 seconds
Started Sep 04 02:59:03 AM UTC 24
Finished Sep 04 02:59:14 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218159615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4218159615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.2086852316
Short name T515
Test name
Test status
Simulation time 170576960 ps
CPU time 7.55 seconds
Started Sep 04 02:59:03 AM UTC 24
Finished Sep 04 02:59:12 AM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086852316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2086852316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.1058787242
Short name T402
Test name
Test status
Simulation time 57129714 ps
CPU time 3.42 seconds
Started Sep 04 02:59:03 AM UTC 24
Finished Sep 04 02:59:08 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058787242 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1058787242
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.44108450
Short name T354
Test name
Test status
Simulation time 20929191 ps
CPU time 2.51 seconds
Started Sep 04 02:59:03 AM UTC 24
Finished Sep 04 02:59:07 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44108450 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.44108450
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.1775370994
Short name T516
Test name
Test status
Simulation time 737751592 ps
CPU time 8.67 seconds
Started Sep 04 02:59:03 AM UTC 24
Finished Sep 04 02:59:13 AM UTC 24
Peak memory 215932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775370994 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1775370994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.1875407955
Short name T510
Test name
Test status
Simulation time 85152079 ps
CPU time 4.09 seconds
Started Sep 04 02:59:05 AM UTC 24
Finished Sep 04 02:59:10 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875407955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1875407955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.2011773133
Short name T507
Test name
Test status
Simulation time 28596316 ps
CPU time 2.54 seconds
Started Sep 04 02:59:02 AM UTC 24
Finished Sep 04 02:59:05 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011773133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2011773133
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.1700360924
Short name T332
Test name
Test status
Simulation time 135274305 ps
CPU time 8.18 seconds
Started Sep 04 02:59:06 AM UTC 24
Finished Sep 04 02:59:15 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700360924 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1700360924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.3295414537
Short name T309
Test name
Test status
Simulation time 100830711 ps
CPU time 4.42 seconds
Started Sep 04 02:59:05 AM UTC 24
Finished Sep 04 02:59:10 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295414537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3295414537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.65438154
Short name T195
Test name
Test status
Simulation time 225562242 ps
CPU time 3.77 seconds
Started Sep 04 02:59:06 AM UTC 24
Finished Sep 04 02:59:11 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65438154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.65438154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.2207881542
Short name T66
Test name
Test status
Simulation time 17105497 ps
CPU time 1.12 seconds
Started Sep 04 02:57:10 AM UTC 24
Finished Sep 04 02:57:13 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207881542 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2207881542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.2387862031
Short name T82
Test name
Test status
Simulation time 26260331 ps
CPU time 2.92 seconds
Started Sep 04 02:57:05 AM UTC 24
Finished Sep 04 02:57:09 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387862031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2387862031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.666837054
Short name T52
Test name
Test status
Simulation time 155006823 ps
CPU time 4.11 seconds
Started Sep 04 02:57:07 AM UTC 24
Finished Sep 04 02:57:12 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666837054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.666837054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.851831821
Short name T64
Test name
Test status
Simulation time 69782766 ps
CPU time 4.3 seconds
Started Sep 04 02:57:06 AM UTC 24
Finished Sep 04 02:57:12 AM UTC 24
Peak memory 230248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851831821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.851831821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_random.2298455346
Short name T215
Test name
Test status
Simulation time 1136006782 ps
CPU time 27.91 seconds
Started Sep 04 02:57:05 AM UTC 24
Finished Sep 04 02:57:34 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298455346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2298455346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.823644069
Short name T14
Test name
Test status
Simulation time 413753677 ps
CPU time 12.93 seconds
Started Sep 04 02:57:10 AM UTC 24
Finished Sep 04 02:57:25 AM UTC 24
Peak memory 252312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823644069 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.823644069
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.2110047413
Short name T80
Test name
Test status
Simulation time 85841629 ps
CPU time 3.01 seconds
Started Sep 04 02:57:04 AM UTC 24
Finished Sep 04 02:57:08 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110047413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2110047413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.1859717390
Short name T68
Test name
Test status
Simulation time 163123663 ps
CPU time 4.01 seconds
Started Sep 04 02:57:04 AM UTC 24
Finished Sep 04 02:57:09 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859717390 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1859717390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.3344739078
Short name T81
Test name
Test status
Simulation time 84493614 ps
CPU time 3.64 seconds
Started Sep 04 02:57:04 AM UTC 24
Finished Sep 04 02:57:09 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344739078 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3344739078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.3945887823
Short name T83
Test name
Test status
Simulation time 82470789 ps
CPU time 3.71 seconds
Started Sep 04 02:57:05 AM UTC 24
Finished Sep 04 02:57:10 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945887823 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3945887823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.3552623923
Short name T214
Test name
Test status
Simulation time 208225157 ps
CPU time 5.52 seconds
Started Sep 04 02:57:08 AM UTC 24
Finished Sep 04 02:57:15 AM UTC 24
Peak memory 218036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552623923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3552623923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.3509623215
Short name T209
Test name
Test status
Simulation time 782398750 ps
CPU time 17.9 seconds
Started Sep 04 02:57:03 AM UTC 24
Finished Sep 04 02:57:22 AM UTC 24
Peak memory 217844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509623215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3509623215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.2260365276
Short name T28
Test name
Test status
Simulation time 324287589 ps
CPU time 8.94 seconds
Started Sep 04 02:57:07 AM UTC 24
Finished Sep 04 02:57:17 AM UTC 24
Peak memory 224024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260365276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2260365276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.2677222461
Short name T85
Test name
Test status
Simulation time 258408214 ps
CPU time 3.68 seconds
Started Sep 04 02:57:08 AM UTC 24
Finished Sep 04 02:57:13 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677222461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2677222461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.815818481
Short name T522
Test name
Test status
Simulation time 38435662 ps
CPU time 1.1 seconds
Started Sep 04 02:59:14 AM UTC 24
Finished Sep 04 02:59:16 AM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815818481 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.815818481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.4181615054
Short name T282
Test name
Test status
Simulation time 238856102 ps
CPU time 3.28 seconds
Started Sep 04 02:59:10 AM UTC 24
Finished Sep 04 02:59:14 AM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181615054 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.4181615054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.946984063
Short name T341
Test name
Test status
Simulation time 51153761 ps
CPU time 2.5 seconds
Started Sep 04 02:59:11 AM UTC 24
Finished Sep 04 02:59:15 AM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946984063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.946984063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.2438310400
Short name T377
Test name
Test status
Simulation time 1571481421 ps
CPU time 4.07 seconds
Started Sep 04 02:59:12 AM UTC 24
Finished Sep 04 02:59:17 AM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438310400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2438310400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.290625391
Short name T521
Test name
Test status
Simulation time 110382793 ps
CPU time 3.53 seconds
Started Sep 04 02:59:11 AM UTC 24
Finished Sep 04 02:59:16 AM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290625391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.290625391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_random.3801630462
Short name T524
Test name
Test status
Simulation time 100350915 ps
CPU time 6.54 seconds
Started Sep 04 02:59:10 AM UTC 24
Finished Sep 04 02:59:17 AM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801630462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3801630462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.1039885169
Short name T525
Test name
Test status
Simulation time 761912650 ps
CPU time 9.06 seconds
Started Sep 04 02:59:07 AM UTC 24
Finished Sep 04 02:59:18 AM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039885169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1039885169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.1387517768
Short name T517
Test name
Test status
Simulation time 62942002 ps
CPU time 3.49 seconds
Started Sep 04 02:59:09 AM UTC 24
Finished Sep 04 02:59:13 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387517768 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1387517768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.1021666179
Short name T564
Test name
Test status
Simulation time 872656042 ps
CPU time 23.57 seconds
Started Sep 04 02:59:09 AM UTC 24
Finished Sep 04 02:59:33 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021666179 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1021666179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.4122737554
Short name T518
Test name
Test status
Simulation time 58134246 ps
CPU time 3.83 seconds
Started Sep 04 02:59:09 AM UTC 24
Finished Sep 04 02:59:13 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122737554 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4122737554
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.3841969915
Short name T307
Test name
Test status
Simulation time 555000223 ps
CPU time 5.33 seconds
Started Sep 04 02:59:12 AM UTC 24
Finished Sep 04 02:59:19 AM UTC 24
Peak memory 218388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841969915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3841969915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.197060211
Short name T511
Test name
Test status
Simulation time 258455316 ps
CPU time 4.13 seconds
Started Sep 04 02:59:06 AM UTC 24
Finished Sep 04 02:59:11 AM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197060211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.197060211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.3975832156
Short name T535
Test name
Test status
Simulation time 332050396 ps
CPU time 9 seconds
Started Sep 04 02:59:13 AM UTC 24
Finished Sep 04 02:59:23 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975832156 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3975832156
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.2042156084
Short name T107
Test name
Test status
Simulation time 603023601 ps
CPU time 21.53 seconds
Started Sep 04 02:59:13 AM UTC 24
Finished Sep 04 02:59:35 AM UTC 24
Peak memory 230516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2042156084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg
r_stress_all_with_rand_reset.2042156084
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.5431184
Short name T556
Test name
Test status
Simulation time 1398179014 ps
CPU time 16.75 seconds
Started Sep 04 02:59:11 AM UTC 24
Finished Sep 04 02:59:29 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5431184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k
eymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.5431184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.3465765333
Short name T523
Test name
Test status
Simulation time 354586318 ps
CPU time 3.49 seconds
Started Sep 04 02:59:13 AM UTC 24
Finished Sep 04 02:59:17 AM UTC 24
Peak memory 230252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465765333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3465765333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.2637386899
Short name T529
Test name
Test status
Simulation time 208355628 ps
CPU time 1.12 seconds
Started Sep 04 02:59:19 AM UTC 24
Finished Sep 04 02:59:21 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637386899 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2637386899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1639890479
Short name T353
Test name
Test status
Simulation time 56484984 ps
CPU time 5.09 seconds
Started Sep 04 02:59:15 AM UTC 24
Finished Sep 04 02:59:21 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639890479 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1639890479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.72430141
Short name T34
Test name
Test status
Simulation time 170384285 ps
CPU time 3.29 seconds
Started Sep 04 02:59:17 AM UTC 24
Finished Sep 04 02:59:21 AM UTC 24
Peak memory 220368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72430141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.72430141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.2878350618
Short name T528
Test name
Test status
Simulation time 36192532 ps
CPU time 1.91 seconds
Started Sep 04 02:59:17 AM UTC 24
Finished Sep 04 02:59:20 AM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878350618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2878350618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.1122598092
Short name T374
Test name
Test status
Simulation time 313948658 ps
CPU time 5.35 seconds
Started Sep 04 02:59:17 AM UTC 24
Finished Sep 04 02:59:23 AM UTC 24
Peak memory 216068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122598092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1122598092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.374987929
Short name T242
Test name
Test status
Simulation time 69347230 ps
CPU time 3.62 seconds
Started Sep 04 02:59:17 AM UTC 24
Finished Sep 04 02:59:21 AM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374987929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.374987929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_random.3792478886
Short name T530
Test name
Test status
Simulation time 88365111 ps
CPU time 4.48 seconds
Started Sep 04 02:59:15 AM UTC 24
Finished Sep 04 02:59:21 AM UTC 24
Peak memory 218028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792478886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3792478886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.888479285
Short name T534
Test name
Test status
Simulation time 524270222 ps
CPU time 6.44 seconds
Started Sep 04 02:59:15 AM UTC 24
Finished Sep 04 02:59:22 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888479285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.888479285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.1072631843
Short name T532
Test name
Test status
Simulation time 197340453 ps
CPU time 5.08 seconds
Started Sep 04 02:59:15 AM UTC 24
Finished Sep 04 02:59:21 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072631843 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1072631843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.1882284516
Short name T531
Test name
Test status
Simulation time 92471768 ps
CPU time 4.78 seconds
Started Sep 04 02:59:15 AM UTC 24
Finished Sep 04 02:59:21 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882284516 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1882284516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.3313908268
Short name T527
Test name
Test status
Simulation time 216374879 ps
CPU time 3.16 seconds
Started Sep 04 02:59:15 AM UTC 24
Finished Sep 04 02:59:19 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313908268 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3313908268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.1537523910
Short name T533
Test name
Test status
Simulation time 34127658 ps
CPU time 2.54 seconds
Started Sep 04 02:59:18 AM UTC 24
Finished Sep 04 02:59:22 AM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537523910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1537523910
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.1683865263
Short name T570
Test name
Test status
Simulation time 3387829330 ps
CPU time 20.9 seconds
Started Sep 04 02:59:14 AM UTC 24
Finished Sep 04 02:59:36 AM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683865263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1683865263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.2825308397
Short name T230
Test name
Test status
Simulation time 14683876959 ps
CPU time 135.28 seconds
Started Sep 04 02:59:18 AM UTC 24
Finished Sep 04 03:01:36 AM UTC 24
Peak memory 232348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825308397 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2825308397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all_with_rand_reset.2338184803
Short name T103
Test name
Test status
Simulation time 1210445115 ps
CPU time 7.1 seconds
Started Sep 04 02:59:18 AM UTC 24
Finished Sep 04 02:59:27 AM UTC 24
Peak memory 232636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2338184803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymg
r_stress_all_with_rand_reset.2338184803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.52879503
Short name T368
Test name
Test status
Simulation time 58461386 ps
CPU time 4.02 seconds
Started Sep 04 02:59:17 AM UTC 24
Finished Sep 04 02:59:22 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52879503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.52879503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.1622164240
Short name T546
Test name
Test status
Simulation time 21344180 ps
CPU time 1.1 seconds
Started Sep 04 02:59:24 AM UTC 24
Finished Sep 04 02:59:26 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622164240 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1622164240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.2112597837
Short name T543
Test name
Test status
Simulation time 88470217 ps
CPU time 1.86 seconds
Started Sep 04 02:59:23 AM UTC 24
Finished Sep 04 02:59:26 AM UTC 24
Peak memory 225572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112597837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2112597837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.788918313
Short name T539
Test name
Test status
Simulation time 18234621 ps
CPU time 1.81 seconds
Started Sep 04 02:59:21 AM UTC 24
Finished Sep 04 02:59:24 AM UTC 24
Peak memory 217692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788918313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.788918313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.230192211
Short name T62
Test name
Test status
Simulation time 42510364 ps
CPU time 3.88 seconds
Started Sep 04 02:59:23 AM UTC 24
Finished Sep 04 02:59:28 AM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230192211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.230192211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.2889594766
Short name T376
Test name
Test status
Simulation time 460460491 ps
CPU time 6.83 seconds
Started Sep 04 02:59:23 AM UTC 24
Finished Sep 04 02:59:31 AM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889594766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2889594766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.603822374
Short name T541
Test name
Test status
Simulation time 63689283 ps
CPU time 2.02 seconds
Started Sep 04 02:59:21 AM UTC 24
Finished Sep 04 02:59:24 AM UTC 24
Peak memory 216204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603822374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.603822374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_random.1555949257
Short name T545
Test name
Test status
Simulation time 200279550 ps
CPU time 3.92 seconds
Started Sep 04 02:59:21 AM UTC 24
Finished Sep 04 02:59:26 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555949257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1555949257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.1542941289
Short name T542
Test name
Test status
Simulation time 386737838 ps
CPU time 3.83 seconds
Started Sep 04 02:59:20 AM UTC 24
Finished Sep 04 02:59:25 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542941289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1542941289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.4162351170
Short name T538
Test name
Test status
Simulation time 131276986 ps
CPU time 2.68 seconds
Started Sep 04 02:59:20 AM UTC 24
Finished Sep 04 02:59:24 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162351170 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4162351170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.923619891
Short name T537
Test name
Test status
Simulation time 20765543 ps
CPU time 2.44 seconds
Started Sep 04 02:59:20 AM UTC 24
Finished Sep 04 02:59:23 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923619891 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.923619891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.1464970834
Short name T548
Test name
Test status
Simulation time 456321917 ps
CPU time 5.52 seconds
Started Sep 04 02:59:20 AM UTC 24
Finished Sep 04 02:59:27 AM UTC 24
Peak memory 217928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464970834 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1464970834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.2780669243
Short name T549
Test name
Test status
Simulation time 79613133 ps
CPU time 3.81 seconds
Started Sep 04 02:59:23 AM UTC 24
Finished Sep 04 02:59:28 AM UTC 24
Peak memory 228184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780669243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2780669243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.155785751
Short name T536
Test name
Test status
Simulation time 123374762 ps
CPU time 3.14 seconds
Started Sep 04 02:59:19 AM UTC 24
Finished Sep 04 02:59:23 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155785751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.155785751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.3160714879
Short name T550
Test name
Test status
Simulation time 699854723 ps
CPU time 4.07 seconds
Started Sep 04 02:59:23 AM UTC 24
Finished Sep 04 02:59:28 AM UTC 24
Peak memory 228156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160714879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3160714879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.3752232195
Short name T547
Test name
Test status
Simulation time 63466115 ps
CPU time 2.64 seconds
Started Sep 04 02:59:23 AM UTC 24
Finished Sep 04 02:59:26 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752232195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3752232195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.54700840
Short name T561
Test name
Test status
Simulation time 12134881 ps
CPU time 1.35 seconds
Started Sep 04 02:59:29 AM UTC 24
Finished Sep 04 02:59:31 AM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54700840 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.54700840
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.936198149
Short name T421
Test name
Test status
Simulation time 2150122884 ps
CPU time 107.13 seconds
Started Sep 04 02:59:26 AM UTC 24
Finished Sep 04 03:01:15 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936198149 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.936198149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.1082740237
Short name T569
Test name
Test status
Simulation time 226640568 ps
CPU time 7.34 seconds
Started Sep 04 02:59:27 AM UTC 24
Finished Sep 04 02:59:36 AM UTC 24
Peak memory 218300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082740237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1082740237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.93935430
Short name T554
Test name
Test status
Simulation time 41022184 ps
CPU time 2.16 seconds
Started Sep 04 02:59:26 AM UTC 24
Finished Sep 04 02:59:29 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93935430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.93935430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.2454885374
Short name T560
Test name
Test status
Simulation time 302687868 ps
CPU time 2.89 seconds
Started Sep 04 02:59:27 AM UTC 24
Finished Sep 04 02:59:31 AM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454885374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2454885374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.1894270512
Short name T557
Test name
Test status
Simulation time 177359842 ps
CPU time 2.67 seconds
Started Sep 04 02:59:26 AM UTC 24
Finished Sep 04 02:59:30 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894270512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1894270512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_random.3354867252
Short name T562
Test name
Test status
Simulation time 112982756 ps
CPU time 4.61 seconds
Started Sep 04 02:59:26 AM UTC 24
Finished Sep 04 02:59:31 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354867252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3354867252
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.3110399465
Short name T610
Test name
Test status
Simulation time 1272415377 ps
CPU time 28.74 seconds
Started Sep 04 02:59:24 AM UTC 24
Finished Sep 04 02:59:54 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110399465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3110399465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.2223948332
Short name T551
Test name
Test status
Simulation time 171831381 ps
CPU time 2.29 seconds
Started Sep 04 02:59:24 AM UTC 24
Finished Sep 04 02:59:28 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223948332 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2223948332
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.3949125176
Short name T552
Test name
Test status
Simulation time 24021626 ps
CPU time 2.51 seconds
Started Sep 04 02:59:24 AM UTC 24
Finished Sep 04 02:59:28 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949125176 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3949125176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.3615286060
Short name T555
Test name
Test status
Simulation time 35706162 ps
CPU time 3.36 seconds
Started Sep 04 02:59:25 AM UTC 24
Finished Sep 04 02:59:29 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615286060 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3615286060
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.3897888232
Short name T559
Test name
Test status
Simulation time 75543093 ps
CPU time 2.69 seconds
Started Sep 04 02:59:27 AM UTC 24
Finished Sep 04 02:59:31 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897888232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3897888232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.2990238241
Short name T553
Test name
Test status
Simulation time 130401849 ps
CPU time 3.19 seconds
Started Sep 04 02:59:24 AM UTC 24
Finished Sep 04 02:59:28 AM UTC 24
Peak memory 217912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990238241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2990238241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.4273453631
Short name T138
Test name
Test status
Simulation time 4177573555 ps
CPU time 37.16 seconds
Started Sep 04 02:59:29 AM UTC 24
Finished Sep 04 03:00:07 AM UTC 24
Peak memory 231044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273453631 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4273453631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.1762819000
Short name T613
Test name
Test status
Simulation time 4691161703 ps
CPU time 29.6 seconds
Started Sep 04 02:59:27 AM UTC 24
Finished Sep 04 02:59:58 AM UTC 24
Peak memory 230236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762819000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1762819000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.3635915856
Short name T558
Test name
Test status
Simulation time 179538337 ps
CPU time 1.89 seconds
Started Sep 04 02:59:27 AM UTC 24
Finished Sep 04 02:59:30 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635915856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3635915856
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.1769478104
Short name T571
Test name
Test status
Simulation time 43914238 ps
CPU time 1.13 seconds
Started Sep 04 02:59:34 AM UTC 24
Finished Sep 04 02:59:36 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769478104 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1769478104
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.175495750
Short name T267
Test name
Test status
Simulation time 76234317 ps
CPU time 5.08 seconds
Started Sep 04 02:59:30 AM UTC 24
Finished Sep 04 02:59:36 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175495750 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.175495750
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.2747060972
Short name T568
Test name
Test status
Simulation time 123548692 ps
CPU time 2.45 seconds
Started Sep 04 02:59:32 AM UTC 24
Finished Sep 04 02:59:35 AM UTC 24
Peak memory 230904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747060972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2747060972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.3730559037
Short name T565
Test name
Test status
Simulation time 367811647 ps
CPU time 2.4 seconds
Started Sep 04 02:59:30 AM UTC 24
Finished Sep 04 02:59:34 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730559037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3730559037
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.3537974580
Short name T50
Test name
Test status
Simulation time 35411410 ps
CPU time 3.77 seconds
Started Sep 04 02:59:32 AM UTC 24
Finished Sep 04 02:59:36 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537974580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3537974580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.3545742713
Short name T303
Test name
Test status
Simulation time 224373398 ps
CPU time 2.75 seconds
Started Sep 04 02:59:32 AM UTC 24
Finished Sep 04 02:59:35 AM UTC 24
Peak memory 226016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545742713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3545742713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_random.285976876
Short name T578
Test name
Test status
Simulation time 1225944630 ps
CPU time 9.32 seconds
Started Sep 04 02:59:30 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 228216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285976876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.285976876
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.170285111
Short name T623
Test name
Test status
Simulation time 6132849742 ps
CPU time 33.63 seconds
Started Sep 04 02:59:29 AM UTC 24
Finished Sep 04 03:00:04 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170285111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.170285111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.3131472355
Short name T513
Test name
Test status
Simulation time 148121533 ps
CPU time 3.06 seconds
Started Sep 04 02:59:30 AM UTC 24
Finished Sep 04 02:59:34 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131472355 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3131472355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.352878170
Short name T572
Test name
Test status
Simulation time 198916487 ps
CPU time 6.88 seconds
Started Sep 04 02:59:29 AM UTC 24
Finished Sep 04 02:59:37 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352878170 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.352878170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.998625818
Short name T544
Test name
Test status
Simulation time 558108148 ps
CPU time 3.73 seconds
Started Sep 04 02:59:30 AM UTC 24
Finished Sep 04 02:59:35 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998625818 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.998625818
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.659002963
Short name T580
Test name
Test status
Simulation time 1309548460 ps
CPU time 8 seconds
Started Sep 04 02:59:32 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 230244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659002963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.659002963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.3345320769
Short name T563
Test name
Test status
Simulation time 199196794 ps
CPU time 2.87 seconds
Started Sep 04 02:59:29 AM UTC 24
Finished Sep 04 02:59:33 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345320769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3345320769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.2498487863
Short name T168
Test name
Test status
Simulation time 818294619 ps
CPU time 17.55 seconds
Started Sep 04 02:59:33 AM UTC 24
Finished Sep 04 02:59:52 AM UTC 24
Peak memory 232452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2498487863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymg
r_stress_all_with_rand_reset.2498487863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.544959503
Short name T283
Test name
Test status
Simulation time 72959374 ps
CPU time 5.02 seconds
Started Sep 04 02:59:32 AM UTC 24
Finished Sep 04 02:59:38 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544959503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.544959503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.231813931
Short name T574
Test name
Test status
Simulation time 590805218 ps
CPU time 4.79 seconds
Started Sep 04 02:59:32 AM UTC 24
Finished Sep 04 02:59:38 AM UTC 24
Peak memory 219676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231813931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.231813931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.1562312244
Short name T579
Test name
Test status
Simulation time 20592330 ps
CPU time 1.12 seconds
Started Sep 04 02:59:38 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562312244 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1562312244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.764228843
Short name T255
Test name
Test status
Simulation time 203012120 ps
CPU time 4.62 seconds
Started Sep 04 02:59:36 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 232612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764228843 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.764228843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.1246364684
Short name T591
Test name
Test status
Simulation time 260581724 ps
CPU time 8.37 seconds
Started Sep 04 02:59:36 AM UTC 24
Finished Sep 04 02:59:45 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246364684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1246364684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.4168862205
Short name T60
Test name
Test status
Simulation time 115462253 ps
CPU time 2.69 seconds
Started Sep 04 02:59:37 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168862205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4168862205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.44734750
Short name T587
Test name
Test status
Simulation time 286867804 ps
CPU time 4.96 seconds
Started Sep 04 02:59:37 AM UTC 24
Finished Sep 04 02:59:43 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44734750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.44734750
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.844311586
Short name T362
Test name
Test status
Simulation time 91289078 ps
CPU time 2.59 seconds
Started Sep 04 02:59:36 AM UTC 24
Finished Sep 04 02:59:39 AM UTC 24
Peak memory 226520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844311586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.844311586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_random.3400200850
Short name T585
Test name
Test status
Simulation time 670277089 ps
CPU time 5.39 seconds
Started Sep 04 02:59:36 AM UTC 24
Finished Sep 04 02:59:42 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400200850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3400200850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.704000567
Short name T352
Test name
Test status
Simulation time 198708574 ps
CPU time 5.68 seconds
Started Sep 04 02:59:34 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704000567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.704000567
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.222380315
Short name T576
Test name
Test status
Simulation time 412169766 ps
CPU time 4.01 seconds
Started Sep 04 02:59:34 AM UTC 24
Finished Sep 04 02:59:39 AM UTC 24
Peak memory 217936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222380315 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.222380315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.4160416433
Short name T577
Test name
Test status
Simulation time 263349589 ps
CPU time 4.59 seconds
Started Sep 04 02:59:34 AM UTC 24
Finished Sep 04 02:59:40 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160416433 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4160416433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.2704451452
Short name T581
Test name
Test status
Simulation time 507252131 ps
CPU time 5.67 seconds
Started Sep 04 02:59:34 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704451452 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2704451452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.3153194873
Short name T583
Test name
Test status
Simulation time 319293928 ps
CPU time 3.06 seconds
Started Sep 04 02:59:37 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153194873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3153194873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.973473374
Short name T575
Test name
Test status
Simulation time 135926669 ps
CPU time 3.18 seconds
Started Sep 04 02:59:34 AM UTC 24
Finished Sep 04 02:59:38 AM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973473374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.973473374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.2972244098
Short name T650
Test name
Test status
Simulation time 1870002369 ps
CPU time 38 seconds
Started Sep 04 02:59:37 AM UTC 24
Finished Sep 04 03:00:17 AM UTC 24
Peak memory 226132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972244098 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2972244098
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.610072312
Short name T586
Test name
Test status
Simulation time 292548319 ps
CPU time 5.32 seconds
Started Sep 04 02:59:36 AM UTC 24
Finished Sep 04 02:59:42 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610072312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.610072312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.3695316510
Short name T582
Test name
Test status
Simulation time 63905737 ps
CPU time 2.98 seconds
Started Sep 04 02:59:37 AM UTC 24
Finished Sep 04 02:59:41 AM UTC 24
Peak memory 218308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695316510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3695316510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.750951200
Short name T594
Test name
Test status
Simulation time 47883321 ps
CPU time 1.21 seconds
Started Sep 04 02:59:44 AM UTC 24
Finished Sep 04 02:59:46 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750951200 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.750951200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.2648085109
Short name T595
Test name
Test status
Simulation time 201445821 ps
CPU time 3.18 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:47 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648085109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2648085109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.487509269
Short name T590
Test name
Test status
Simulation time 151317351 ps
CPU time 1.66 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:45 AM UTC 24
Peak memory 217692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487509269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.487509269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.2703423289
Short name T358
Test name
Test status
Simulation time 71025369 ps
CPU time 3.38 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:47 AM UTC 24
Peak memory 232216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703423289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2703423289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.2288961585
Short name T592
Test name
Test status
Simulation time 91037964 ps
CPU time 2.6 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:46 AM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288961585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2288961585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_random.566433501
Short name T597
Test name
Test status
Simulation time 406847517 ps
CPU time 4.88 seconds
Started Sep 04 02:59:41 AM UTC 24
Finished Sep 04 02:59:47 AM UTC 24
Peak memory 226084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566433501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.566433501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.809962345
Short name T588
Test name
Test status
Simulation time 80861038 ps
CPU time 3.65 seconds
Started Sep 04 02:59:39 AM UTC 24
Finished Sep 04 02:59:43 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809962345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.809962345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.1491623958
Short name T746
Test name
Test status
Simulation time 17780086109 ps
CPU time 73.55 seconds
Started Sep 04 02:59:40 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491623958 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1491623958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.27244914
Short name T589
Test name
Test status
Simulation time 52971688 ps
CPU time 3.65 seconds
Started Sep 04 02:59:40 AM UTC 24
Finished Sep 04 02:59:44 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27244914 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.27244914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.25824111
Short name T596
Test name
Test status
Simulation time 94477936 ps
CPU time 4.78 seconds
Started Sep 04 02:59:41 AM UTC 24
Finished Sep 04 02:59:47 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25824111 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.25824111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.3477807391
Short name T615
Test name
Test status
Simulation time 1318789355 ps
CPU time 14.38 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:58 AM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477807391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3477807391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.1749428930
Short name T584
Test name
Test status
Simulation time 72007304 ps
CPU time 2.65 seconds
Started Sep 04 02:59:39 AM UTC 24
Finished Sep 04 02:59:42 AM UTC 24
Peak memory 217820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749428930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1749428930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.1212067372
Short name T155
Test name
Test status
Simulation time 16666878436 ps
CPU time 66.54 seconds
Started Sep 04 02:59:44 AM UTC 24
Finished Sep 04 03:00:52 AM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212067372 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1212067372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all_with_rand_reset.1677802793
Short name T607
Test name
Test status
Simulation time 194409860 ps
CPU time 8.19 seconds
Started Sep 04 02:59:44 AM UTC 24
Finished Sep 04 02:59:53 AM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1677802793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymg
r_stress_all_with_rand_reset.1677802793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.2846545209
Short name T598
Test name
Test status
Simulation time 713422957 ps
CPU time 3.93 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:47 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846545209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2846545209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.2920149634
Short name T593
Test name
Test status
Simulation time 140191519 ps
CPU time 2.43 seconds
Started Sep 04 02:59:42 AM UTC 24
Finished Sep 04 02:59:46 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920149634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2920149634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.3800161993
Short name T604
Test name
Test status
Simulation time 54778226 ps
CPU time 1.48 seconds
Started Sep 04 02:59:49 AM UTC 24
Finished Sep 04 02:59:52 AM UTC 24
Peak memory 213720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800161993 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3800161993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.1882921933
Short name T425
Test name
Test status
Simulation time 151428456 ps
CPU time 10.08 seconds
Started Sep 04 02:59:47 AM UTC 24
Finished Sep 04 02:59:58 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882921933 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1882921933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.3534699100
Short name T606
Test name
Test status
Simulation time 234683717 ps
CPU time 4.62 seconds
Started Sep 04 02:59:47 AM UTC 24
Finished Sep 04 02:59:52 AM UTC 24
Peak memory 230500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534699100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3534699100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.410591978
Short name T61
Test name
Test status
Simulation time 6112225379 ps
CPU time 51.65 seconds
Started Sep 04 02:59:48 AM UTC 24
Finished Sep 04 03:00:41 AM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410591978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.410591978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.2051193403
Short name T414
Test name
Test status
Simulation time 87188793 ps
CPU time 4.36 seconds
Started Sep 04 02:59:47 AM UTC 24
Finished Sep 04 02:59:52 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051193403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2051193403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_random.1923003520
Short name T603
Test name
Test status
Simulation time 140443568 ps
CPU time 4.13 seconds
Started Sep 04 02:59:46 AM UTC 24
Finished Sep 04 02:59:52 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923003520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1923003520
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.394258268
Short name T602
Test name
Test status
Simulation time 288241360 ps
CPU time 6.16 seconds
Started Sep 04 02:59:44 AM UTC 24
Finished Sep 04 02:59:51 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394258268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.394258268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.1009738852
Short name T600
Test name
Test status
Simulation time 211451392 ps
CPU time 3.54 seconds
Started Sep 04 02:59:45 AM UTC 24
Finished Sep 04 02:59:50 AM UTC 24
Peak memory 218312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009738852 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1009738852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.510362474
Short name T622
Test name
Test status
Simulation time 2493236885 ps
CPU time 18.6 seconds
Started Sep 04 02:59:44 AM UTC 24
Finished Sep 04 03:00:04 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510362474 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.510362474
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.981178105
Short name T601
Test name
Test status
Simulation time 111964766 ps
CPU time 3.72 seconds
Started Sep 04 02:59:45 AM UTC 24
Finished Sep 04 02:59:50 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981178105 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.981178105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.1500992723
Short name T609
Test name
Test status
Simulation time 517339925 ps
CPU time 4.73 seconds
Started Sep 04 02:59:48 AM UTC 24
Finished Sep 04 02:59:54 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500992723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1500992723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.1823858340
Short name T599
Test name
Test status
Simulation time 32120697 ps
CPU time 2.76 seconds
Started Sep 04 02:59:44 AM UTC 24
Finished Sep 04 02:59:48 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823858340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1823858340
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.2058044444
Short name T643
Test name
Test status
Simulation time 2698033711 ps
CPU time 25.03 seconds
Started Sep 04 02:59:48 AM UTC 24
Finished Sep 04 03:00:15 AM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058044444 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2058044444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.2120560490
Short name T384
Test name
Test status
Simulation time 789287935 ps
CPU time 6.11 seconds
Started Sep 04 02:59:47 AM UTC 24
Finished Sep 04 02:59:54 AM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120560490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2120560490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.4178275865
Short name T605
Test name
Test status
Simulation time 124734439 ps
CPU time 3.06 seconds
Started Sep 04 02:59:48 AM UTC 24
Finished Sep 04 02:59:52 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178275865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.4178275865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.3142865083
Short name T614
Test name
Test status
Simulation time 8456044 ps
CPU time 1.22 seconds
Started Sep 04 02:59:56 AM UTC 24
Finished Sep 04 02:59:58 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142865083 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3142865083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.2189981761
Short name T247
Test name
Test status
Simulation time 141927223 ps
CPU time 4.07 seconds
Started Sep 04 02:59:53 AM UTC 24
Finished Sep 04 02:59:58 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189981761 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2189981761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.144093417
Short name T42
Test name
Test status
Simulation time 154953271 ps
CPU time 5.66 seconds
Started Sep 04 02:59:54 AM UTC 24
Finished Sep 04 03:00:01 AM UTC 24
Peak memory 218112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144093417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.144093417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.1301348176
Short name T611
Test name
Test status
Simulation time 32257850 ps
CPU time 1.93 seconds
Started Sep 04 02:59:53 AM UTC 24
Finished Sep 04 02:59:56 AM UTC 24
Peak memory 215708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301348176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1301348176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.2900928691
Short name T616
Test name
Test status
Simulation time 77968591 ps
CPU time 3.77 seconds
Started Sep 04 02:59:53 AM UTC 24
Finished Sep 04 02:59:58 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900928691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2900928691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.2957714198
Short name T619
Test name
Test status
Simulation time 86870044 ps
CPU time 4.61 seconds
Started Sep 04 02:59:54 AM UTC 24
Finished Sep 04 03:00:00 AM UTC 24
Peak memory 223940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957714198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2957714198
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.1379154555
Short name T612
Test name
Test status
Simulation time 182406403 ps
CPU time 3.66 seconds
Started Sep 04 02:59:53 AM UTC 24
Finished Sep 04 02:59:58 AM UTC 24
Peak memory 230184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379154555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1379154555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_random.1865997658
Short name T620
Test name
Test status
Simulation time 247946989 ps
CPU time 9.24 seconds
Started Sep 04 02:59:53 AM UTC 24
Finished Sep 04 03:00:03 AM UTC 24
Peak memory 218028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865997658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1865997658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.1613118377
Short name T641
Test name
Test status
Simulation time 2969547543 ps
CPU time 21.37 seconds
Started Sep 04 02:59:51 AM UTC 24
Finished Sep 04 03:00:13 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613118377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1613118377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.3375055604
Short name T637
Test name
Test status
Simulation time 755974630 ps
CPU time 19.69 seconds
Started Sep 04 02:59:52 AM UTC 24
Finished Sep 04 03:00:13 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375055604 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3375055604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.2142671196
Short name T573
Test name
Test status
Simulation time 1314179771 ps
CPU time 9.81 seconds
Started Sep 04 02:59:51 AM UTC 24
Finished Sep 04 03:00:01 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142671196 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2142671196
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.3899360528
Short name T696
Test name
Test status
Simulation time 21298442769 ps
CPU time 43.55 seconds
Started Sep 04 02:59:53 AM UTC 24
Finished Sep 04 03:00:38 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899360528 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3899360528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.2584262297
Short name T608
Test name
Test status
Simulation time 33028047 ps
CPU time 3.2 seconds
Started Sep 04 02:59:49 AM UTC 24
Finished Sep 04 02:59:54 AM UTC 24
Peak memory 216036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584262297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2584262297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.4194866561
Short name T196
Test name
Test status
Simulation time 2552614625 ps
CPU time 26.89 seconds
Started Sep 04 02:59:56 AM UTC 24
Finished Sep 04 03:00:24 AM UTC 24
Peak memory 232540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4194866561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg
r_stress_all_with_rand_reset.4194866561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.3384928505
Short name T269
Test name
Test status
Simulation time 421262093 ps
CPU time 7.18 seconds
Started Sep 04 02:59:53 AM UTC 24
Finished Sep 04 03:00:01 AM UTC 24
Peak memory 219928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384928505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3384928505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.2157647553
Short name T617
Test name
Test status
Simulation time 185232637 ps
CPU time 2.89 seconds
Started Sep 04 02:59:55 AM UTC 24
Finished Sep 04 02:59:59 AM UTC 24
Peak memory 218152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157647553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2157647553
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.2821144973
Short name T625
Test name
Test status
Simulation time 87502091 ps
CPU time 1.17 seconds
Started Sep 04 03:00:02 AM UTC 24
Finished Sep 04 03:00:07 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821144973 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2821144973
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.411639545
Short name T351
Test name
Test status
Simulation time 490705749 ps
CPU time 4.28 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:05 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411639545 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.411639545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.3366564276
Short name T31
Test name
Test status
Simulation time 186175931 ps
CPU time 6.98 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:12 AM UTC 24
Peak memory 218524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366564276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3366564276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.3727063444
Short name T151
Test name
Test status
Simulation time 604677660 ps
CPU time 5.42 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:07 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727063444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3727063444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.2712097467
Short name T626
Test name
Test status
Simulation time 125262028 ps
CPU time 2.7 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:07 AM UTC 24
Peak memory 226068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712097467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2712097467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.2355273721
Short name T244
Test name
Test status
Simulation time 241458854 ps
CPU time 6.39 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:11 AM UTC 24
Peak memory 217828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355273721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2355273721
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_random.919812491
Short name T328
Test name
Test status
Simulation time 813019192 ps
CPU time 9.38 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:10 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919812491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.919812491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.3843432519
Short name T566
Test name
Test status
Simulation time 57161966 ps
CPU time 2.8 seconds
Started Sep 04 02:59:57 AM UTC 24
Finished Sep 04 03:00:01 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843432519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3843432519
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.9502422
Short name T636
Test name
Test status
Simulation time 1439856939 ps
CPU time 12.7 seconds
Started Sep 04 02:59:58 AM UTC 24
Finished Sep 04 03:00:12 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9502422 -assert nopostproc +UVM_TESTNAME=keymgr_base_t
est +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.9502422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.1979795278
Short name T635
Test name
Test status
Simulation time 2418295503 ps
CPU time 12.46 seconds
Started Sep 04 02:59:58 AM UTC 24
Finished Sep 04 03:00:12 AM UTC 24
Peak memory 218016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979795278 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1979795278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.3022544306
Short name T621
Test name
Test status
Simulation time 177303461 ps
CPU time 2.99 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:04 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022544306 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3022544306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3898767100
Short name T628
Test name
Test status
Simulation time 89546430 ps
CPU time 3.68 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:08 AM UTC 24
Peak memory 220320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898767100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3898767100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.631983300
Short name T618
Test name
Test status
Simulation time 50169072 ps
CPU time 2.44 seconds
Started Sep 04 02:59:57 AM UTC 24
Finished Sep 04 03:00:00 AM UTC 24
Peak memory 217836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631983300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.631983300
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2617813590
Short name T627
Test name
Test status
Simulation time 87103901 ps
CPU time 3.2 seconds
Started Sep 04 03:00:00 AM UTC 24
Finished Sep 04 03:00:08 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617813590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2617813590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.3160278263
Short name T629
Test name
Test status
Simulation time 153342851 ps
CPU time 3.53 seconds
Started Sep 04 03:00:01 AM UTC 24
Finished Sep 04 03:00:09 AM UTC 24
Peak memory 220024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160278263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3160278263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.2904298863
Short name T438
Test name
Test status
Simulation time 35122879 ps
CPU time 1.51 seconds
Started Sep 04 02:57:20 AM UTC 24
Finished Sep 04 02:57:23 AM UTC 24
Peak memory 213728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904298863 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2904298863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.3534109898
Short name T128
Test name
Test status
Simulation time 105426833 ps
CPU time 4.04 seconds
Started Sep 04 02:57:14 AM UTC 24
Finished Sep 04 02:57:19 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534109898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3534109898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.608827757
Short name T54
Test name
Test status
Simulation time 210568208 ps
CPU time 3.23 seconds
Started Sep 04 02:57:15 AM UTC 24
Finished Sep 04 02:57:20 AM UTC 24
Peak memory 224424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608827757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.608827757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.2202888073
Short name T130
Test name
Test status
Simulation time 59947957 ps
CPU time 3.79 seconds
Started Sep 04 02:57:17 AM UTC 24
Finished Sep 04 02:57:21 AM UTC 24
Peak memory 231368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202888073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2202888073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.2924459996
Short name T7
Test name
Test status
Simulation time 307269413 ps
CPU time 10.15 seconds
Started Sep 04 02:57:14 AM UTC 24
Finished Sep 04 02:57:26 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924459996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2924459996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_random.1746471268
Short name T206
Test name
Test status
Simulation time 96099347 ps
CPU time 4.89 seconds
Started Sep 04 02:57:13 AM UTC 24
Finished Sep 04 02:57:19 AM UTC 24
Peak memory 224472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746471268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1746471268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.4122771036
Short name T207
Test name
Test status
Simulation time 65857004 ps
CPU time 3.8 seconds
Started Sep 04 02:57:11 AM UTC 24
Finished Sep 04 02:57:16 AM UTC 24
Peak memory 218084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122771036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4122771036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.718796119
Short name T221
Test name
Test status
Simulation time 588942814 ps
CPU time 9.6 seconds
Started Sep 04 02:57:13 AM UTC 24
Finished Sep 04 02:57:24 AM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718796119 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.718796119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.2388565749
Short name T311
Test name
Test status
Simulation time 4886096609 ps
CPU time 29.5 seconds
Started Sep 04 02:57:12 AM UTC 24
Finished Sep 04 02:57:43 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388565749 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2388565749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.2963153636
Short name T224
Test name
Test status
Simulation time 63878903 ps
CPU time 3.17 seconds
Started Sep 04 02:57:13 AM UTC 24
Finished Sep 04 02:57:17 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963153636 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2963153636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.2418615139
Short name T220
Test name
Test status
Simulation time 96270613 ps
CPU time 3.7 seconds
Started Sep 04 02:57:18 AM UTC 24
Finished Sep 04 02:57:23 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418615139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2418615139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.2436213251
Short name T213
Test name
Test status
Simulation time 1706887126 ps
CPU time 36.24 seconds
Started Sep 04 02:57:10 AM UTC 24
Finished Sep 04 02:57:48 AM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436213251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2436213251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.31842839
Short name T317
Test name
Test status
Simulation time 160146685 ps
CPU time 7.43 seconds
Started Sep 04 02:57:14 AM UTC 24
Finished Sep 04 02:57:23 AM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31842839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.31842839
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.1082288038
Short name T43
Test name
Test status
Simulation time 1707752189 ps
CPU time 6.04 seconds
Started Sep 04 02:57:18 AM UTC 24
Finished Sep 04 02:57:25 AM UTC 24
Peak memory 220328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082288038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1082288038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.575856100
Short name T640
Test name
Test status
Simulation time 23226006 ps
CPU time 1.12 seconds
Started Sep 04 03:00:11 AM UTC 24
Finished Sep 04 03:00:13 AM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575856100 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.575856100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.297065931
Short name T647
Test name
Test status
Simulation time 1269838490 ps
CPU time 5.81 seconds
Started Sep 04 03:00:08 AM UTC 24
Finished Sep 04 03:00:15 AM UTC 24
Peak memory 231228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297065931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.297065931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.809126128
Short name T633
Test name
Test status
Simulation time 52833784 ps
CPU time 2.29 seconds
Started Sep 04 03:00:07 AM UTC 24
Finished Sep 04 03:00:10 AM UTC 24
Peak memory 224200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809126128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.809126128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.4113769271
Short name T742
Test name
Test status
Simulation time 4969331253 ps
CPU time 44.76 seconds
Started Sep 04 03:00:08 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113769271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4113769271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.643753326
Short name T639
Test name
Test status
Simulation time 170633009 ps
CPU time 3.45 seconds
Started Sep 04 03:00:08 AM UTC 24
Finished Sep 04 03:00:13 AM UTC 24
Peak memory 230388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643753326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.643753326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.2858920814
Short name T634
Test name
Test status
Simulation time 97046942 ps
CPU time 3.5 seconds
Started Sep 04 03:00:07 AM UTC 24
Finished Sep 04 03:00:12 AM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858920814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2858920814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_random.869052523
Short name T644
Test name
Test status
Simulation time 376573604 ps
CPU time 7.66 seconds
Started Sep 04 03:00:06 AM UTC 24
Finished Sep 04 03:00:15 AM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869052523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.869052523
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.1412949807
Short name T666
Test name
Test status
Simulation time 859439608 ps
CPU time 19.09 seconds
Started Sep 04 03:00:03 AM UTC 24
Finished Sep 04 03:00:25 AM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412949807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1412949807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.3545133228
Short name T632
Test name
Test status
Simulation time 61665060 ps
CPU time 3.21 seconds
Started Sep 04 03:00:06 AM UTC 24
Finished Sep 04 03:00:10 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545133228 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3545133228
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.1676848953
Short name T642
Test name
Test status
Simulation time 194945367 ps
CPU time 6.93 seconds
Started Sep 04 03:00:06 AM UTC 24
Finished Sep 04 03:00:14 AM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676848953 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1676848953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.607136842
Short name T631
Test name
Test status
Simulation time 51115724 ps
CPU time 2.96 seconds
Started Sep 04 03:00:06 AM UTC 24
Finished Sep 04 03:00:10 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607136842 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.607136842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.1305098112
Short name T645
Test name
Test status
Simulation time 292527963 ps
CPU time 4.25 seconds
Started Sep 04 03:00:10 AM UTC 24
Finished Sep 04 03:00:15 AM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305098112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1305098112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.2149785863
Short name T630
Test name
Test status
Simulation time 47843897 ps
CPU time 3.48 seconds
Started Sep 04 03:00:02 AM UTC 24
Finished Sep 04 03:00:09 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149785863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2149785863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.1649358747
Short name T203
Test name
Test status
Simulation time 1173914737 ps
CPU time 45.53 seconds
Started Sep 04 03:00:11 AM UTC 24
Finished Sep 04 03:00:58 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649358747 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1649358747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all_with_rand_reset.1974807925
Short name T245
Test name
Test status
Simulation time 528279689 ps
CPU time 20.01 seconds
Started Sep 04 03:00:11 AM UTC 24
Finished Sep 04 03:00:32 AM UTC 24
Peak memory 231076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1974807925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymg
r_stress_all_with_rand_reset.1974807925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.3509048411
Short name T638
Test name
Test status
Simulation time 91520819 ps
CPU time 3.57 seconds
Started Sep 04 03:00:08 AM UTC 24
Finished Sep 04 03:00:13 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509048411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3509048411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.3721099093
Short name T646
Test name
Test status
Simulation time 127149894 ps
CPU time 3.19 seconds
Started Sep 04 03:00:11 AM UTC 24
Finished Sep 04 03:00:15 AM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721099093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3721099093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.2377222685
Short name T654
Test name
Test status
Simulation time 20145872 ps
CPU time 1.27 seconds
Started Sep 04 03:00:16 AM UTC 24
Finished Sep 04 03:00:19 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377222685 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2377222685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.1055164278
Short name T424
Test name
Test status
Simulation time 115688851 ps
CPU time 5.08 seconds
Started Sep 04 03:00:14 AM UTC 24
Finished Sep 04 03:00:20 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055164278 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1055164278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.2124610692
Short name T652
Test name
Test status
Simulation time 137466086 ps
CPU time 2.79 seconds
Started Sep 04 03:00:14 AM UTC 24
Finished Sep 04 03:00:18 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124610692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2124610692
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.3066620563
Short name T651
Test name
Test status
Simulation time 28225734 ps
CPU time 2.08 seconds
Started Sep 04 03:00:14 AM UTC 24
Finished Sep 04 03:00:17 AM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066620563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3066620563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.1164460038
Short name T653
Test name
Test status
Simulation time 132880048 ps
CPU time 2.74 seconds
Started Sep 04 03:00:14 AM UTC 24
Finished Sep 04 03:00:18 AM UTC 24
Peak memory 219948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164460038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1164460038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.2933938461
Short name T380
Test name
Test status
Simulation time 90791088 ps
CPU time 5.14 seconds
Started Sep 04 03:00:14 AM UTC 24
Finished Sep 04 03:00:20 AM UTC 24
Peak memory 224240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933938461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2933938461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_random.1401742046
Short name T658
Test name
Test status
Simulation time 502027499 ps
CPU time 6.91 seconds
Started Sep 04 03:00:13 AM UTC 24
Finished Sep 04 03:00:22 AM UTC 24
Peak memory 226120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401742046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1401742046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.2410418555
Short name T715
Test name
Test status
Simulation time 2893533191 ps
CPU time 30.73 seconds
Started Sep 04 03:00:12 AM UTC 24
Finished Sep 04 03:00:44 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410418555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2410418555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.3858307559
Short name T649
Test name
Test status
Simulation time 196523687 ps
CPU time 3.31 seconds
Started Sep 04 03:00:12 AM UTC 24
Finished Sep 04 03:00:17 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858307559 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3858307559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.2936456895
Short name T648
Test name
Test status
Simulation time 50849495 ps
CPU time 3.35 seconds
Started Sep 04 03:00:12 AM UTC 24
Finished Sep 04 03:00:16 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936456895 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2936456895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.2172537137
Short name T670
Test name
Test status
Simulation time 326537633 ps
CPU time 12.69 seconds
Started Sep 04 03:00:12 AM UTC 24
Finished Sep 04 03:00:26 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172537137 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2172537137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.2339791104
Short name T655
Test name
Test status
Simulation time 86022528 ps
CPU time 3.1 seconds
Started Sep 04 03:00:15 AM UTC 24
Finished Sep 04 03:00:19 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339791104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2339791104
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.1829882707
Short name T657
Test name
Test status
Simulation time 683147605 ps
CPU time 7.05 seconds
Started Sep 04 03:00:12 AM UTC 24
Finished Sep 04 03:00:20 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829882707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1829882707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.1408285244
Short name T674
Test name
Test status
Simulation time 990918514 ps
CPU time 11.28 seconds
Started Sep 04 03:00:15 AM UTC 24
Finished Sep 04 03:00:27 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408285244 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1408285244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.996779906
Short name T690
Test name
Test status
Simulation time 535248765 ps
CPU time 21.08 seconds
Started Sep 04 03:00:14 AM UTC 24
Finished Sep 04 03:00:36 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996779906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.996779906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.399525322
Short name T656
Test name
Test status
Simulation time 307067141 ps
CPU time 3.64 seconds
Started Sep 04 03:00:15 AM UTC 24
Finished Sep 04 03:00:20 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399525322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.399525322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.1415950074
Short name T667
Test name
Test status
Simulation time 10814193 ps
CPU time 1.24 seconds
Started Sep 04 03:00:23 AM UTC 24
Finished Sep 04 03:00:25 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415950074 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1415950074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.3702138169
Short name T418
Test name
Test status
Simulation time 650127303 ps
CPU time 4.67 seconds
Started Sep 04 03:00:19 AM UTC 24
Finished Sep 04 03:00:25 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702138169 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3702138169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.3800840197
Short name T36
Test name
Test status
Simulation time 159051415 ps
CPU time 2.28 seconds
Started Sep 04 03:00:21 AM UTC 24
Finished Sep 04 03:00:25 AM UTC 24
Peak memory 226416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800840197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3800840197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.253299832
Short name T661
Test name
Test status
Simulation time 31568858 ps
CPU time 2.05 seconds
Started Sep 04 03:00:19 AM UTC 24
Finished Sep 04 03:00:22 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253299832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.253299832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.2037871583
Short name T668
Test name
Test status
Simulation time 37890358 ps
CPU time 3.37 seconds
Started Sep 04 03:00:21 AM UTC 24
Finished Sep 04 03:00:26 AM UTC 24
Peak memory 230752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037871583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2037871583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.2481262629
Short name T669
Test name
Test status
Simulation time 41683631 ps
CPU time 3.35 seconds
Started Sep 04 03:00:21 AM UTC 24
Finished Sep 04 03:00:26 AM UTC 24
Peak memory 223968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481262629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2481262629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.3850918772
Short name T346
Test name
Test status
Simulation time 174462028 ps
CPU time 5.49 seconds
Started Sep 04 03:00:20 AM UTC 24
Finished Sep 04 03:00:27 AM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850918772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3850918772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_random.2993765391
Short name T665
Test name
Test status
Simulation time 144411559 ps
CPU time 5.66 seconds
Started Sep 04 03:00:18 AM UTC 24
Finished Sep 04 03:00:25 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993765391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2993765391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.2055877517
Short name T662
Test name
Test status
Simulation time 1432870585 ps
CPU time 5.45 seconds
Started Sep 04 03:00:16 AM UTC 24
Finished Sep 04 03:00:23 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055877517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2055877517
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.3193206262
Short name T677
Test name
Test status
Simulation time 3061409463 ps
CPU time 10.6 seconds
Started Sep 04 03:00:18 AM UTC 24
Finished Sep 04 03:00:30 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193206262 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3193206262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.1598561118
Short name T660
Test name
Test status
Simulation time 701589308 ps
CPU time 3.27 seconds
Started Sep 04 03:00:18 AM UTC 24
Finished Sep 04 03:00:22 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598561118 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1598561118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.3074412373
Short name T707
Test name
Test status
Simulation time 6078728158 ps
CPU time 22.21 seconds
Started Sep 04 03:00:18 AM UTC 24
Finished Sep 04 03:00:41 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074412373 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3074412373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.2949797756
Short name T686
Test name
Test status
Simulation time 795833760 ps
CPU time 10.77 seconds
Started Sep 04 03:00:21 AM UTC 24
Finished Sep 04 03:00:33 AM UTC 24
Peak memory 228516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949797756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2949797756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.133536239
Short name T659
Test name
Test status
Simulation time 151703104 ps
CPU time 4.07 seconds
Started Sep 04 03:00:16 AM UTC 24
Finished Sep 04 03:00:22 AM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133536239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.133536239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.2876185493
Short name T154
Test name
Test status
Simulation time 3568050751 ps
CPU time 26.68 seconds
Started Sep 04 03:00:23 AM UTC 24
Finished Sep 04 03:00:51 AM UTC 24
Peak memory 232404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876185493 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2876185493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.2564749678
Short name T673
Test name
Test status
Simulation time 640403552 ps
CPU time 5.9 seconds
Started Sep 04 03:00:20 AM UTC 24
Finished Sep 04 03:00:27 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564749678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2564749678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.2822105700
Short name T664
Test name
Test status
Simulation time 28080876 ps
CPU time 1.69 seconds
Started Sep 04 03:00:21 AM UTC 24
Finished Sep 04 03:00:24 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822105700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2822105700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.231896136
Short name T672
Test name
Test status
Simulation time 16678191 ps
CPU time 1.51 seconds
Started Sep 04 03:00:28 AM UTC 24
Finished Sep 04 03:00:31 AM UTC 24
Peak memory 213724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231896136 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.231896136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.1729702851
Short name T436
Test name
Test status
Simulation time 45223268 ps
CPU time 4.15 seconds
Started Sep 04 03:00:25 AM UTC 24
Finished Sep 04 03:00:30 AM UTC 24
Peak memory 226408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729702851 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1729702851
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.3533654970
Short name T293
Test name
Test status
Simulation time 63244335 ps
CPU time 3.87 seconds
Started Sep 04 03:00:25 AM UTC 24
Finished Sep 04 03:00:30 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533654970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3533654970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.2264155700
Short name T678
Test name
Test status
Simulation time 130770325 ps
CPU time 3.12 seconds
Started Sep 04 03:00:26 AM UTC 24
Finished Sep 04 03:00:30 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264155700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2264155700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.1603366326
Short name T663
Test name
Test status
Simulation time 133430772 ps
CPU time 2.95 seconds
Started Sep 04 03:00:27 AM UTC 24
Finished Sep 04 03:00:31 AM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603366326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1603366326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.4107057152
Short name T241
Test name
Test status
Simulation time 591411005 ps
CPU time 3.65 seconds
Started Sep 04 03:00:25 AM UTC 24
Finished Sep 04 03:00:30 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107057152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4107057152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_random.2487238151
Short name T331
Test name
Test status
Simulation time 791621984 ps
CPU time 7.14 seconds
Started Sep 04 03:00:25 AM UTC 24
Finished Sep 04 03:00:33 AM UTC 24
Peak memory 217848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487238151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2487238151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.2368697803
Short name T671
Test name
Test status
Simulation time 115672365 ps
CPU time 2.82 seconds
Started Sep 04 03:00:23 AM UTC 24
Finished Sep 04 03:00:27 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368697803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2368697803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.1854649759
Short name T679
Test name
Test status
Simulation time 329451541 ps
CPU time 4.97 seconds
Started Sep 04 03:00:24 AM UTC 24
Finished Sep 04 03:00:30 AM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854649759 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1854649759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.2566070702
Short name T675
Test name
Test status
Simulation time 574326138 ps
CPU time 2.74 seconds
Started Sep 04 03:00:24 AM UTC 24
Finished Sep 04 03:00:28 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566070702 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2566070702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.404112394
Short name T676
Test name
Test status
Simulation time 93150917 ps
CPU time 2.19 seconds
Started Sep 04 03:00:25 AM UTC 24
Finished Sep 04 03:00:28 AM UTC 24
Peak memory 217836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404112394 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.404112394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.541123801
Short name T680
Test name
Test status
Simulation time 40717649 ps
CPU time 2.96 seconds
Started Sep 04 03:00:27 AM UTC 24
Finished Sep 04 03:00:31 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541123801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.541123801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.164729550
Short name T780
Test name
Test status
Simulation time 6611617261 ps
CPU time 44.38 seconds
Started Sep 04 03:00:23 AM UTC 24
Finished Sep 04 03:01:09 AM UTC 24
Peak memory 218280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164729550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.164729550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.3079249173
Short name T733
Test name
Test status
Simulation time 2256461290 ps
CPU time 21.74 seconds
Started Sep 04 03:00:27 AM UTC 24
Finished Sep 04 03:00:50 AM UTC 24
Peak memory 230312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079249173 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3079249173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.2462368617
Short name T685
Test name
Test status
Simulation time 297976349 ps
CPU time 6.58 seconds
Started Sep 04 03:00:25 AM UTC 24
Finished Sep 04 03:00:33 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462368617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2462368617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.3532012203
Short name T681
Test name
Test status
Simulation time 359296690 ps
CPU time 4.07 seconds
Started Sep 04 03:00:27 AM UTC 24
Finished Sep 04 03:00:32 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532012203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3532012203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.2869444837
Short name T691
Test name
Test status
Simulation time 32889038 ps
CPU time 1.49 seconds
Started Sep 04 03:00:34 AM UTC 24
Finished Sep 04 03:00:36 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869444837 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2869444837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.38719847
Short name T432
Test name
Test status
Simulation time 47756503 ps
CPU time 4.66 seconds
Started Sep 04 03:00:31 AM UTC 24
Finished Sep 04 03:00:36 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38719847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test
+UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keym
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.38719847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.3157986402
Short name T278
Test name
Test status
Simulation time 461798691 ps
CPU time 3.72 seconds
Started Sep 04 03:00:32 AM UTC 24
Finished Sep 04 03:00:37 AM UTC 24
Peak memory 218292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157986402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3157986402
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.2292530983
Short name T152
Test name
Test status
Simulation time 45311401 ps
CPU time 2.92 seconds
Started Sep 04 03:00:31 AM UTC 24
Finished Sep 04 03:00:35 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292530983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2292530983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.1771363104
Short name T688
Test name
Test status
Simulation time 66305767 ps
CPU time 3.27 seconds
Started Sep 04 03:00:31 AM UTC 24
Finished Sep 04 03:00:35 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771363104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1771363104
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.1826050829
Short name T695
Test name
Test status
Simulation time 100016751 ps
CPU time 4.78 seconds
Started Sep 04 03:00:32 AM UTC 24
Finished Sep 04 03:00:38 AM UTC 24
Peak memory 230952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826050829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1826050829
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.1169340978
Short name T228
Test name
Test status
Simulation time 125320848 ps
CPU time 5.72 seconds
Started Sep 04 03:00:31 AM UTC 24
Finished Sep 04 03:00:38 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169340978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1169340978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_random.326798219
Short name T687
Test name
Test status
Simulation time 184135404 ps
CPU time 4.54 seconds
Started Sep 04 03:00:30 AM UTC 24
Finished Sep 04 03:00:35 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326798219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.326798219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.632035826
Short name T693
Test name
Test status
Simulation time 688403318 ps
CPU time 7.56 seconds
Started Sep 04 03:00:28 AM UTC 24
Finished Sep 04 03:00:37 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632035826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.632035826
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.1142581491
Short name T683
Test name
Test status
Simulation time 531768699 ps
CPU time 3.28 seconds
Started Sep 04 03:00:28 AM UTC 24
Finished Sep 04 03:00:33 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142581491 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1142581491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.743341570
Short name T718
Test name
Test status
Simulation time 470872915 ps
CPU time 16.07 seconds
Started Sep 04 03:00:28 AM UTC 24
Finished Sep 04 03:00:46 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743341570 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.743341570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.3436008362
Short name T699
Test name
Test status
Simulation time 2312153590 ps
CPU time 8.27 seconds
Started Sep 04 03:00:30 AM UTC 24
Finished Sep 04 03:00:39 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436008362 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3436008362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.1143514357
Short name T689
Test name
Test status
Simulation time 28407156 ps
CPU time 2.61 seconds
Started Sep 04 03:00:32 AM UTC 24
Finished Sep 04 03:00:36 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143514357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1143514357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.819795728
Short name T682
Test name
Test status
Simulation time 65176360 ps
CPU time 3.42 seconds
Started Sep 04 03:00:28 AM UTC 24
Finished Sep 04 03:00:33 AM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819795728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.819795728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.1268387010
Short name T830
Test name
Test status
Simulation time 14321854469 ps
CPU time 55.36 seconds
Started Sep 04 03:00:32 AM UTC 24
Finished Sep 04 03:01:29 AM UTC 24
Peak memory 231248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268387010 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1268387010
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.2744805
Short name T743
Test name
Test status
Simulation time 1825037433 ps
CPU time 20.08 seconds
Started Sep 04 03:00:33 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 232712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2744805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_s
tress_all_with_rand_reset.2744805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.3704305205
Short name T701
Test name
Test status
Simulation time 1388716704 ps
CPU time 7.07 seconds
Started Sep 04 03:00:31 AM UTC 24
Finished Sep 04 03:00:39 AM UTC 24
Peak memory 218052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704305205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3704305205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.2563258590
Short name T692
Test name
Test status
Simulation time 129387150 ps
CPU time 3.29 seconds
Started Sep 04 03:00:32 AM UTC 24
Finished Sep 04 03:00:37 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563258590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2563258590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.83447563
Short name T705
Test name
Test status
Simulation time 13843477 ps
CPU time 1.18 seconds
Started Sep 04 03:00:39 AM UTC 24
Finished Sep 04 03:00:41 AM UTC 24
Peak memory 213536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83447563 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.83447563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.3165368317
Short name T712
Test name
Test status
Simulation time 83198569 ps
CPU time 5.03 seconds
Started Sep 04 03:00:37 AM UTC 24
Finished Sep 04 03:00:44 AM UTC 24
Peak memory 218292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165368317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3165368317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.3698718184
Short name T706
Test name
Test status
Simulation time 71665254 ps
CPU time 3.58 seconds
Started Sep 04 03:00:36 AM UTC 24
Finished Sep 04 03:00:41 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698718184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3698718184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.2127323162
Short name T385
Test name
Test status
Simulation time 208326893 ps
CPU time 8.35 seconds
Started Sep 04 03:00:37 AM UTC 24
Finished Sep 04 03:00:47 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127323162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2127323162
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.2489427888
Short name T716
Test name
Test status
Simulation time 539542250 ps
CPU time 5.71 seconds
Started Sep 04 03:00:37 AM UTC 24
Finished Sep 04 03:00:44 AM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489427888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2489427888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.2123198759
Short name T717
Test name
Test status
Simulation time 280358400 ps
CPU time 7.47 seconds
Started Sep 04 03:00:36 AM UTC 24
Finished Sep 04 03:00:45 AM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123198759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2123198759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_random.4130737460
Short name T700
Test name
Test status
Simulation time 228075859 ps
CPU time 3.13 seconds
Started Sep 04 03:00:35 AM UTC 24
Finished Sep 04 03:00:39 AM UTC 24
Peak memory 216028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130737460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4130737460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.52264380
Short name T704
Test name
Test status
Simulation time 383477115 ps
CPU time 5.98 seconds
Started Sep 04 03:00:34 AM UTC 24
Finished Sep 04 03:00:41 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52264380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.52264380
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.2081400266
Short name T703
Test name
Test status
Simulation time 99062056 ps
CPU time 4.55 seconds
Started Sep 04 03:00:35 AM UTC 24
Finished Sep 04 03:00:40 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081400266 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2081400266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.2918293238
Short name T698
Test name
Test status
Simulation time 212295865 ps
CPU time 3.81 seconds
Started Sep 04 03:00:34 AM UTC 24
Finished Sep 04 03:00:39 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918293238 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2918293238
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.515731624
Short name T697
Test name
Test status
Simulation time 25696419 ps
CPU time 2.66 seconds
Started Sep 04 03:00:35 AM UTC 24
Finished Sep 04 03:00:39 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515731624 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.515731624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.3054555595
Short name T708
Test name
Test status
Simulation time 453375853 ps
CPU time 2.71 seconds
Started Sep 04 03:00:37 AM UTC 24
Finished Sep 04 03:00:41 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054555595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3054555595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.278356167
Short name T694
Test name
Test status
Simulation time 166048305 ps
CPU time 2.81 seconds
Started Sep 04 03:00:34 AM UTC 24
Finished Sep 04 03:00:37 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278356167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.278356167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.1646598551
Short name T710
Test name
Test status
Simulation time 130980228 ps
CPU time 3.95 seconds
Started Sep 04 03:00:38 AM UTC 24
Finished Sep 04 03:00:43 AM UTC 24
Peak memory 219932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646598551 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1646598551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all_with_rand_reset.358410096
Short name T725
Test name
Test status
Simulation time 133600096 ps
CPU time 8.45 seconds
Started Sep 04 03:00:39 AM UTC 24
Finished Sep 04 03:00:48 AM UTC 24
Peak memory 232720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=358410096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr
_stress_all_with_rand_reset.358410096
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.2208751165
Short name T709
Test name
Test status
Simulation time 311343383 ps
CPU time 4.16 seconds
Started Sep 04 03:00:37 AM UTC 24
Finished Sep 04 03:00:42 AM UTC 24
Peak memory 224352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208751165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2208751165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.2888613649
Short name T702
Test name
Test status
Simulation time 39473333 ps
CPU time 1.53 seconds
Started Sep 04 03:00:37 AM UTC 24
Finished Sep 04 03:00:40 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888613649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2888613649
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.520281841
Short name T720
Test name
Test status
Simulation time 12373050 ps
CPU time 1.34 seconds
Started Sep 04 03:00:44 AM UTC 24
Finished Sep 04 03:00:46 AM UTC 24
Peak memory 214176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520281841 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.520281841
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3265075909
Short name T433
Test name
Test status
Simulation time 64068069 ps
CPU time 3.57 seconds
Started Sep 04 03:00:40 AM UTC 24
Finished Sep 04 03:00:45 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265075909 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3265075909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.643669959
Short name T713
Test name
Test status
Simulation time 74892866 ps
CPU time 1.62 seconds
Started Sep 04 03:00:41 AM UTC 24
Finished Sep 04 03:00:44 AM UTC 24
Peak memory 215708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643669959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.643669959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.1915652724
Short name T843
Test name
Test status
Simulation time 1759115816 ps
CPU time 50.55 seconds
Started Sep 04 03:00:41 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915652724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1915652724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.527099867
Short name T338
Test name
Test status
Simulation time 303756385 ps
CPU time 4.94 seconds
Started Sep 04 03:00:41 AM UTC 24
Finished Sep 04 03:00:47 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527099867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.527099867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.18628080
Short name T370
Test name
Test status
Simulation time 621718386 ps
CPU time 7.02 seconds
Started Sep 04 03:00:41 AM UTC 24
Finished Sep 04 03:00:49 AM UTC 24
Peak memory 219956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18628080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.18628080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_random.262370123
Short name T721
Test name
Test status
Simulation time 397222133 ps
CPU time 5.26 seconds
Started Sep 04 03:00:40 AM UTC 24
Finished Sep 04 03:00:46 AM UTC 24
Peak memory 218248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262370123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.262370123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.4051133062
Short name T714
Test name
Test status
Simulation time 182525102 ps
CPU time 4.25 seconds
Started Sep 04 03:00:39 AM UTC 24
Finished Sep 04 03:00:44 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051133062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4051133062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.3033065760
Short name T719
Test name
Test status
Simulation time 153140957 ps
CPU time 4.95 seconds
Started Sep 04 03:00:40 AM UTC 24
Finished Sep 04 03:00:46 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033065760 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3033065760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.718004056
Short name T724
Test name
Test status
Simulation time 154721726 ps
CPU time 6.41 seconds
Started Sep 04 03:00:40 AM UTC 24
Finished Sep 04 03:00:47 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718004056 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.718004056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.1940066128
Short name T767
Test name
Test status
Simulation time 4289791808 ps
CPU time 22.56 seconds
Started Sep 04 03:00:40 AM UTC 24
Finished Sep 04 03:01:04 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940066128 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1940066128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.157791627
Short name T722
Test name
Test status
Simulation time 109809318 ps
CPU time 3.27 seconds
Started Sep 04 03:00:43 AM UTC 24
Finished Sep 04 03:00:47 AM UTC 24
Peak memory 225936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157791627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.157791627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.3678199864
Short name T711
Test name
Test status
Simulation time 60338978 ps
CPU time 3.43 seconds
Started Sep 04 03:00:39 AM UTC 24
Finished Sep 04 03:00:43 AM UTC 24
Peak memory 217904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678199864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3678199864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.2815135254
Short name T813
Test name
Test status
Simulation time 5276272966 ps
CPU time 38.02 seconds
Started Sep 04 03:00:43 AM UTC 24
Finished Sep 04 03:01:22 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815135254 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2815135254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all_with_rand_reset.3061702462
Short name T766
Test name
Test status
Simulation time 436790421 ps
CPU time 18.74 seconds
Started Sep 04 03:00:44 AM UTC 24
Finished Sep 04 03:01:04 AM UTC 24
Peak memory 230296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3061702462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymg
r_stress_all_with_rand_reset.3061702462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.2423783820
Short name T731
Test name
Test status
Simulation time 948349439 ps
CPU time 7.28 seconds
Started Sep 04 03:00:41 AM UTC 24
Finished Sep 04 03:00:50 AM UTC 24
Peak memory 224288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423783820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2423783820
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.4059621030
Short name T723
Test name
Test status
Simulation time 726280173 ps
CPU time 3.52 seconds
Started Sep 04 03:00:43 AM UTC 24
Finished Sep 04 03:00:47 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059621030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4059621030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.215473038
Short name T738
Test name
Test status
Simulation time 52143323 ps
CPU time 1.36 seconds
Started Sep 04 03:00:49 AM UTC 24
Finished Sep 04 03:00:51 AM UTC 24
Peak memory 213724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215473038 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.215473038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.358655758
Short name T728
Test name
Test status
Simulation time 34532257 ps
CPU time 2.89 seconds
Started Sep 04 03:00:45 AM UTC 24
Finished Sep 04 03:00:49 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358655758 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.358655758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.2246083576
Short name T240
Test name
Test status
Simulation time 212846058 ps
CPU time 4.13 seconds
Started Sep 04 03:00:48 AM UTC 24
Finished Sep 04 03:00:53 AM UTC 24
Peak memory 228196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246083576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2246083576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.3066969971
Short name T736
Test name
Test status
Simulation time 828241513 ps
CPU time 3.03 seconds
Started Sep 04 03:00:46 AM UTC 24
Finished Sep 04 03:00:51 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066969971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3066969971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.1716474751
Short name T740
Test name
Test status
Simulation time 125816523 ps
CPU time 5.29 seconds
Started Sep 04 03:00:48 AM UTC 24
Finished Sep 04 03:00:54 AM UTC 24
Peak memory 226284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716474751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1716474751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.3430026660
Short name T339
Test name
Test status
Simulation time 375952212 ps
CPU time 4.83 seconds
Started Sep 04 03:00:48 AM UTC 24
Finished Sep 04 03:00:53 AM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430026660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3430026660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.3024846783
Short name T732
Test name
Test status
Simulation time 79253374 ps
CPU time 2.31 seconds
Started Sep 04 03:00:46 AM UTC 24
Finished Sep 04 03:00:50 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024846783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3024846783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_random.2015809165
Short name T735
Test name
Test status
Simulation time 434445801 ps
CPU time 4.17 seconds
Started Sep 04 03:00:45 AM UTC 24
Finished Sep 04 03:00:51 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015809165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2015809165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2773950112
Short name T734
Test name
Test status
Simulation time 106417532 ps
CPU time 4.03 seconds
Started Sep 04 03:00:45 AM UTC 24
Finished Sep 04 03:00:50 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773950112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2773950112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.2959095139
Short name T810
Test name
Test status
Simulation time 1413384780 ps
CPU time 34.9 seconds
Started Sep 04 03:00:45 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959095139 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2959095139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.4281040718
Short name T727
Test name
Test status
Simulation time 288793171 ps
CPU time 2.95 seconds
Started Sep 04 03:00:45 AM UTC 24
Finished Sep 04 03:00:49 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281040718 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4281040718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.4159023130
Short name T730
Test name
Test status
Simulation time 49406776 ps
CPU time 3.47 seconds
Started Sep 04 03:00:45 AM UTC 24
Finished Sep 04 03:00:50 AM UTC 24
Peak memory 215948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159023130 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4159023130
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.1264065631
Short name T739
Test name
Test status
Simulation time 80767880 ps
CPU time 3.99 seconds
Started Sep 04 03:00:48 AM UTC 24
Finished Sep 04 03:00:53 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264065631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1264065631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.1386784136
Short name T726
Test name
Test status
Simulation time 694426955 ps
CPU time 3.91 seconds
Started Sep 04 03:00:44 AM UTC 24
Finished Sep 04 03:00:49 AM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386784136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1386784136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all_with_rand_reset.389235852
Short name T197
Test name
Test status
Simulation time 796316448 ps
CPU time 14.65 seconds
Started Sep 04 03:00:49 AM UTC 24
Finished Sep 04 03:01:05 AM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=389235852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr
_stress_all_with_rand_reset.389235852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.2548659682
Short name T386
Test name
Test status
Simulation time 252997247 ps
CPU time 9 seconds
Started Sep 04 03:00:47 AM UTC 24
Finished Sep 04 03:00:57 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548659682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2548659682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.2291824964
Short name T737
Test name
Test status
Simulation time 44484136 ps
CPU time 1.87 seconds
Started Sep 04 03:00:48 AM UTC 24
Finished Sep 04 03:00:51 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291824964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2291824964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.1687404918
Short name T749
Test name
Test status
Simulation time 42834701 ps
CPU time 1.08 seconds
Started Sep 04 03:00:53 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687404918 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1687404918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.2240797850
Short name T233
Test name
Test status
Simulation time 283969901 ps
CPU time 4.47 seconds
Started Sep 04 03:00:52 AM UTC 24
Finished Sep 04 03:00:57 AM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240797850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2240797850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.70341984
Short name T684
Test name
Test status
Simulation time 45139095 ps
CPU time 1.93 seconds
Started Sep 04 03:00:51 AM UTC 24
Finished Sep 04 03:00:53 AM UTC 24
Peak memory 227644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70341984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.70341984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.374805447
Short name T748
Test name
Test status
Simulation time 57784709 ps
CPU time 3.53 seconds
Started Sep 04 03:00:51 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374805447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.374805447
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.4030429016
Short name T751
Test name
Test status
Simulation time 63530667 ps
CPU time 3.3 seconds
Started Sep 04 03:00:52 AM UTC 24
Finished Sep 04 03:00:56 AM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030429016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4030429016
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.3201784526
Short name T237
Test name
Test status
Simulation time 116848919 ps
CPU time 4.06 seconds
Started Sep 04 03:00:51 AM UTC 24
Finished Sep 04 03:00:56 AM UTC 24
Peak memory 224060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201784526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3201784526
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_random.2672313485
Short name T756
Test name
Test status
Simulation time 218587547 ps
CPU time 7.9 seconds
Started Sep 04 03:00:50 AM UTC 24
Finished Sep 04 03:00:59 AM UTC 24
Peak memory 228132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672313485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2672313485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.2777101131
Short name T747
Test name
Test status
Simulation time 157353619 ps
CPU time 4.86 seconds
Started Sep 04 03:00:49 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777101131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2777101131
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.1657782593
Short name T744
Test name
Test status
Simulation time 70659513 ps
CPU time 3.64 seconds
Started Sep 04 03:00:50 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657782593 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1657782593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.4026491825
Short name T729
Test name
Test status
Simulation time 170373559 ps
CPU time 3.41 seconds
Started Sep 04 03:00:49 AM UTC 24
Finished Sep 04 03:00:54 AM UTC 24
Peak memory 215644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026491825 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4026491825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.1535099371
Short name T754
Test name
Test status
Simulation time 667528394 ps
CPU time 7.05 seconds
Started Sep 04 03:00:50 AM UTC 24
Finished Sep 04 03:00:58 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535099371 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1535099371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.3891117151
Short name T750
Test name
Test status
Simulation time 96768109 ps
CPU time 2.58 seconds
Started Sep 04 03:00:52 AM UTC 24
Finished Sep 04 03:00:56 AM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891117151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3891117151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.1679092019
Short name T741
Test name
Test status
Simulation time 112401572 ps
CPU time 4.09 seconds
Started Sep 04 03:00:49 AM UTC 24
Finished Sep 04 03:00:54 AM UTC 24
Peak memory 215956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679092019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1679092019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.1801069119
Short name T917
Test name
Test status
Simulation time 15900464978 ps
CPU time 174.76 seconds
Started Sep 04 03:00:52 AM UTC 24
Finished Sep 04 03:03:50 AM UTC 24
Peak memory 232268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801069119 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1801069119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.3382857605
Short name T295
Test name
Test status
Simulation time 153379226 ps
CPU time 7.1 seconds
Started Sep 04 03:00:53 AM UTC 24
Finished Sep 04 03:01:01 AM UTC 24
Peak memory 232632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3382857605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg
r_stress_all_with_rand_reset.3382857605
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.2760177381
Short name T752
Test name
Test status
Simulation time 174441121 ps
CPU time 5.57 seconds
Started Sep 04 03:00:51 AM UTC 24
Finished Sep 04 03:00:57 AM UTC 24
Peak memory 228448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760177381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2760177381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.1032596661
Short name T395
Test name
Test status
Simulation time 265623919 ps
CPU time 2.22 seconds
Started Sep 04 03:00:52 AM UTC 24
Finished Sep 04 03:00:55 AM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032596661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1032596661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.3681042491
Short name T758
Test name
Test status
Simulation time 13930572 ps
CPU time 1.2 seconds
Started Sep 04 03:00:58 AM UTC 24
Finished Sep 04 03:01:00 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681042491 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3681042491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.2629363944
Short name T315
Test name
Test status
Simulation time 45988529 ps
CPU time 4.26 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:01 AM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629363944 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2629363944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.1775524981
Short name T382
Test name
Test status
Simulation time 653483444 ps
CPU time 7.45 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:05 AM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775524981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1775524981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1107564655
Short name T156
Test name
Test status
Simulation time 701672880 ps
CPU time 3.39 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:00 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107564655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1107564655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.363188739
Short name T340
Test name
Test status
Simulation time 108694872 ps
CPU time 2.72 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:00 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363188739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.363188739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.411493055
Short name T760
Test name
Test status
Simulation time 202910504 ps
CPU time 3.67 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:01 AM UTC 24
Peak memory 230508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411493055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.411493055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_random.3975551406
Short name T762
Test name
Test status
Simulation time 81872359 ps
CPU time 4.08 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:01 AM UTC 24
Peak memory 216284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975551406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3975551406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.4207947222
Short name T759
Test name
Test status
Simulation time 461185668 ps
CPU time 4.33 seconds
Started Sep 04 03:00:55 AM UTC 24
Finished Sep 04 03:01:00 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207947222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4207947222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.358388245
Short name T850
Test name
Test status
Simulation time 5184795234 ps
CPU time 39.13 seconds
Started Sep 04 03:00:55 AM UTC 24
Finished Sep 04 03:01:35 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358388245 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.358388245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.1437923807
Short name T755
Test name
Test status
Simulation time 145747133 ps
CPU time 3.78 seconds
Started Sep 04 03:00:55 AM UTC 24
Finished Sep 04 03:00:59 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437923807 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1437923807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.3659838690
Short name T757
Test name
Test status
Simulation time 326250737 ps
CPU time 3.6 seconds
Started Sep 04 03:00:55 AM UTC 24
Finished Sep 04 03:00:59 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659838690 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3659838690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.2305053023
Short name T273
Test name
Test status
Simulation time 91753302 ps
CPU time 2.62 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:00 AM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305053023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2305053023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.3126137277
Short name T753
Test name
Test status
Simulation time 240919290 ps
CPU time 3.67 seconds
Started Sep 04 03:00:53 AM UTC 24
Finished Sep 04 03:00:58 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126137277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3126137277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.1427876377
Short name T802
Test name
Test status
Simulation time 911489892 ps
CPU time 22.39 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:20 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427876377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1427876377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/39.keymgr_sync_async_fault_cross.1899519866
Short name T761
Test name
Test status
Simulation time 232024625 ps
CPU time 3.46 seconds
Started Sep 04 03:00:56 AM UTC 24
Finished Sep 04 03:01:01 AM UTC 24
Peak memory 219980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899519866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1899519866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.1145561201
Short name T440
Test name
Test status
Simulation time 55707979 ps
CPU time 1.23 seconds
Started Sep 04 02:57:30 AM UTC 24
Finished Sep 04 02:57:32 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145561201 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1145561201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.3340324689
Short name T131
Test name
Test status
Simulation time 48342427 ps
CPU time 3.27 seconds
Started Sep 04 02:57:24 AM UTC 24
Finished Sep 04 02:57:28 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340324689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3340324689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.2937279234
Short name T53
Test name
Test status
Simulation time 127862865 ps
CPU time 2.54 seconds
Started Sep 04 02:57:25 AM UTC 24
Finished Sep 04 02:57:29 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937279234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2937279234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.2309006195
Short name T257
Test name
Test status
Simulation time 133814807 ps
CPU time 4.5 seconds
Started Sep 04 02:57:26 AM UTC 24
Finished Sep 04 02:57:32 AM UTC 24
Peak memory 231808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309006195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2309006195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.1636002206
Short name T135
Test name
Test status
Simulation time 287615152 ps
CPU time 5.08 seconds
Started Sep 04 02:57:24 AM UTC 24
Finished Sep 04 02:57:30 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636002206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1636002206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_random.2478786568
Short name T392
Test name
Test status
Simulation time 201707214 ps
CPU time 5.74 seconds
Started Sep 04 02:57:23 AM UTC 24
Finished Sep 04 02:57:30 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478786568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2478786568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.640231430
Short name T46
Test name
Test status
Simulation time 1030623760 ps
CPU time 16.58 seconds
Started Sep 04 02:57:29 AM UTC 24
Finished Sep 04 02:57:46 AM UTC 24
Peak memory 262292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640231430 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.640231430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.1512071385
Short name T284
Test name
Test status
Simulation time 44981882 ps
CPU time 3.44 seconds
Started Sep 04 02:57:20 AM UTC 24
Finished Sep 04 02:57:25 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512071385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1512071385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.2107200045
Short name T275
Test name
Test status
Simulation time 138309355 ps
CPU time 5.93 seconds
Started Sep 04 02:57:23 AM UTC 24
Finished Sep 04 02:57:30 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107200045 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2107200045
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.358197457
Short name T439
Test name
Test status
Simulation time 274616145 ps
CPU time 4.8 seconds
Started Sep 04 02:57:21 AM UTC 24
Finished Sep 04 02:57:27 AM UTC 24
Peak memory 218088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358197457 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.358197457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.845768681
Short name T264
Test name
Test status
Simulation time 110026530 ps
CPU time 6.1 seconds
Started Sep 04 02:57:23 AM UTC 24
Finished Sep 04 02:57:30 AM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845768681 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.845768681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.1715767390
Short name T279
Test name
Test status
Simulation time 83498072 ps
CPU time 4.37 seconds
Started Sep 04 02:57:26 AM UTC 24
Finished Sep 04 02:57:32 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715767390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1715767390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.2011530316
Short name T219
Test name
Test status
Simulation time 264793908 ps
CPU time 3.75 seconds
Started Sep 04 02:57:20 AM UTC 24
Finished Sep 04 02:57:25 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011530316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2011530316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.205501592
Short name T212
Test name
Test status
Simulation time 56346803 ps
CPU time 3.79 seconds
Started Sep 04 02:57:25 AM UTC 24
Finished Sep 04 02:57:30 AM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205501592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.205501592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.919457056
Short name T226
Test name
Test status
Simulation time 161674508 ps
CPU time 4.28 seconds
Started Sep 04 02:57:27 AM UTC 24
Finished Sep 04 02:57:32 AM UTC 24
Peak memory 220076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919457056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.919457056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.1645390016
Short name T772
Test name
Test status
Simulation time 117625518 ps
CPU time 1.44 seconds
Started Sep 04 03:01:03 AM UTC 24
Finished Sep 04 03:01:05 AM UTC 24
Peak memory 213692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645390016 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1645390016
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.1390296566
Short name T771
Test name
Test status
Simulation time 155532633 ps
CPU time 3.68 seconds
Started Sep 04 03:01:00 AM UTC 24
Finished Sep 04 03:01:05 AM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390296566 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1390296566
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.29365349
Short name T773
Test name
Test status
Simulation time 187424996 ps
CPU time 3.2 seconds
Started Sep 04 03:01:02 AM UTC 24
Finished Sep 04 03:01:06 AM UTC 24
Peak memory 218648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29365349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.29365349
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.1955850103
Short name T768
Test name
Test status
Simulation time 38499123 ps
CPU time 2.81 seconds
Started Sep 04 03:01:00 AM UTC 24
Finished Sep 04 03:01:04 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955850103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1955850103
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.2841314054
Short name T777
Test name
Test status
Simulation time 305059337 ps
CPU time 5.5 seconds
Started Sep 04 03:01:01 AM UTC 24
Finished Sep 04 03:01:08 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841314054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2841314054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.3712352922
Short name T775
Test name
Test status
Simulation time 152167760 ps
CPU time 4.23 seconds
Started Sep 04 03:01:02 AM UTC 24
Finished Sep 04 03:01:07 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712352922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3712352922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.734680684
Short name T769
Test name
Test status
Simulation time 486727517 ps
CPU time 3.33 seconds
Started Sep 04 03:01:00 AM UTC 24
Finished Sep 04 03:01:05 AM UTC 24
Peak memory 230584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734680684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.734680684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_random.1693277076
Short name T783
Test name
Test status
Simulation time 242792266 ps
CPU time 8.14 seconds
Started Sep 04 03:01:00 AM UTC 24
Finished Sep 04 03:01:09 AM UTC 24
Peak memory 218304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693277076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1693277076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.3902273887
Short name T770
Test name
Test status
Simulation time 133240610 ps
CPU time 4.94 seconds
Started Sep 04 03:00:59 AM UTC 24
Finished Sep 04 03:01:05 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902273887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3902273887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.1570950137
Short name T835
Test name
Test status
Simulation time 4287029252 ps
CPU time 30.05 seconds
Started Sep 04 03:00:59 AM UTC 24
Finished Sep 04 03:01:30 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570950137 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1570950137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.1725948449
Short name T764
Test name
Test status
Simulation time 102434520 ps
CPU time 2.79 seconds
Started Sep 04 03:00:59 AM UTC 24
Finished Sep 04 03:01:03 AM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725948449 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1725948449
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.74283883
Short name T765
Test name
Test status
Simulation time 198241804 ps
CPU time 3.23 seconds
Started Sep 04 03:00:59 AM UTC 24
Finished Sep 04 03:01:03 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74283883 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.74283883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.1850450570
Short name T776
Test name
Test status
Simulation time 487990094 ps
CPU time 5.06 seconds
Started Sep 04 03:01:02 AM UTC 24
Finished Sep 04 03:01:08 AM UTC 24
Peak memory 220032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850450570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1850450570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.1085736036
Short name T763
Test name
Test status
Simulation time 181730067 ps
CPU time 2.85 seconds
Started Sep 04 03:00:58 AM UTC 24
Finished Sep 04 03:01:01 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085736036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1085736036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.1643174462
Short name T912
Test name
Test status
Simulation time 2718362145 ps
CPU time 70.45 seconds
Started Sep 04 03:01:02 AM UTC 24
Finished Sep 04 03:02:14 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643174462 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1643174462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.2498491176
Short name T798
Test name
Test status
Simulation time 2319641008 ps
CPU time 14.91 seconds
Started Sep 04 03:01:01 AM UTC 24
Finished Sep 04 03:01:18 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498491176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2498491176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.2221815403
Short name T784
Test name
Test status
Simulation time 16188656 ps
CPU time 1.2 seconds
Started Sep 04 03:01:07 AM UTC 24
Finished Sep 04 03:01:09 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221815403 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2221815403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.275664804
Short name T428
Test name
Test status
Simulation time 386061520 ps
CPU time 5.36 seconds
Started Sep 04 03:01:04 AM UTC 24
Finished Sep 04 03:01:11 AM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275664804 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.275664804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.4008517901
Short name T24
Test name
Test status
Simulation time 100242920 ps
CPU time 1.82 seconds
Started Sep 04 03:01:06 AM UTC 24
Finished Sep 04 03:01:09 AM UTC 24
Peak memory 217696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008517901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4008517901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.2066483425
Short name T781
Test name
Test status
Simulation time 93417383 ps
CPU time 3.39 seconds
Started Sep 04 03:01:05 AM UTC 24
Finished Sep 04 03:01:09 AM UTC 24
Peak memory 226112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066483425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2066483425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.86989674
Short name T387
Test name
Test status
Simulation time 142493660 ps
CPU time 3.56 seconds
Started Sep 04 03:01:06 AM UTC 24
Finished Sep 04 03:01:11 AM UTC 24
Peak memory 226016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86989674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.86989674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.86389987
Short name T788
Test name
Test status
Simulation time 267993937 ps
CPU time 4.55 seconds
Started Sep 04 03:01:06 AM UTC 24
Finished Sep 04 03:01:11 AM UTC 24
Peak memory 230268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86389987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.86389987
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_random.2841566589
Short name T789
Test name
Test status
Simulation time 161972416 ps
CPU time 6.16 seconds
Started Sep 04 03:01:04 AM UTC 24
Finished Sep 04 03:01:12 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841566589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2841566589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.3232351904
Short name T778
Test name
Test status
Simulation time 128192668 ps
CPU time 3.96 seconds
Started Sep 04 03:01:03 AM UTC 24
Finished Sep 04 03:01:08 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232351904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3232351904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.3429490782
Short name T782
Test name
Test status
Simulation time 118679357 ps
CPU time 3.62 seconds
Started Sep 04 03:01:04 AM UTC 24
Finished Sep 04 03:01:09 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429490782 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3429490782
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.2702575376
Short name T774
Test name
Test status
Simulation time 22769822 ps
CPU time 2.34 seconds
Started Sep 04 03:01:03 AM UTC 24
Finished Sep 04 03:01:06 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702575376 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2702575376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.2847515203
Short name T785
Test name
Test status
Simulation time 90221401 ps
CPU time 2.72 seconds
Started Sep 04 03:01:06 AM UTC 24
Finished Sep 04 03:01:10 AM UTC 24
Peak memory 224240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847515203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2847515203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.3364229011
Short name T745
Test name
Test status
Simulation time 2001195158 ps
CPU time 10.56 seconds
Started Sep 04 03:01:03 AM UTC 24
Finished Sep 04 03:01:15 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364229011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3364229011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.13381688
Short name T268
Test name
Test status
Simulation time 6285168130 ps
CPU time 46.13 seconds
Started Sep 04 03:01:07 AM UTC 24
Finished Sep 04 03:01:55 AM UTC 24
Peak memory 228196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13381688 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.13381688
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.1611177868
Short name T842
Test name
Test status
Simulation time 7200107810 ps
CPU time 24.63 seconds
Started Sep 04 03:01:07 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1611177868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymg
r_stress_all_with_rand_reset.1611177868
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.3977796921
Short name T915
Test name
Test status
Simulation time 16882730522 ps
CPU time 84.82 seconds
Started Sep 04 03:01:06 AM UTC 24
Finished Sep 04 03:02:33 AM UTC 24
Peak memory 218336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977796921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3977796921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.4138036152
Short name T786
Test name
Test status
Simulation time 360580845 ps
CPU time 2.9 seconds
Started Sep 04 03:01:06 AM UTC 24
Finished Sep 04 03:01:10 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138036152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4138036152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.2387696690
Short name T779
Test name
Test status
Simulation time 15189840 ps
CPU time 1.45 seconds
Started Sep 04 03:01:13 AM UTC 24
Finished Sep 04 03:01:15 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387696690 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2387696690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.787041258
Short name T796
Test name
Test status
Simulation time 59322548 ps
CPU time 3.22 seconds
Started Sep 04 03:01:10 AM UTC 24
Finished Sep 04 03:01:14 AM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787041258 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.787041258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.433469974
Short name T794
Test name
Test status
Simulation time 165502482 ps
CPU time 2.67 seconds
Started Sep 04 03:01:10 AM UTC 24
Finished Sep 04 03:01:14 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433469974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.433469974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.3829123530
Short name T59
Test name
Test status
Simulation time 48978676 ps
CPU time 3.41 seconds
Started Sep 04 03:01:11 AM UTC 24
Finished Sep 04 03:01:16 AM UTC 24
Peak memory 230860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829123530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3829123530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.3544298106
Short name T361
Test name
Test status
Simulation time 107210407 ps
CPU time 3.49 seconds
Started Sep 04 03:01:11 AM UTC 24
Finished Sep 04 03:01:16 AM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544298106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3544298106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.2092311082
Short name T321
Test name
Test status
Simulation time 173768541 ps
CPU time 5.44 seconds
Started Sep 04 03:01:10 AM UTC 24
Finished Sep 04 03:01:16 AM UTC 24
Peak memory 230252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092311082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2092311082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_random.3889281318
Short name T795
Test name
Test status
Simulation time 43197752 ps
CPU time 3.21 seconds
Started Sep 04 03:01:10 AM UTC 24
Finished Sep 04 03:01:14 AM UTC 24
Peak memory 216172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889281318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3889281318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.3209055939
Short name T790
Test name
Test status
Simulation time 311193660 ps
CPU time 3.15 seconds
Started Sep 04 03:01:09 AM UTC 24
Finished Sep 04 03:01:13 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209055939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3209055939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.2373986995
Short name T793
Test name
Test status
Simulation time 121294473 ps
CPU time 3.98 seconds
Started Sep 04 03:01:09 AM UTC 24
Finished Sep 04 03:01:14 AM UTC 24
Peak memory 218292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373986995 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2373986995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.3218850514
Short name T792
Test name
Test status
Simulation time 199862706 ps
CPU time 3.64 seconds
Started Sep 04 03:01:09 AM UTC 24
Finished Sep 04 03:01:13 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218850514 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3218850514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.3494872178
Short name T791
Test name
Test status
Simulation time 59849141 ps
CPU time 2.45 seconds
Started Sep 04 03:01:10 AM UTC 24
Finished Sep 04 03:01:13 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494872178 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3494872178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.1143054828
Short name T325
Test name
Test status
Simulation time 132055491 ps
CPU time 4.28 seconds
Started Sep 04 03:01:11 AM UTC 24
Finished Sep 04 03:01:17 AM UTC 24
Peak memory 220324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143054828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1143054828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.551407815
Short name T787
Test name
Test status
Simulation time 81669847 ps
CPU time 2.62 seconds
Started Sep 04 03:01:07 AM UTC 24
Finished Sep 04 03:01:11 AM UTC 24
Peak memory 217904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551407815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.551407815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.1893614028
Short name T822
Test name
Test status
Simulation time 1252958039 ps
CPU time 12.11 seconds
Started Sep 04 03:01:13 AM UTC 24
Finished Sep 04 03:01:26 AM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893614028 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1893614028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.1246888551
Short name T803
Test name
Test status
Simulation time 672659733 ps
CPU time 9.22 seconds
Started Sep 04 03:01:10 AM UTC 24
Finished Sep 04 03:01:20 AM UTC 24
Peak memory 218144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246888551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1246888551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.61007173
Short name T799
Test name
Test status
Simulation time 178981412 ps
CPU time 4.32 seconds
Started Sep 04 03:01:12 AM UTC 24
Finished Sep 04 03:01:18 AM UTC 24
Peak memory 220048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61007173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.61007173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.85044245
Short name T809
Test name
Test status
Simulation time 44665419 ps
CPU time 1.24 seconds
Started Sep 04 03:01:19 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 213452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85044245 -assert nopostproc +UVM_TESTNAME=keymg
r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.85044245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.2416309852
Short name T422
Test name
Test status
Simulation time 1294874136 ps
CPU time 7.23 seconds
Started Sep 04 03:01:15 AM UTC 24
Finished Sep 04 03:01:23 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416309852 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2416309852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.3456802109
Short name T819
Test name
Test status
Simulation time 491952997 ps
CPU time 5.47 seconds
Started Sep 04 03:01:18 AM UTC 24
Finished Sep 04 03:01:24 AM UTC 24
Peak memory 220696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456802109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3456802109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.348629972
Short name T807
Test name
Test status
Simulation time 88859131 ps
CPU time 3.7 seconds
Started Sep 04 03:01:16 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348629972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.348629972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.1932309754
Short name T804
Test name
Test status
Simulation time 109415532 ps
CPU time 3.13 seconds
Started Sep 04 03:01:16 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932309754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1932309754
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.4064161615
Short name T359
Test name
Test status
Simulation time 121089779 ps
CPU time 3.66 seconds
Started Sep 04 03:01:17 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064161615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.4064161615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.3090821339
Short name T812
Test name
Test status
Simulation time 471852465 ps
CPU time 4.6 seconds
Started Sep 04 03:01:16 AM UTC 24
Finished Sep 04 03:01:22 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090821339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3090821339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_random.3402838125
Short name T815
Test name
Test status
Simulation time 675126971 ps
CPU time 6.87 seconds
Started Sep 04 03:01:15 AM UTC 24
Finished Sep 04 03:01:23 AM UTC 24
Peak memory 218000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402838125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3402838125
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.1942668677
Short name T800
Test name
Test status
Simulation time 38746285 ps
CPU time 3.09 seconds
Started Sep 04 03:01:14 AM UTC 24
Finished Sep 04 03:01:18 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942668677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1942668677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.1459855755
Short name T909
Test name
Test status
Simulation time 1649413881 ps
CPU time 42.13 seconds
Started Sep 04 03:01:15 AM UTC 24
Finished Sep 04 03:01:58 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459855755 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1459855755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.3971554837
Short name T818
Test name
Test status
Simulation time 736359085 ps
CPU time 9.02 seconds
Started Sep 04 03:01:14 AM UTC 24
Finished Sep 04 03:01:24 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971554837 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3971554837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.684322966
Short name T806
Test name
Test status
Simulation time 153317884 ps
CPU time 4.92 seconds
Started Sep 04 03:01:15 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684322966 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.684322966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.1192325367
Short name T808
Test name
Test status
Simulation time 40740217 ps
CPU time 2.51 seconds
Started Sep 04 03:01:18 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192325367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1192325367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.1996354645
Short name T801
Test name
Test status
Simulation time 571207042 ps
CPU time 3.54 seconds
Started Sep 04 03:01:14 AM UTC 24
Finished Sep 04 03:01:18 AM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996354645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1996354645
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.628513440
Short name T239
Test name
Test status
Simulation time 5433908333 ps
CPU time 40.12 seconds
Started Sep 04 03:01:18 AM UTC 24
Finished Sep 04 03:01:59 AM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628513440 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.628513440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.32915588
Short name T838
Test name
Test status
Simulation time 360103665 ps
CPU time 12.34 seconds
Started Sep 04 03:01:19 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 232532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=32915588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_
stress_all_with_rand_reset.32915588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.1823001658
Short name T805
Test name
Test status
Simulation time 239016134 ps
CPU time 3.25 seconds
Started Sep 04 03:01:16 AM UTC 24
Finished Sep 04 03:01:21 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823001658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1823001658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.4176620072
Short name T811
Test name
Test status
Simulation time 85610623 ps
CPU time 2.92 seconds
Started Sep 04 03:01:18 AM UTC 24
Finished Sep 04 03:01:22 AM UTC 24
Peak memory 218220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176620072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.4176620072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.3249407281
Short name T825
Test name
Test status
Simulation time 20079954 ps
CPU time 1.07 seconds
Started Sep 04 03:01:24 AM UTC 24
Finished Sep 04 03:01:27 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249407281 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3249407281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.3377409526
Short name T429
Test name
Test status
Simulation time 832576079 ps
CPU time 11.51 seconds
Started Sep 04 03:01:22 AM UTC 24
Finished Sep 04 03:01:34 AM UTC 24
Peak memory 226236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377409526 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3377409526
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.1337190301
Short name T827
Test name
Test status
Simulation time 43146574 ps
CPU time 3.36 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:28 AM UTC 24
Peak memory 220356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337190301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1337190301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.2045186273
Short name T823
Test name
Test status
Simulation time 46099675 ps
CPU time 2.19 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:26 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045186273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2045186273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.3817481111
Short name T63
Test name
Test status
Simulation time 528083599 ps
CPU time 4.64 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:29 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817481111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3817481111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.827738237
Short name T335
Test name
Test status
Simulation time 310881178 ps
CPU time 3.54 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:28 AM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827738237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.827738237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.4216530028
Short name T826
Test name
Test status
Simulation time 288574334 ps
CPU time 3.67 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:28 AM UTC 24
Peak memory 230656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216530028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4216530028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_random.992426962
Short name T821
Test name
Test status
Simulation time 93997750 ps
CPU time 2.73 seconds
Started Sep 04 03:01:22 AM UTC 24
Finished Sep 04 03:01:25 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992426962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.992426962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.3378830231
Short name T816
Test name
Test status
Simulation time 60050645 ps
CPU time 2.9 seconds
Started Sep 04 03:01:19 AM UTC 24
Finished Sep 04 03:01:23 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378830231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3378830231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.3940887687
Short name T824
Test name
Test status
Simulation time 412793577 ps
CPU time 4.38 seconds
Started Sep 04 03:01:20 AM UTC 24
Finished Sep 04 03:01:26 AM UTC 24
Peak memory 216200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940887687 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3940887687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.203796384
Short name T817
Test name
Test status
Simulation time 232044335 ps
CPU time 3.49 seconds
Started Sep 04 03:01:19 AM UTC 24
Finished Sep 04 03:01:24 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203796384 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.203796384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.2545770378
Short name T820
Test name
Test status
Simulation time 42218361 ps
CPU time 2.68 seconds
Started Sep 04 03:01:21 AM UTC 24
Finished Sep 04 03:01:25 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545770378 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2545770378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.667570399
Short name T828
Test name
Test status
Simulation time 417691983 ps
CPU time 4.11 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:28 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667570399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.667570399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.2223598939
Short name T814
Test name
Test status
Simulation time 39593383 ps
CPU time 2.42 seconds
Started Sep 04 03:01:19 AM UTC 24
Finished Sep 04 03:01:23 AM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223598939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2223598939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.118711844
Short name T829
Test name
Test status
Simulation time 1017230975 ps
CPU time 4.48 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:29 AM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118711844 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.118711844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all_with_rand_reset.3462686642
Short name T198
Test name
Test status
Simulation time 1964591296 ps
CPU time 20.27 seconds
Started Sep 04 03:01:24 AM UTC 24
Finished Sep 04 03:01:46 AM UTC 24
Peak memory 230384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3462686642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymg
r_stress_all_with_rand_reset.3462686642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.3283811189
Short name T885
Test name
Test status
Simulation time 826243622 ps
CPU time 24.14 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:49 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283811189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3283811189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.260810604
Short name T840
Test name
Test status
Simulation time 598197661 ps
CPU time 8.1 seconds
Started Sep 04 03:01:23 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 219940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260810604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.260810604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.3405702647
Short name T841
Test name
Test status
Simulation time 21775175 ps
CPU time 1.27 seconds
Started Sep 04 03:01:31 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405702647 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3405702647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.2817498325
Short name T430
Test name
Test status
Simulation time 219545373 ps
CPU time 5.78 seconds
Started Sep 04 03:01:26 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817498325 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2817498325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.4006367644
Short name T854
Test name
Test status
Simulation time 109901204 ps
CPU time 5.2 seconds
Started Sep 04 03:01:29 AM UTC 24
Finished Sep 04 03:01:36 AM UTC 24
Peak memory 231332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006367644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4006367644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.2256111597
Short name T836
Test name
Test status
Simulation time 195153773 ps
CPU time 3.64 seconds
Started Sep 04 03:01:27 AM UTC 24
Finished Sep 04 03:01:32 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256111597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2256111597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.3992997102
Short name T846
Test name
Test status
Simulation time 418229070 ps
CPU time 5.03 seconds
Started Sep 04 03:01:28 AM UTC 24
Finished Sep 04 03:01:34 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992997102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3992997102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.1744469000
Short name T389
Test name
Test status
Simulation time 399654206 ps
CPU time 4.44 seconds
Started Sep 04 03:01:29 AM UTC 24
Finished Sep 04 03:01:35 AM UTC 24
Peak memory 231144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744469000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1744469000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.2281310656
Short name T849
Test name
Test status
Simulation time 1560510004 ps
CPU time 6.73 seconds
Started Sep 04 03:01:27 AM UTC 24
Finished Sep 04 03:01:35 AM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281310656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2281310656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_random.470369286
Short name T844
Test name
Test status
Simulation time 440889649 ps
CPU time 6.4 seconds
Started Sep 04 03:01:26 AM UTC 24
Finished Sep 04 03:01:34 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470369286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.470369286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.2147910783
Short name T832
Test name
Test status
Simulation time 385730211 ps
CPU time 3.35 seconds
Started Sep 04 03:01:25 AM UTC 24
Finished Sep 04 03:01:29 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147910783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2147910783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.3684098366
Short name T833
Test name
Test status
Simulation time 79193178 ps
CPU time 3.55 seconds
Started Sep 04 03:01:25 AM UTC 24
Finished Sep 04 03:01:30 AM UTC 24
Peak memory 218216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684098366 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3684098366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.863816377
Short name T831
Test name
Test status
Simulation time 63611585 ps
CPU time 3.21 seconds
Started Sep 04 03:01:25 AM UTC 24
Finished Sep 04 03:01:29 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863816377 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.863816377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.2414775322
Short name T834
Test name
Test status
Simulation time 118693162 ps
CPU time 2.87 seconds
Started Sep 04 03:01:26 AM UTC 24
Finished Sep 04 03:01:30 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414775322 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2414775322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.3575931479
Short name T296
Test name
Test status
Simulation time 52289542 ps
CPU time 2.48 seconds
Started Sep 04 03:01:29 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 230344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575931479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3575931479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.1268394938
Short name T837
Test name
Test status
Simulation time 216059768 ps
CPU time 6.3 seconds
Started Sep 04 03:01:24 AM UTC 24
Finished Sep 04 03:01:32 AM UTC 24
Peak memory 217892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268394938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1268394938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.1479027758
Short name T918
Test name
Test status
Simulation time 20037569654 ps
CPU time 388.99 seconds
Started Sep 04 03:01:29 AM UTC 24
Finished Sep 04 03:08:04 AM UTC 24
Peak memory 230844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479027758 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1479027758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all_with_rand_reset.2785015538
Short name T365
Test name
Test status
Simulation time 282378847 ps
CPU time 16.35 seconds
Started Sep 04 03:01:30 AM UTC 24
Finished Sep 04 03:01:47 AM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2785015538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymg
r_stress_all_with_rand_reset.2785015538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.3287636574
Short name T839
Test name
Test status
Simulation time 224394987 ps
CPU time 4.26 seconds
Started Sep 04 03:01:27 AM UTC 24
Finished Sep 04 03:01:33 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287636574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3287636574
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.61687890
Short name T845
Test name
Test status
Simulation time 178552256 ps
CPU time 2.88 seconds
Started Sep 04 03:01:29 AM UTC 24
Finished Sep 04 03:01:34 AM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61687890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.61687890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.3444968722
Short name T857
Test name
Test status
Simulation time 14293106 ps
CPU time 1.26 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:01:38 AM UTC 24
Peak memory 213668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444968722 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3444968722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.688879414
Short name T862
Test name
Test status
Simulation time 56234149 ps
CPU time 3.96 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:01:40 AM UTC 24
Peak memory 218160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688879414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.688879414
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.3989509122
Short name T859
Test name
Test status
Simulation time 223824842 ps
CPU time 4.51 seconds
Started Sep 04 03:01:33 AM UTC 24
Finished Sep 04 03:01:39 AM UTC 24
Peak memory 223240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989509122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3989509122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.274491521
Short name T860
Test name
Test status
Simulation time 167492459 ps
CPU time 3.29 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:01:39 AM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274491521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.274491521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.1219978135
Short name T797
Test name
Test status
Simulation time 71500096 ps
CPU time 3.3 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:01:39 AM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219978135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1219978135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.2705406724
Short name T856
Test name
Test status
Simulation time 109499788 ps
CPU time 2.94 seconds
Started Sep 04 03:01:33 AM UTC 24
Finished Sep 04 03:01:37 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705406724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2705406724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_random.4020115971
Short name T855
Test name
Test status
Simulation time 35870289 ps
CPU time 2.71 seconds
Started Sep 04 03:01:33 AM UTC 24
Finished Sep 04 03:01:37 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020115971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4020115971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.2587038024
Short name T853
Test name
Test status
Simulation time 335113239 ps
CPU time 3.86 seconds
Started Sep 04 03:01:31 AM UTC 24
Finished Sep 04 03:01:36 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587038024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2587038024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.2907195834
Short name T852
Test name
Test status
Simulation time 257195858 ps
CPU time 3.38 seconds
Started Sep 04 03:01:31 AM UTC 24
Finished Sep 04 03:01:36 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907195834 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2907195834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.1777684993
Short name T848
Test name
Test status
Simulation time 318811462 ps
CPU time 2.45 seconds
Started Sep 04 03:01:31 AM UTC 24
Finished Sep 04 03:01:35 AM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777684993 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1777684993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.3155260827
Short name T851
Test name
Test status
Simulation time 48589898 ps
CPU time 3.35 seconds
Started Sep 04 03:01:31 AM UTC 24
Finished Sep 04 03:01:36 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155260827 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3155260827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.2810761000
Short name T858
Test name
Test status
Simulation time 59074688 ps
CPU time 2.2 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:01:39 AM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810761000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2810761000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.131611218
Short name T847
Test name
Test status
Simulation time 166374900 ps
CPU time 2.73 seconds
Started Sep 04 03:01:31 AM UTC 24
Finished Sep 04 03:01:35 AM UTC 24
Peak memory 215588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131611218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.131611218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.114406918
Short name T913
Test name
Test status
Simulation time 5278780163 ps
CPU time 42.91 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:02:20 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114406918 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.114406918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all_with_rand_reset.3722248550
Short name T246
Test name
Test status
Simulation time 3870555293 ps
CPU time 27.15 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:02:04 AM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3722248550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymg
r_stress_all_with_rand_reset.3722248550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.1376855201
Short name T914
Test name
Test status
Simulation time 13978375040 ps
CPU time 45.82 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:02:22 AM UTC 24
Peak memory 230396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376855201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1376855201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.4030084099
Short name T861
Test name
Test status
Simulation time 115850940 ps
CPU time 3.59 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:01:40 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030084099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4030084099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.174731819
Short name T870
Test name
Test status
Simulation time 51488403 ps
CPU time 1.11 seconds
Started Sep 04 03:01:40 AM UTC 24
Finished Sep 04 03:01:43 AM UTC 24
Peak memory 213544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174731819 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.174731819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.468630390
Short name T864
Test name
Test status
Simulation time 128904716 ps
CPU time 3.64 seconds
Started Sep 04 03:01:37 AM UTC 24
Finished Sep 04 03:01:41 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468630390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.468630390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.517762631
Short name T872
Test name
Test status
Simulation time 747066924 ps
CPU time 5.2 seconds
Started Sep 04 03:01:37 AM UTC 24
Finished Sep 04 03:01:43 AM UTC 24
Peak memory 226280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517762631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.517762631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.1036111505
Short name T871
Test name
Test status
Simulation time 236920570 ps
CPU time 4.96 seconds
Started Sep 04 03:01:37 AM UTC 24
Finished Sep 04 03:01:43 AM UTC 24
Peak memory 224004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036111505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1036111505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.2119480018
Short name T867
Test name
Test status
Simulation time 92688768 ps
CPU time 4.08 seconds
Started Sep 04 03:01:37 AM UTC 24
Finished Sep 04 03:01:42 AM UTC 24
Peak memory 232592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119480018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2119480018
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_random.3655166604
Short name T873
Test name
Test status
Simulation time 151796596 ps
CPU time 5.67 seconds
Started Sep 04 03:01:36 AM UTC 24
Finished Sep 04 03:01:43 AM UTC 24
Peak memory 230252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655166604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3655166604
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.2875925496
Short name T888
Test name
Test status
Simulation time 513108908 ps
CPU time 11.75 seconds
Started Sep 04 03:01:36 AM UTC 24
Finished Sep 04 03:01:49 AM UTC 24
Peak memory 217772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875925496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2875925496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.2907035777
Short name T865
Test name
Test status
Simulation time 672514550 ps
CPU time 3.86 seconds
Started Sep 04 03:01:36 AM UTC 24
Finished Sep 04 03:01:41 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907035777 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2907035777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.2160817938
Short name T875
Test name
Test status
Simulation time 157450091 ps
CPU time 7.01 seconds
Started Sep 04 03:01:36 AM UTC 24
Finished Sep 04 03:01:45 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160817938 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2160817938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.3251100169
Short name T866
Test name
Test status
Simulation time 57854800 ps
CPU time 4.19 seconds
Started Sep 04 03:01:36 AM UTC 24
Finished Sep 04 03:01:42 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251100169 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3251100169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.2803487548
Short name T869
Test name
Test status
Simulation time 357301092 ps
CPU time 3.07 seconds
Started Sep 04 03:01:38 AM UTC 24
Finished Sep 04 03:01:42 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803487548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2803487548
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.3586500400
Short name T863
Test name
Test status
Simulation time 72876382 ps
CPU time 3.44 seconds
Started Sep 04 03:01:35 AM UTC 24
Finished Sep 04 03:01:40 AM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586500400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3586500400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all.3430226685
Short name T910
Test name
Test status
Simulation time 995603551 ps
CPU time 19.8 seconds
Started Sep 04 03:01:39 AM UTC 24
Finished Sep 04 03:02:00 AM UTC 24
Peak memory 226080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430226685 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3430226685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.1585391763
Short name T907
Test name
Test status
Simulation time 1287941961 ps
CPU time 15.21 seconds
Started Sep 04 03:01:39 AM UTC 24
Finished Sep 04 03:01:56 AM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1585391763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg
r_stress_all_with_rand_reset.1585391763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.3092433072
Short name T889
Test name
Test status
Simulation time 490079510 ps
CPU time 11.87 seconds
Started Sep 04 03:01:37 AM UTC 24
Finished Sep 04 03:01:50 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092433072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3092433072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.1032527608
Short name T868
Test name
Test status
Simulation time 100145543 ps
CPU time 2.92 seconds
Started Sep 04 03:01:38 AM UTC 24
Finished Sep 04 03:01:42 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032527608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1032527608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.2564667067
Short name T880
Test name
Test status
Simulation time 16391313 ps
CPU time 1.1 seconds
Started Sep 04 03:01:45 AM UTC 24
Finished Sep 04 03:01:47 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564667067 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2564667067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.906697457
Short name T417
Test name
Test status
Simulation time 60047185 ps
CPU time 5.56 seconds
Started Sep 04 03:01:42 AM UTC 24
Finished Sep 04 03:01:49 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906697457 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes
t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/key
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.906697457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.3732927770
Short name T887
Test name
Test status
Simulation time 97660881 ps
CPU time 3.48 seconds
Started Sep 04 03:01:44 AM UTC 24
Finished Sep 04 03:01:49 AM UTC 24
Peak memory 230268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732927770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3732927770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.2255960594
Short name T879
Test name
Test status
Simulation time 173208875 ps
CPU time 2.5 seconds
Started Sep 04 03:01:43 AM UTC 24
Finished Sep 04 03:01:47 AM UTC 24
Peak memory 228284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255960594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2255960594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.1951100690
Short name T336
Test name
Test status
Simulation time 29491443 ps
CPU time 2.9 seconds
Started Sep 04 03:01:43 AM UTC 24
Finished Sep 04 03:01:47 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951100690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1951100690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.3853289760
Short name T882
Test name
Test status
Simulation time 83030340 ps
CPU time 3.15 seconds
Started Sep 04 03:01:43 AM UTC 24
Finished Sep 04 03:01:47 AM UTC 24
Peak memory 228160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853289760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3853289760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.3760287728
Short name T881
Test name
Test status
Simulation time 375915839 ps
CPU time 3.24 seconds
Started Sep 04 03:01:43 AM UTC 24
Finished Sep 04 03:01:47 AM UTC 24
Peak memory 230252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760287728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3760287728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_random.1999916904
Short name T894
Test name
Test status
Simulation time 537415085 ps
CPU time 8.94 seconds
Started Sep 04 03:01:42 AM UTC 24
Finished Sep 04 03:01:52 AM UTC 24
Peak memory 228128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999916904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1999916904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.626280328
Short name T876
Test name
Test status
Simulation time 341349661 ps
CPU time 2.93 seconds
Started Sep 04 03:01:40 AM UTC 24
Finished Sep 04 03:01:45 AM UTC 24
Peak memory 216040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626280328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.626280328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.4080507116
Short name T878
Test name
Test status
Simulation time 137259674 ps
CPU time 4.27 seconds
Started Sep 04 03:01:41 AM UTC 24
Finished Sep 04 03:01:46 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080507116 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4080507116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.841709126
Short name T883
Test name
Test status
Simulation time 377888365 ps
CPU time 6.06 seconds
Started Sep 04 03:01:40 AM UTC 24
Finished Sep 04 03:01:48 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841709126 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.841709126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.1657502515
Short name T877
Test name
Test status
Simulation time 44207044 ps
CPU time 2.49 seconds
Started Sep 04 03:01:42 AM UTC 24
Finished Sep 04 03:01:45 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657502515 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1657502515
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.1815743864
Short name T884
Test name
Test status
Simulation time 411876409 ps
CPU time 2.8 seconds
Started Sep 04 03:01:44 AM UTC 24
Finished Sep 04 03:01:48 AM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815743864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1815743864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.2454110924
Short name T874
Test name
Test status
Simulation time 56275489 ps
CPU time 2.26 seconds
Started Sep 04 03:01:40 AM UTC 24
Finished Sep 04 03:01:44 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454110924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2454110924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1950794987
Short name T911
Test name
Test status
Simulation time 2573554680 ps
CPU time 20.79 seconds
Started Sep 04 03:01:44 AM UTC 24
Finished Sep 04 03:02:07 AM UTC 24
Peak memory 230308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950794987 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1950794987
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all_with_rand_reset.3344557911
Short name T908
Test name
Test status
Simulation time 145655606 ps
CPU time 11.88 seconds
Started Sep 04 03:01:45 AM UTC 24
Finished Sep 04 03:01:58 AM UTC 24
Peak memory 230628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3344557911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymg
r_stress_all_with_rand_reset.3344557911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.2335410768
Short name T898
Test name
Test status
Simulation time 1070327517 ps
CPU time 8.33 seconds
Started Sep 04 03:01:43 AM UTC 24
Finished Sep 04 03:01:52 AM UTC 24
Peak memory 230276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335410768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2335410768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.532218629
Short name T886
Test name
Test status
Simulation time 104293717 ps
CPU time 3.37 seconds
Started Sep 04 03:01:44 AM UTC 24
Finished Sep 04 03:01:49 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532218629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.532218629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.4194588525
Short name T895
Test name
Test status
Simulation time 123780650 ps
CPU time 1.07 seconds
Started Sep 04 03:01:50 AM UTC 24
Finished Sep 04 03:01:52 AM UTC 24
Peak memory 213504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194588525 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4194588525
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3075335222
Short name T893
Test name
Test status
Simulation time 144750243 ps
CPU time 3.22 seconds
Started Sep 04 03:01:47 AM UTC 24
Finished Sep 04 03:01:51 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075335222 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3075335222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.4060308201
Short name T901
Test name
Test status
Simulation time 331251602 ps
CPU time 2.94 seconds
Started Sep 04 03:01:49 AM UTC 24
Finished Sep 04 03:01:53 AM UTC 24
Peak memory 232612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060308201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4060308201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.3234267504
Short name T899
Test name
Test status
Simulation time 94035036 ps
CPU time 4.22 seconds
Started Sep 04 03:01:47 AM UTC 24
Finished Sep 04 03:01:53 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234267504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3234267504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.22037909
Short name T903
Test name
Test status
Simulation time 68195940 ps
CPU time 4.3 seconds
Started Sep 04 03:01:49 AM UTC 24
Finished Sep 04 03:01:54 AM UTC 24
Peak memory 220120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22037909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.22037909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.354177335
Short name T900
Test name
Test status
Simulation time 172603316 ps
CPU time 2.9 seconds
Started Sep 04 03:01:49 AM UTC 24
Finished Sep 04 03:01:53 AM UTC 24
Peak memory 224240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354177335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.354177335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.3178997888
Short name T902
Test name
Test status
Simulation time 69213073 ps
CPU time 3.68 seconds
Started Sep 04 03:01:48 AM UTC 24
Finished Sep 04 03:01:53 AM UTC 24
Peak memory 226196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178997888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3178997888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_random.3889761960
Short name T916
Test name
Test status
Simulation time 12931571852 ps
CPU time 51.8 seconds
Started Sep 04 03:01:47 AM UTC 24
Finished Sep 04 03:02:40 AM UTC 24
Peak memory 224176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889761960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3889761960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.3374977015
Short name T890
Test name
Test status
Simulation time 97467112 ps
CPU time 3.68 seconds
Started Sep 04 03:01:46 AM UTC 24
Finished Sep 04 03:01:50 AM UTC 24
Peak memory 218376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374977015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3374977015
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.764356082
Short name T892
Test name
Test status
Simulation time 148950958 ps
CPU time 4.26 seconds
Started Sep 04 03:01:46 AM UTC 24
Finished Sep 04 03:01:51 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764356082 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.764356082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.1812887494
Short name T904
Test name
Test status
Simulation time 752083823 ps
CPU time 7.29 seconds
Started Sep 04 03:01:46 AM UTC 24
Finished Sep 04 03:01:54 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812887494 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1812887494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.669505848
Short name T891
Test name
Test status
Simulation time 186498686 ps
CPU time 3.86 seconds
Started Sep 04 03:01:46 AM UTC 24
Finished Sep 04 03:01:51 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669505848 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.669505848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.3722761960
Short name T897
Test name
Test status
Simulation time 55029201 ps
CPU time 2.59 seconds
Started Sep 04 03:01:49 AM UTC 24
Finished Sep 04 03:01:52 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722761960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3722761960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.3417892211
Short name T896
Test name
Test status
Simulation time 197194862 ps
CPU time 6.38 seconds
Started Sep 04 03:01:45 AM UTC 24
Finished Sep 04 03:01:52 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417892211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3417892211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.1899313621
Short name T324
Test name
Test status
Simulation time 1738996148 ps
CPU time 54.73 seconds
Started Sep 04 03:01:50 AM UTC 24
Finished Sep 04 03:02:46 AM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899313621 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1899313621
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.962616180
Short name T905
Test name
Test status
Simulation time 120099232 ps
CPU time 5.15 seconds
Started Sep 04 03:01:49 AM UTC 24
Finished Sep 04 03:01:55 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962616180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.962616180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.276447190
Short name T906
Test name
Test status
Simulation time 67740575 ps
CPU time 3.9 seconds
Started Sep 04 03:01:50 AM UTC 24
Finished Sep 04 03:01:55 AM UTC 24
Peak memory 217860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276447190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.276447190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.2686042452
Short name T441
Test name
Test status
Simulation time 21324310 ps
CPU time 1.16 seconds
Started Sep 04 02:57:37 AM UTC 24
Finished Sep 04 02:57:40 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686042452 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2686042452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.81227844
Short name T144
Test name
Test status
Simulation time 98014993 ps
CPU time 3.55 seconds
Started Sep 04 02:57:32 AM UTC 24
Finished Sep 04 02:57:36 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81227844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.81227844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.4095786768
Short name T136
Test name
Test status
Simulation time 130510251 ps
CPU time 4.56 seconds
Started Sep 04 02:57:32 AM UTC 24
Finished Sep 04 02:57:37 AM UTC 24
Peak memory 219976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095786768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4095786768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_random.4289506981
Short name T290
Test name
Test status
Simulation time 1994756973 ps
CPU time 23.13 seconds
Started Sep 04 02:57:31 AM UTC 24
Finished Sep 04 02:57:56 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289506981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4289506981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.2052014240
Short name T105
Test name
Test status
Simulation time 210049435 ps
CPU time 3.99 seconds
Started Sep 04 02:57:30 AM UTC 24
Finished Sep 04 02:57:35 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052014240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2052014240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.506946337
Short name T222
Test name
Test status
Simulation time 467022332 ps
CPU time 3.05 seconds
Started Sep 04 02:57:30 AM UTC 24
Finished Sep 04 02:57:34 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506946337 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.506946337
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.1281197323
Short name T407
Test name
Test status
Simulation time 2646739223 ps
CPU time 33.96 seconds
Started Sep 04 02:57:30 AM UTC 24
Finished Sep 04 02:58:06 AM UTC 24
Peak memory 218016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281197323 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1281197323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.3917762140
Short name T322
Test name
Test status
Simulation time 30708307 ps
CPU time 3.1 seconds
Started Sep 04 02:57:30 AM UTC 24
Finished Sep 04 02:57:35 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917762140 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3917762140
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.1300557000
Short name T216
Test name
Test status
Simulation time 92553453 ps
CPU time 5.11 seconds
Started Sep 04 02:57:35 AM UTC 24
Finished Sep 04 02:57:41 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300557000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1300557000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.1424964006
Short name T210
Test name
Test status
Simulation time 212162198 ps
CPU time 5.83 seconds
Started Sep 04 02:57:30 AM UTC 24
Finished Sep 04 02:57:37 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424964006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1424964006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.3267641305
Short name T75
Test name
Test status
Simulation time 386058240 ps
CPU time 8.64 seconds
Started Sep 04 02:57:35 AM UTC 24
Finished Sep 04 02:57:45 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267641305 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3267641305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.1720109393
Short name T76
Test name
Test status
Simulation time 858238927 ps
CPU time 8.73 seconds
Started Sep 04 02:57:36 AM UTC 24
Finished Sep 04 02:57:46 AM UTC 24
Peak memory 232644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1720109393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr
_stress_all_with_rand_reset.1720109393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.2609156052
Short name T288
Test name
Test status
Simulation time 270143797 ps
CPU time 4.82 seconds
Started Sep 04 02:57:33 AM UTC 24
Finished Sep 04 02:57:39 AM UTC 24
Peak memory 218272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609156052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2609156052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.3857655234
Short name T167
Test name
Test status
Simulation time 165890311 ps
CPU time 4.46 seconds
Started Sep 04 02:57:35 AM UTC 24
Finished Sep 04 02:57:41 AM UTC 24
Peak memory 219936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857655234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3857655234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.1707800843
Short name T442
Test name
Test status
Simulation time 35167754 ps
CPU time 1.05 seconds
Started Sep 04 02:57:46 AM UTC 24
Finished Sep 04 02:57:48 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707800843 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1707800843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_custom_cm.52715684
Short name T127
Test name
Test status
Simulation time 84568561 ps
CPU time 3.58 seconds
Started Sep 04 02:57:42 AM UTC 24
Finished Sep 04 02:57:47 AM UTC 24
Peak memory 224704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52715684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.52715684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.1087593513
Short name T218
Test name
Test status
Simulation time 54945307 ps
CPU time 3.75 seconds
Started Sep 04 02:57:41 AM UTC 24
Finished Sep 04 02:57:46 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087593513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1087593513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.3738382360
Short name T55
Test name
Test status
Simulation time 372915230 ps
CPU time 5.07 seconds
Started Sep 04 02:57:42 AM UTC 24
Finished Sep 04 02:57:48 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738382360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3738382360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.598021304
Short name T73
Test name
Test status
Simulation time 78450860 ps
CPU time 2.56 seconds
Started Sep 04 02:57:42 AM UTC 24
Finished Sep 04 02:57:46 AM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598021304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.598021304
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.1577712875
Short name T113
Test name
Test status
Simulation time 99831799 ps
CPU time 6.12 seconds
Started Sep 04 02:57:41 AM UTC 24
Finished Sep 04 02:57:48 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577712875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1577712875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_random.1204883005
Short name T318
Test name
Test status
Simulation time 466662522 ps
CPU time 11.12 seconds
Started Sep 04 02:57:40 AM UTC 24
Finished Sep 04 02:57:52 AM UTC 24
Peak memory 215844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204883005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1204883005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.2104880801
Short name T250
Test name
Test status
Simulation time 408059512 ps
CPU time 3.36 seconds
Started Sep 04 02:57:37 AM UTC 24
Finished Sep 04 02:57:42 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104880801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2104880801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.3707603775
Short name T327
Test name
Test status
Simulation time 79346417 ps
CPU time 2.33 seconds
Started Sep 04 02:57:39 AM UTC 24
Finished Sep 04 02:57:42 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707603775 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3707603775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.4236534478
Short name T265
Test name
Test status
Simulation time 38279310 ps
CPU time 3.42 seconds
Started Sep 04 02:57:38 AM UTC 24
Finished Sep 04 02:57:42 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236534478 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4236534478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.2070933982
Short name T329
Test name
Test status
Simulation time 347854666 ps
CPU time 4.45 seconds
Started Sep 04 02:57:40 AM UTC 24
Finished Sep 04 02:57:45 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070933982 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2070933982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.85442249
Short name T280
Test name
Test status
Simulation time 145859372 ps
CPU time 2.46 seconds
Started Sep 04 02:57:43 AM UTC 24
Finished Sep 04 02:57:46 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85442249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=
keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.85442249
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.1387911534
Short name T410
Test name
Test status
Simulation time 75625678 ps
CPU time 2.33 seconds
Started Sep 04 02:57:37 AM UTC 24
Finished Sep 04 02:57:41 AM UTC 24
Peak memory 215848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387911534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1387911534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.584432052
Short name T217
Test name
Test status
Simulation time 516396562 ps
CPU time 5.51 seconds
Started Sep 04 02:57:44 AM UTC 24
Finished Sep 04 02:57:50 AM UTC 24
Peak memory 216160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584432052 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.584432052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.4126718588
Short name T208
Test name
Test status
Simulation time 4175246688 ps
CPU time 10.58 seconds
Started Sep 04 02:57:41 AM UTC 24
Finished Sep 04 02:57:53 AM UTC 24
Peak memory 230232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126718588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.4126718588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.3244912571
Short name T45
Test name
Test status
Simulation time 95716706 ps
CPU time 2.73 seconds
Started Sep 04 02:57:43 AM UTC 24
Finished Sep 04 02:57:46 AM UTC 24
Peak memory 217888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244912571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3244912571
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.986876568
Short name T443
Test name
Test status
Simulation time 12415916 ps
CPU time 1.07 seconds
Started Sep 04 02:57:53 AM UTC 24
Finished Sep 04 02:57:55 AM UTC 24
Peak memory 213596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986876568 -assert nopostproc +UVM_TESTNAME=keym
gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.986876568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.789551172
Short name T35
Test name
Test status
Simulation time 223857583 ps
CPU time 4.39 seconds
Started Sep 04 02:57:50 AM UTC 24
Finished Sep 04 02:57:55 AM UTC 24
Peak memory 231068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789551172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.789551172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.2713923529
Short name T129
Test name
Test status
Simulation time 114888156 ps
CPU time 3.33 seconds
Started Sep 04 02:57:48 AM UTC 24
Finished Sep 04 02:57:53 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713923529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2713923529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.1173994113
Short name T294
Test name
Test status
Simulation time 255800258 ps
CPU time 4.11 seconds
Started Sep 04 02:57:50 AM UTC 24
Finished Sep 04 02:57:55 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173994113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1173994113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.501981704
Short name T390
Test name
Test status
Simulation time 56503188 ps
CPU time 2.81 seconds
Started Sep 04 02:57:50 AM UTC 24
Finished Sep 04 02:57:54 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501981704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.501981704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.1155168584
Short name T147
Test name
Test status
Simulation time 274136448 ps
CPU time 6.56 seconds
Started Sep 04 02:57:48 AM UTC 24
Finished Sep 04 02:57:56 AM UTC 24
Peak memory 230184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155168584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1155168584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_random.636843050
Short name T291
Test name
Test status
Simulation time 189714068 ps
CPU time 5.48 seconds
Started Sep 04 02:57:47 AM UTC 24
Finished Sep 04 02:57:54 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636843050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.636843050
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.1226806269
Short name T266
Test name
Test status
Simulation time 520011415 ps
CPU time 3.88 seconds
Started Sep 04 02:57:47 AM UTC 24
Finished Sep 04 02:57:52 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226806269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1226806269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.1592694854
Short name T312
Test name
Test status
Simulation time 138670952 ps
CPU time 3.66 seconds
Started Sep 04 02:57:47 AM UTC 24
Finished Sep 04 02:57:52 AM UTC 24
Peak memory 217988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592694854 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1592694854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.3893264106
Short name T381
Test name
Test status
Simulation time 50509827 ps
CPU time 3.49 seconds
Started Sep 04 02:57:47 AM UTC 24
Finished Sep 04 02:57:52 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893264106 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3893264106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.1019015179
Short name T308
Test name
Test status
Simulation time 972446519 ps
CPU time 3.45 seconds
Started Sep 04 02:57:51 AM UTC 24
Finished Sep 04 02:57:55 AM UTC 24
Peak memory 228192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019015179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1019015179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.399164739
Short name T411
Test name
Test status
Simulation time 327989975 ps
CPU time 7.28 seconds
Started Sep 04 02:57:47 AM UTC 24
Finished Sep 04 02:57:55 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399164739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.399164739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2329378869
Short name T289
Test name
Test status
Simulation time 54488414 ps
CPU time 4.68 seconds
Started Sep 04 02:57:49 AM UTC 24
Finished Sep 04 02:57:54 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329378869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2329378869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.3770647148
Short name T141
Test name
Test status
Simulation time 106345907 ps
CPU time 4.2 seconds
Started Sep 04 02:57:52 AM UTC 24
Finished Sep 04 02:57:57 AM UTC 24
Peak memory 220016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770647148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3770647148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.3111083706
Short name T445
Test name
Test status
Simulation time 30621054 ps
CPU time 1 seconds
Started Sep 04 02:57:59 AM UTC 24
Finished Sep 04 02:58:01 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111083706 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3111083706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.2475084685
Short name T326
Test name
Test status
Simulation time 66228102 ps
CPU time 3.44 seconds
Started Sep 04 02:57:55 AM UTC 24
Finished Sep 04 02:57:59 AM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475084685 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2475084685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.1262809045
Short name T261
Test name
Test status
Simulation time 1036629762 ps
CPU time 3.71 seconds
Started Sep 04 02:57:55 AM UTC 24
Finished Sep 04 02:58:00 AM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262809045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1262809045
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.1484799359
Short name T223
Test name
Test status
Simulation time 500009150 ps
CPU time 7.31 seconds
Started Sep 04 02:57:56 AM UTC 24
Finished Sep 04 02:58:05 AM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484799359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1484799359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.2315571036
Short name T142
Test name
Test status
Simulation time 158900718 ps
CPU time 7.29 seconds
Started Sep 04 02:57:55 AM UTC 24
Finished Sep 04 02:58:03 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315571036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2315571036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_random.2295390473
Short name T383
Test name
Test status
Simulation time 1087096597 ps
CPU time 33 seconds
Started Sep 04 02:57:55 AM UTC 24
Finished Sep 04 02:58:29 AM UTC 24
Peak memory 218252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295390473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2295390473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.1898827996
Short name T160
Test name
Test status
Simulation time 802680704 ps
CPU time 30.9 seconds
Started Sep 04 02:57:53 AM UTC 24
Finished Sep 04 02:58:26 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898827996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1898827996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.265259232
Short name T314
Test name
Test status
Simulation time 344231457 ps
CPU time 2.3 seconds
Started Sep 04 02:57:54 AM UTC 24
Finished Sep 04 02:57:57 AM UTC 24
Peak memory 218328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265259232 -assert nopostproc +UVM_TESTNAME=keymgr_base
_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.265259232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.1882558262
Short name T272
Test name
Test status
Simulation time 115997592 ps
CPU time 4.39 seconds
Started Sep 04 02:57:53 AM UTC 24
Finished Sep 04 02:57:59 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882558262 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1882558262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.1929601341
Short name T276
Test name
Test status
Simulation time 381341330 ps
CPU time 3.61 seconds
Started Sep 04 02:57:54 AM UTC 24
Finished Sep 04 02:57:58 AM UTC 24
Peak memory 217952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929601341 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1929601341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.2269696991
Short name T310
Test name
Test status
Simulation time 43949646 ps
CPU time 2.74 seconds
Started Sep 04 02:57:56 AM UTC 24
Finished Sep 04 02:58:00 AM UTC 24
Peak memory 218276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269696991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2269696991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1882693682
Short name T446
Test name
Test status
Simulation time 230009968 ps
CPU time 6.61 seconds
Started Sep 04 02:57:53 AM UTC 24
Finished Sep 04 02:58:01 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882693682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1882693682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.3120892022
Short name T249
Test name
Test status
Simulation time 427406130 ps
CPU time 4.51 seconds
Started Sep 04 02:57:56 AM UTC 24
Finished Sep 04 02:58:02 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120892022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3120892022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.784009941
Short name T174
Test name
Test status
Simulation time 164934880 ps
CPU time 2.75 seconds
Started Sep 04 02:57:57 AM UTC 24
Finished Sep 04 02:58:01 AM UTC 24
Peak memory 220012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784009941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.784009941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.2403315357
Short name T444
Test name
Test status
Simulation time 38772367 ps
CPU time 1.31 seconds
Started Sep 04 02:58:05 AM UTC 24
Finished Sep 04 02:58:07 AM UTC 24
Peak memory 213540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403315357 -assert nopostproc +UVM_TESTNAME=key
mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2403315357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.2859765339
Short name T298
Test name
Test status
Simulation time 36072886 ps
CPU time 3.8 seconds
Started Sep 04 02:58:00 AM UTC 24
Finished Sep 04 02:58:05 AM UTC 24
Peak memory 224296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859765339 -assert nopostproc +UVM_TESTNAME=keymgr_base_te
st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ke
ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2859765339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.527816055
Short name T10
Test name
Test status
Simulation time 68889673 ps
CPU time 2.22 seconds
Started Sep 04 02:58:03 AM UTC 24
Finished Sep 04 02:58:06 AM UTC 24
Peak memory 232516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527816055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.527816055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_custom_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.3658459967
Short name T132
Test name
Test status
Simulation time 298838487 ps
CPU time 3.32 seconds
Started Sep 04 02:58:00 AM UTC 24
Finished Sep 04 02:58:05 AM UTC 24
Peak memory 216164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658459967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3658459967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.322843338
Short name T259
Test name
Test status
Simulation time 123505732 ps
CPU time 2.98 seconds
Started Sep 04 02:58:02 AM UTC 24
Finished Sep 04 02:58:06 AM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322843338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ
=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.322843338
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.2819635116
Short name T320
Test name
Test status
Simulation time 215981857 ps
CPU time 3.28 seconds
Started Sep 04 02:58:02 AM UTC 24
Finished Sep 04 02:58:06 AM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819635116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2819635116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.3874273730
Short name T143
Test name
Test status
Simulation time 101300175 ps
CPU time 3.86 seconds
Started Sep 04 02:58:02 AM UTC 24
Finished Sep 04 02:58:06 AM UTC 24
Peak memory 218008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874273730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3874273730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_lc_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_random.1895420614
Short name T300
Test name
Test status
Simulation time 90629737 ps
CPU time 5.35 seconds
Started Sep 04 02:58:00 AM UTC 24
Finished Sep 04 02:58:07 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895420614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1895420614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.3622037682
Short name T285
Test name
Test status
Simulation time 138497808 ps
CPU time 2.51 seconds
Started Sep 04 02:57:59 AM UTC 24
Finished Sep 04 02:58:02 AM UTC 24
Peak memory 215908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622037682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3622037682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.2523246422
Short name T363
Test name
Test status
Simulation time 359562854 ps
CPU time 4.42 seconds
Started Sep 04 02:58:00 AM UTC 24
Finished Sep 04 02:58:05 AM UTC 24
Peak memory 217960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523246422 -assert nopostproc +UVM_TESTNAME=keymgr_bas
e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2523246422
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_sideload_aes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.1796976327
Short name T348
Test name
Test status
Simulation time 108411812 ps
CPU time 3.15 seconds
Started Sep 04 02:58:00 AM UTC 24
Finished Sep 04 02:58:04 AM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796976327 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1796976327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.4280152623
Short name T349
Test name
Test status
Simulation time 465207272 ps
CPU time 4.32 seconds
Started Sep 04 02:58:00 AM UTC 24
Finished Sep 04 02:58:06 AM UTC 24
Peak memory 218212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280152623 -assert nopostproc +UVM_TESTNAME=keymgr_ba
se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.4280152623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.3729399427
Short name T270
Test name
Test status
Simulation time 89472920 ps
CPU time 3.42 seconds
Started Sep 04 02:58:03 AM UTC 24
Finished Sep 04 02:58:07 AM UTC 24
Peak memory 224172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729399427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3729399427
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_sideload_protect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.2640972102
Short name T447
Test name
Test status
Simulation time 836778083 ps
CPU time 5.53 seconds
Started Sep 04 02:57:59 AM UTC 24
Finished Sep 04 02:58:05 AM UTC 24
Peak memory 217896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640972102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2640972102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.3200295428
Short name T133
Test name
Test status
Simulation time 32171576 ps
CPU time 2.15 seconds
Started Sep 04 02:58:05 AM UTC 24
Finished Sep 04 02:58:08 AM UTC 24
Peak memory 215836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200295428 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3200295428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all_with_rand_reset.2734470951
Short name T84
Test name
Test status
Simulation time 1199169868 ps
CPU time 10.01 seconds
Started Sep 04 02:58:05 AM UTC 24
Finished Sep 04 02:58:16 AM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2734470951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr
_stress_all_with_rand_reset.2734470951
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.1755927719
Short name T397
Test name
Test status
Simulation time 72793861 ps
CPU time 2.68 seconds
Started Sep 04 02:58:04 AM UTC 24
Finished Sep 04 02:58:08 AM UTC 24
Peak memory 220008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755927719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/keymg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1755927719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest
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