Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4849

1

T1

3

T2

4

T3

5

auto[1]

554

1

T1

1

T17

2

T19

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4849

1

T1

3

T2

4

T3

5

auto[1]

554

1

T1

1

T17

2

T19

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4817

1

T1

4

T2

4

T3

5

auto[1]

586

1

T4

4

T19

1

T20

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4817

1

T1

4

T2

4

T3

5

auto[1]

586

1

T4

4

T19

1

T20

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	443	1			T3	1		T5	2		T34	2
auto[OpGenId]	1147	1			T1	2		T2	2		T3	1
auto[OpGenSwOut]	1184	1			T2	1		T3	1		T5	2
auto[OpGenHwOut]	2557	1			T1	2		T2	1		T3	2
auto[OpDisable]	72	1			T128	1		T126	1		T111	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	443	1			T3	1		T5	2		T34	2
auto[OpGenId]	1147	1			T1	2		T2	2		T3	1
auto[OpGenSwOut]	1184	1			T2	1		T3	1		T5	2
auto[OpGenHwOut]	2557	1			T1	2		T2	1		T3	2
auto[OpDisable]	72	1			T128	1		T126	1		T111	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4867

1

T1

3

T2

4

T3

5

auto[1]

536

1

T1

1

T5

1

T36

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4867

1

T1

3

T2

4

T3

5

auto[1]

536

1

T1

1

T5

1

T36

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5096

1

T1

4

T2

4

T3

5

auto[1]

307

1

T5

3

T75

1

T76

10

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1852	1			T1	2		T2	2		T3	2
auto[1]	692	1			T1	1		T3	1		T4	1
auto[2]	688	1			T2	1		T3	1		T4	1
auto[3]	713	1			T1	1		T2	1		T3	1
auto[4]	399	1			T15	1		T20	1		T68	1
auto[5]	341	1			T4	1		T17	2		T156	1
auto[6]	333	1			T106	1		T68	1		T203	1
auto[7]	385	1			T4	2		T68	1		T156	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1458	1			T4	3		T15	1		T17	2
clear_one[1]	692	1			T1	1		T3	1		T4	1
clear_one[2]	688	1			T2	1		T3	1		T4	1
clear_one[3]	713	1			T1	1		T2	1		T3	1
clear_none	1852	1			T1	2		T2	2		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1001	1			T4	1		T5	2		T34	1
auto[StInit]	666	1			T2	1		T4	1		T5	1
auto[StCreatorRootKey]	569	1			T4	1		T17	1		T19	1
auto[StOwnerIntKey]	517	1			T4	1		T15	1		T17	1
auto[StOwnerKey]	480	1			T4	1		T5	1		T15	1
auto[StDisabled]	1882	1			T1	4		T4	4		T5	4
auto[StInvalid]	288	1			T2	3		T3	5		T125	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1001	1			T4	1		T5	2		T34	1
auto[StInit]	666	1			T2	1		T4	1		T5	1
auto[StCreatorRootKey]	569	1			T4	1		T17	1		T19	1
auto[StOwnerIntKey]	517	1			T4	1		T15	1		T17	1
auto[StOwnerKey]	480	1			T4	1		T5	1		T15	1
auto[StDisabled]	1882	1			T1	4		T4	4		T5	4
auto[StInvalid]	288	1			T2	3		T3	5		T125	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T76	1		T245	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	151	1			T35	1		T198	2		T37	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	152	1			T5	1		T34	1		T203	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	249	1			T4	1		T20	1		T6	1
auto[0]	auto[StInit]	auto[OpAdvance]	51	1			T35	1		T209	1		T130	1
auto[0]	auto[StInit]	auto[OpGenId]	94	1			T106	1		T28	1		T61	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	93	1			T67	1		T76	1		T61	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	180	1			T2	1		T17	1		T68	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	17	1			T130	1		T53	1		T246	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	52	1			T205	1		T207	1		T61	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	58	1			T19	1		T102	1		T64	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	80	1			T4	1		T36	1		T68	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T92	1		T133	1		T247	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T105	1		T61	1		T248	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T15	1		T153	1		T61	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	53	1			T19	1		T34	1		T27	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T111	1		T249	1		T250	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	23	1			T61	1		T251	1		T252	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T34	1		T132	1		T52	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T66	1		T212	1		T61	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	33	1			T111	1		T139	1		T206	1
auto[0]	auto[StDisabled]	auto[OpGenId]	59	1			T1	1		T65	1		T61	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	71	1			T34	1		T155	1		T207	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	176	1			T1	1		T4	2		T5	1
auto[0]	auto[StDisabled]	auto[OpDisable]	17	1			T128	1		T139	2		T206	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	24	1			T3	1		T125	1		T35	1
auto[0]	auto[StInvalid]	auto[OpGenId]	27	1			T2	1		T45	1		T47	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	19	1			T35	1		T93	1		T62	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	22	1			T3	1		T204	1		T253	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T5	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	30	1			T35	1		T23	1		T254	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	32	1			T37	1		T23	1		T255	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	42	1			T203	1		T99	2		T103	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T149	1		T256	1		T257	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T198	1		T24	1		T26	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	10	1			T5	1		T61	1		T129	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	21	1			T258	1		T26	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T107	1		T260	1		T261	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T105	1		T262	1		T263	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T6	1		T27	1		T154	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T17	1		T211	1		T104	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T28	1		T139	1		T264	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T102	1		T86	1		T87	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T111	1		T265	1		T266	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T17	1		T107	1		T61	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T108	1		T267	1		T268	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T75	1		T269	1		T139	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T153	1		T270	1		T260	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T68	1		T156	1		T159	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	25	1			T75	1		T191	1		T139	1
auto[1]	auto[StDisabled]	auto[OpGenId]	37	1			T205	1		T207	1		T132	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T20	1		T108	1		T64	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	145	1			T1	1		T4	1		T17	1
auto[1]	auto[StDisabled]	auto[OpDisable]	14	1			T126	1		T111	1		T133	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T271	1		T272	1		T273	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T62	1		T274	1		T275	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T45	1		T276	1		T277	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T3	1		T93	1		T278	1
auto[2]	auto[StReset]	auto[OpGenId]	17	1			T279	1		T254	1		T280	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	19	1			T200	1		T281	1		T282	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	47	1			T99	1		T204	1		T283	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T260	1		T266	1		T284	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T221	1		T226	1		T187	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	11	1			T282	1		T254	1		T206	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T211	1		T66	1		T285	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T286	1		T287	1		T288	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T132	1		T84	1		T133	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T214	1		T200	1		T289	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T290	1		T90	1		T269	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T226	1		T291	1		T292	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T289	1		T293	1		T294	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T205	1		T214	1		T111	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T4	1		T203	1		T258	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T295	1		T226	1		T186	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T296	1		T297	1		T298	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T111	1		T139	1		T299	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T108	1		T132	1		T300	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	24	1			T34	2		T132	1		T301	1
auto[2]	auto[StDisabled]	auto[OpGenId]	62	1			T281	1		T132	1		T111	3
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T20	1		T102	1		T105	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T17	2		T205	1		T102	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T88	1		T302	1		T303	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T304	1		T305	1		T306	1
auto[2]	auto[StInvalid]	auto[OpGenId]	14	1			T2	1		T47	1		T278	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T3	1		T45	1		T204	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T93	1		T62	1		T307	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T281	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T35	1		T289	1		T308	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	18	1			T37	1		T293	1		T309	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	47	1			T289	1		T310	1		T283	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T44	1		T55	1		T122	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T139	1		T311	1		T51	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	15	1			T279	1		T312	1		T220	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T212	1		T26	1		T217	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T86	1		T246	1		T313	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T194	1		T296	1		T150	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T209	1		T64	1		T293	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T156	1		T215	1		T281	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T295	1		T313	1		T314	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T94	1		T132	1		T254	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T133	1		T89	1		T315	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T159	1		T103	1		T316	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T5	1		T27	1		T317	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T61	1		T85	1		T206	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T210	1		T142	1		T318	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T213	1		T103	1		T290	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	29	1			T301	1		T133	1		T286	1
auto[3]	auto[StDisabled]	auto[OpGenId]	67	1			T1	1		T5	3		T34	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	68	1			T20	1		T290	1		T281	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T156	2		T159	1		T213	1
auto[3]	auto[StDisabled]	auto[OpDisable]	11	1			T131	1		T89	2		T319	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T320	1		T321	2		T322	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T3	1		T60	1		T93	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T2	1		T253	1		T310	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T125	1		T204	1		T323	1
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T219	1		T167	1		T263	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T210	1		T314	1		T315	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	26	1			T203	1		T211	1		T90	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T315	1		T324	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T210	1		T301	1		T325	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	10	1			T126	1		T131	1		T315	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	19	1			T90	1		T283	1		T326	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T190	1		T327	1		T228	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T301	2		T328	1		T296	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T132	1		T301	2		T219	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T159	1		T212	1		T329	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T296	1		T330	1		T331	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T87	1		T312	1		T219	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T207	1		T318	1		T332	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T66	1		T99	1		T285	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T333	3		T331	1		T334	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T20	1		T335	1		T315	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T15	1		T336	1		T337	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T211	1		T104	1		T90	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T27	1		T111	1		T190	1
auto[4]	auto[StDisabled]	auto[OpGenId]	26	1			T203	1		T197	1		T132	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T203	1		T207	1		T214	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	90	1			T68	1		T211	1		T66	1
auto[4]	auto[StDisabled]	auto[OpDisable]	7	1			T150	1		T338	1		T339	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T340	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	8	1			T62	1		T43	1		T341	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T45	1		T253	1		T310	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T342	1		T305	2		T322	2
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T203	1		T93	1		T132	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T46	1		T343	1		T312	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	17	1			T90	1		T258	1		T329	1
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T328	1		T221	1		T226	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T109	1		T344	1		T231	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	8	1			T103	1		T345	1		T346	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T257	1		T334	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T312	1		T347	1		T348	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T349	1		T206	1		T221	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T282	1		T350	1		T351	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T352	2		T325	1		T334	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T353	1		T48	1		T354	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T84	1		T335	1		T221	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T156	1		T213	1		T355	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T356	1		T220	1		T287	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T207	1		T94	1		T352	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T111	1		T357	1		T358	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T4	1		T17	1		T61	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T359	1		T360	1		T150	1
auto[5]	auto[StDisabled]	auto[OpGenId]	32	1			T155	1		T269	1		T352	2
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T201	1		T132	1		T111	2
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T17	1		T104	1		T90	1
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T361	1		T362	1		T146	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T204	1		T320	1		T321	1
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T274	1		T276	1		T308	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T125	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T321	1		T363	1		T364	1
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T365	1		T263	1		T363	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	13	1			T154	1		T64	1		T149	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	24	1			T90	2		T64	1		T329	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T366	1		T367	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	1	1			T368	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T155	1		T167	1		T331	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	16	1			T329	1		T369	1		T370	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T24	1		T61	1		T233	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T296	1		T371	1		T339	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T315	1		T250	2		T372	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T203	1		T213	1		T99	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T373	1		T366	4		T374	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T210	1		T375	1		T376	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T132	1		T139	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T211	1		T61	1		T283	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T76	1		T53	1		T366	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	10	1			T132	1		T343	1		T344	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T102	1		T359	2		T377	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T107	1		T316	1		T326	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	13	1			T76	2		T155	1		T61	1
auto[6]	auto[StDisabled]	auto[OpGenId]	20	1			T251	1		T111	1		T52	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T106	1		T107	1		T343	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	61	1			T68	1		T104	1		T76	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T133	1		T378	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T45	1		T253	1		T365	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T54	1		T276	1		T342	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T253	1		T323	1		T278	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T60	1		T277	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	14	1			T35	1		T47	1		T317	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T379	1		T306	1		T380	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	32	1			T56	1		T283	1		T126	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T48	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	9	1			T25	1		T132	1		T26	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T108	3		T51	1		T303	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T4	1		T381	1		T86	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T76	1		T109	1		T167	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T198	1		T67	1		T76	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T219	1		T382	1		T383	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T28	1		T285	1		T316	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T336	1		T44	1		T339	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T131	1		T84	1		T309	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T384	1		T385	1		T226	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T68	1		T90	1		T269	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T386	1		T387	1		T221	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	9	1			T203	1		T76	3		T132	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T388	1		T250	2		T243	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T76	1		T389	1		T109	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	5	1			T293	1		T246	1		T390	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T194	1		T54	1		T260	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T205	1		T290	1		T94	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T4	1		T156	1		T27	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T391	1		T315	1		T219	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T392	1		T393	1		T272	1
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T125	1		T394	1		T43	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T62	1		T392	1		T365	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T395	1		T274	1		T396	1