Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1458

1

T4

3

T15

1

T17

2

clear_one[1]

auto[0]

auto[0]

auto[0]

422

1

T3

1

T5

2

T17

3

clear_one[1]

auto[0]

auto[0]

auto[1]

104

1

T1

1

T68

1

T75

1

clear_one[1]

auto[0]

auto[1]

auto[0]

125

1

T4

1

T20

1

T213

2

clear_one[1]

auto[0]

auto[1]

auto[1]

41

1

T75

1

T108

1

T111

1

clear_one[2]

auto[0]

auto[0]

auto[0]

390

1

T2

1

T3

1

T4

1

clear_one[2]

auto[0]

auto[0]

auto[1]

134

1

T102

2

T105

1

T90

1

clear_one[2]

auto[1]

auto[0]

auto[0]

130

1

T17

2

T203

1

T389

1

clear_one[2]

auto[1]

auto[0]

auto[1]

34

1

T61

1

T132

1

T111

1

clear_one[3]

auto[0]

auto[0]

auto[0]

408

1

T1

1

T2

1

T3

1

clear_one[3]

auto[0]

auto[1]

auto[0]

128

1

T20

1

T198

1

T213

2

clear_one[3]

auto[1]

auto[0]

auto[0]

131

1

T156

3

T211

1

T103

2

clear_one[3]

auto[1]

auto[1]

auto[0]

46

1

T200

1

T281

1

T279

2

clear_none

auto[0]

auto[0]

auto[0]

1324

1

T1

1

T2

2

T3

2

clear_none

auto[0]

auto[0]

auto[1]

124

1

T5

1

T68

3

T159

3

clear_none

auto[0]

auto[1]

auto[0]

152

1

T4

3

T213

1

T99

2

clear_none

auto[0]

auto[1]

auto[1]

39

1

T105

1

T61

1

T91

1

clear_none

auto[1]

auto[0]

auto[0]

129

1

T1

1

T19

1

T128

1

clear_none

auto[1]

auto[0]

auto[1]

29

1

T75

1

T65

1

T155

1

clear_none

auto[1]

auto[1]

auto[0]

24

1

T19

1

T200

1

T25

1

clear_none

auto[1]

auto[1]

auto[1]

31

1

T36

1

T75

1

T132

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1352	1			T4	3		T15	1		T17	2
clear_all	auto[1]	106	1			T76	9		T107	1		T108	4
clear_one[1]	auto[0]	658	1			T1	1		T3	1		T4	1
clear_one[1]	auto[1]	34	1			T5	1		T107	1		T108	2
clear_one[2]	auto[0]	646	1			T2	1		T3	1		T4	1
clear_one[2]	auto[1]	42	1			T109	2		T301	2		T254	1
clear_one[3]	auto[0]	657	1			T1	1		T2	1		T3	1
clear_one[3]	auto[1]	56	1			T5	2		T281	3		T294	1
clear_none	auto[0]	1783	1			T1	2		T2	2		T3	2
clear_none	auto[1]	69	1			T75	1		T76	1		T108	2