Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11249

1

T1

5

T2

3

T4

9

auto[Attestation]

7902

1

T1

3

T2

1

T4

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2728	1			T1	1		T5	3		T15	1
auto[Aes]	3455	1			T1	2		T5	4		T15	2
auto[Kmac]	3422	1			T2	1		T4	10		T5	3
auto[Otbn]	3507	1			T1	1		T2	1		T5	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7870	1			T1	8		T2	2		T3	1
auto[OpGenId]	6039	1			T1	4		T2	2		T5	13
auto[OpGenSwOut]	6113	1			T1	1		T2	1		T5	9
auto[OpGenHwOut]	6999	1			T1	3		T2	1		T4	10
auto[OpDisable]	149	1			T106	1		T128	1		T101	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10966

1

T1

8

T2

2

T3

1

auto[OpDoneFail]

16204

1

T1

8

T2

4

T4

10

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6553	1			T1	1		T2	1		T3	1
auto[StInit]	3835	1			T1	2		T2	4		T4	2
auto[StCreatorRootKey]	3299	1			T1	2		T2	1		T4	2
auto[StOwnerIntKey]	2874	1			T1	2		T4	2		T5	5
auto[StOwnerKey]	2500	1			T1	2		T4	2		T5	4
auto[StDisabled]	8109	1			T1	7		T4	7		T5	14

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	333	1			T34	1		T125	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	96	1			T19	1		T39	1		T152	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T6	1		T59	1		T152	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T15	1		T100	1		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	75	1			T34	1		T102	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	212	1			T5	1		T20	1		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	355	1			T5	2		T20	2		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	105	1			T19	1		T198	1		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	77	1			T27	2		T67	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T15	1		T199	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	61	1			T61	1		T25	1		T111	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	207	1			T5	2		T15	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	335	1			T5	1		T19	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	99	1			T5	1		T16	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T5	1		T15	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	65	1			T200	1		T201	1		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	56	1			T15	1		T153	1		T92	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	222	1			T34	1		T203	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	329	1			T19	1		T20	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	109	1			T2	1		T24	2		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T19	1		T34	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T205	1		T102	1		T152	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	53	1			T39	1		T61	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	253	1			T15	2		T101	1		T105	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	65	1			T190	2		T133	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T128	1		T6	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	96	1			T61	1		T92	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	82	1			T19	1		T108	2		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T199	1		T111	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	237	1			T20	1		T106	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	107	1			T132	3		T190	3		T139	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	98	1			T19	1		T24	2		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	85	1			T34	1		T39	1		T154	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	77	1			T75	1		T6	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T1	1		T61	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	243	1			T20	1		T198	1		T102	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	69	1			T139	1		T133	2		T206	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T205	1		T67	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T36	1		T128	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T153	1		T130	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T61	2		T92	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	225	1			T20	1		T199	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	92	1			T132	2		T139	3		T206	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T199	1		T101	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T19	1		T209	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T5	1		T102	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T20	1		T210	1		T132	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	228	1			T34	1		T20	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	272	1			T5	1		T34	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	77	1			T60	1		T105	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T1	1		T203	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T19	1		T34	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T102	1		T61	1		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	168	1			T198	1		T27	1		T102	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T106	2		T6	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	105	1			T156	1		T6	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T17	1		T19	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	89	1			T17	1		T19	2		T156	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T211	1		T39	1		T153	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	268	1			T17	2		T128	1		T156	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	459	1			T4	2		T20	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	109	1			T4	1		T24	4		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T4	1		T198	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T4	1		T19	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	91	1			T4	1		T213	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	292	1			T4	3		T20	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	480	1			T34	2		T20	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	119	1			T19	1		T21	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T159	1		T101	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T19	1		T159	1		T67	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T5	1		T68	1		T159	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	289	1			T1	1		T68	3		T75	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	49	1			T132	1		T139	2		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	107	1			T16	1		T203	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T5	1		T128	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T61	1		T25	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T102	1		T214	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T65	1		T102	1		T155	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	62	1			T206	2		T86	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	120	1			T17	1		T75	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	120	1			T19	1		T128	1		T156	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	101	1			T19	2		T66	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T17	1		T20	1		T156	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	284	1			T1	1		T17	2		T156	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	52	1			T132	1		T111	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	143	1			T2	1		T20	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T36	1		T59	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T19	1		T67	2		T105	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	78	1			T99	1		T102	1		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	273	1			T4	1		T20	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	56	1			T132	1		T111	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	130	1			T19	1		T20	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	116	1			T5	1		T36	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T68	1		T75	1		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T5	1		T65	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	283	1			T5	2		T34	1		T68	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	204	1			T15	1		T34	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	663	1			T5	1		T19	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	197	1			T15	1		T199	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	680	1			T5	4		T15	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	215	1			T5	1		T15	2		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	667	1			T5	2		T16	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	203	1			T19	1		T34	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	702	1			T2	1		T15	2		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	221	1			T19	1		T199	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	413	1			T20	1		T106	1		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	203	1			T1	1		T34	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	464	1			T19	1		T20	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T36	1		T128	1		T153	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	420	1			T20	1		T199	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T5	1		T19	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	453	1			T34	1		T20	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	173	1			T1	1		T19	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	535	1			T5	1		T34	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	273	1			T17	2		T19	3		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	872	1			T17	2		T106	2		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	291	1			T4	3		T19	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	878	1			T4	6		T20	2		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	278	1			T5	1		T19	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	906	1			T1	1		T19	1		T34	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T5	1		T128	1		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	343	1			T16	1		T203	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	282	1			T17	1		T19	3		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	484	1			T1	1		T17	3		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	258	1			T19	1		T36	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	484	1			T2	1		T4	1		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	280	1			T5	2		T36	1		T68	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	486	1			T5	2		T19	1		T34	1