Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33301

1

T1

18

T2

44

T3

34

auto[1]

288

1

T5

2

T75

3

T76

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33310	1			T1	18		T2	44		T3	34
auto[134217728:268435455]	8	1			T76	1		T108	1		T260	1
auto[268435456:402653183]	6	1			T76	1		T287	1		T390	1
auto[402653184:536870911]	13	1			T75	1		T281	1		T294	2
auto[536870912:671088639]	11	1			T76	1		T359	1		T423	2
auto[671088640:805306367]	10	1			T294	1		T246	1		T312	1
auto[805306368:939524095]	5	1			T390	1		T424	1		T425	1
auto[939524096:1073741823]	8	1			T109	1		T423	1		T426	2
auto[1073741824:1207959551]	7	1			T75	1		T427	2		T291	2
auto[1207959552:1342177279]	8	1			T428	2		T426	1		T429	1
auto[1342177280:1476395007]	7	1			T254	1		T384	1		T250	1
auto[1476395008:1610612735]	5	1			T107	1		T281	1		T428	1
auto[1610612736:1744830463]	12	1			T76	1		T108	1		T384	1
auto[1744830464:1879048191]	4	1			T313	1		T426	1		T430	1
auto[1879048192:2013265919]	14	1			T108	1		T384	1		T430	3
auto[2013265920:2147483647]	10	1			T5	1		T359	1		T426	1
auto[2147483648:2281701375]	10	1			T301	1		T423	1		T428	1
auto[2281701376:2415919103]	5	1			T108	1		T423	1		T427	1
auto[2415919104:2550136831]	15	1			T108	1		T254	1		T260	1
auto[2550136832:2684354559]	11	1			T108	1		T109	1		T403	1
auto[2684354560:2818572287]	10	1			T260	3		T403	1		T428	1
auto[2818572288:2952790015]	11	1			T246	1		T430	1		T427	1
auto[2952790016:3087007743]	10	1			T108	1		T352	1		T301	1
auto[3087007744:3221225471]	8	1			T108	1		T281	1		T294	1
auto[3221225472:3355443199]	10	1			T108	1		T281	1		T301	1
auto[3355443200:3489660927]	9	1			T108	1		T403	1		T423	2
auto[3489660928:3623878655]	15	1			T404	1		T403	1		T313	1
auto[3623878656:3758096383]	12	1			T76	1		T404	1		T430	2
auto[3758096384:3892314111]	5	1			T384	1		T403	1		T430	1
auto[3892314112:4026531839]	4	1			T260	1		T291	1		T431	1
auto[4026531840:4160749567]	9	1			T75	1		T108	1		T294	1
auto[4160749568:4294967295]	7	1			T352	1		T359	1		T250	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33301	1			T1	18		T2	44		T3	34
auto[0:134217727]	auto[1]	9	1			T5	1		T76	1		T108	1
auto[134217728:268435455]	auto[1]	8	1			T76	1		T108	1		T260	1
auto[268435456:402653183]	auto[1]	6	1			T76	1		T287	1		T390	1
auto[402653184:536870911]	auto[1]	13	1			T75	1		T281	1		T294	2
auto[536870912:671088639]	auto[1]	11	1			T76	1		T359	1		T423	2
auto[671088640:805306367]	auto[1]	10	1			T294	1		T246	1		T312	1
auto[805306368:939524095]	auto[1]	5	1			T390	1		T424	1		T425	1
auto[939524096:1073741823]	auto[1]	8	1			T109	1		T423	1		T426	2
auto[1073741824:1207959551]	auto[1]	7	1			T75	1		T427	2		T291	2
auto[1207959552:1342177279]	auto[1]	8	1			T428	2		T426	1		T429	1
auto[1342177280:1476395007]	auto[1]	7	1			T254	1		T384	1		T250	1
auto[1476395008:1610612735]	auto[1]	5	1			T107	1		T281	1		T428	1
auto[1610612736:1744830463]	auto[1]	12	1			T76	1		T108	1		T384	1
auto[1744830464:1879048191]	auto[1]	4	1			T313	1		T426	1		T430	1
auto[1879048192:2013265919]	auto[1]	14	1			T108	1		T384	1		T430	3
auto[2013265920:2147483647]	auto[1]	10	1			T5	1		T359	1		T426	1
auto[2147483648:2281701375]	auto[1]	10	1			T301	1		T423	1		T428	1
auto[2281701376:2415919103]	auto[1]	5	1			T108	1		T423	1		T427	1
auto[2415919104:2550136831]	auto[1]	15	1			T108	1		T254	1		T260	1
auto[2550136832:2684354559]	auto[1]	11	1			T108	1		T109	1		T403	1
auto[2684354560:2818572287]	auto[1]	10	1			T260	3		T403	1		T428	1
auto[2818572288:2952790015]	auto[1]	11	1			T246	1		T430	1		T427	1
auto[2952790016:3087007743]	auto[1]	10	1			T108	1		T352	1		T301	1
auto[3087007744:3221225471]	auto[1]	8	1			T108	1		T281	1		T294	1
auto[3221225472:3355443199]	auto[1]	10	1			T108	1		T281	1		T301	1
auto[3355443200:3489660927]	auto[1]	9	1			T108	1		T403	1		T423	2
auto[3489660928:3623878655]	auto[1]	15	1			T404	1		T403	1		T313	1
auto[3623878656:3758096383]	auto[1]	12	1			T76	1		T404	1		T430	2
auto[3758096384:3892314111]	auto[1]	5	1			T384	1		T403	1		T430	1
auto[3892314112:4026531839]	auto[1]	4	1			T260	1		T291	1		T431	1
auto[4026531840:4160749567]	auto[1]	9	1			T75	1		T108	1		T294	1
auto[4160749568:4294967295]	auto[1]	7	1			T352	1		T359	1		T250	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1702

1

T2

3

T3

5

T5

2

auto[1]

1825

1

T2

1

T5

2

T15

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T3	1		T36	1		T21	1
auto[134217728:268435455]	106	1			T5	1		T24	1		T130	1
auto[268435456:402653183]	111	1			T6	1		T35	1		T24	1
auto[402653184:536870911]	128	1			T15	1		T20	1		T36	1
auto[536870912:671088639]	107	1			T2	1		T34	1		T56	1
auto[671088640:805306367]	118	1			T34	1		T6	1		T76	1
auto[805306368:939524095]	114	1			T2	1		T106	1		T56	1
auto[939524096:1073741823]	89	1			T101	1		T130	1		T111	1
auto[1073741824:1207959551]	106	1			T198	1		T94	2		T62	1
auto[1207959552:1342177279]	115	1			T3	1		T15	1		T6	3
auto[1342177280:1476395007]	113	1			T24	2		T200	1		T202	1
auto[1476395008:1610612735]	111	1			T3	1		T5	1		T15	1
auto[1610612736:1744830463]	90	1			T75	1		T125	1		T35	1
auto[1744830464:1879048191]	104	1			T2	1		T27	2		T65	1
auto[1879048192:2013265919]	115	1			T15	2		T125	1		T60	1
auto[2013265920:2147483647]	109	1			T5	1		T15	1		T34	1
auto[2147483648:2281701375]	118	1			T198	1		T60	1		T56	1
auto[2281701376:2415919103]	108	1			T20	1		T209	1		T198	1
auto[2415919104:2550136831]	126	1			T5	1		T19	1		T36	1
auto[2550136832:2684354559]	107	1			T21	1		T60	1		T56	1
auto[2684354560:2818572287]	126	1			T19	1		T34	1		T35	1
auto[2818572288:2952790015]	118	1			T20	1		T56	2		T107	1
auto[2952790016:3087007743]	106	1			T27	1		T37	1		T101	1
auto[3087007744:3221225471]	105	1			T3	1		T34	1		T35	1
auto[3221225472:3355443199]	97	1			T20	1		T75	2		T6	1
auto[3355443200:3489660927]	106	1			T15	1		T27	1		T24	1
auto[3489660928:3623878655]	121	1			T106	1		T128	1		T75	2
auto[3623878656:3758096383]	114	1			T128	1		T6	1		T56	1
auto[3758096384:3892314111]	109	1			T20	1		T56	1		T101	1
auto[3892314112:4026531839]	105	1			T20	1		T60	1		T102	1
auto[4026531840:4160749567]	102	1			T2	1		T3	1		T34	1
auto[4160749568:4294967295]	125	1			T65	1		T37	1		T102	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T3	1		T36	1		T21	1
auto[0:134217727]	auto[1]	50	1			T200	1		T109	1		T111	1
auto[134217728:268435455]	auto[0]	55	1			T24	1		T130	1		T132	2
auto[134217728:268435455]	auto[1]	51	1			T5	1		T28	1		T204	1
auto[268435456:402653183]	auto[0]	53	1			T35	1		T24	1		T102	1
auto[268435456:402653183]	auto[1]	58	1			T6	1		T155	1		T109	1
auto[402653184:536870911]	auto[0]	65	1			T20	1		T61	1		T111	2
auto[402653184:536870911]	auto[1]	63	1			T15	1		T36	1		T21	1
auto[536870912:671088639]	auto[0]	68	1			T34	1		T56	1		T204	2
auto[536870912:671088639]	auto[1]	39	1			T2	1		T91	1		T62	1
auto[671088640:805306367]	auto[0]	59	1			T34	1		T6	1		T140	1
auto[671088640:805306367]	auto[1]	59	1			T76	1		T153	1		T155	1
auto[805306368:939524095]	auto[0]	53	1			T2	1		T56	1		T153	1
auto[805306368:939524095]	auto[1]	61	1			T106	1		T91	1		T202	1
auto[939524096:1073741823]	auto[0]	42	1			T111	1		T432	1		T433	1
auto[939524096:1073741823]	auto[1]	47	1			T101	1		T130	1		T395	1
auto[1073741824:1207959551]	auto[0]	52	1			T94	1		T62	1		T281	1
auto[1073741824:1207959551]	auto[1]	54	1			T198	1		T94	1		T201	1
auto[1207959552:1342177279]	auto[0]	46	1			T3	1		T6	2		T200	1
auto[1207959552:1342177279]	auto[1]	69	1			T15	1		T6	1		T198	1
auto[1342177280:1476395007]	auto[0]	56	1			T24	1		T269	1		T281	1
auto[1342177280:1476395007]	auto[1]	57	1			T24	1		T200	1		T202	1
auto[1476395008:1610612735]	auto[0]	42	1			T3	1		T5	1		T15	1
auto[1476395008:1610612735]	auto[1]	69	1			T198	1		T76	1		T28	1
auto[1610612736:1744830463]	auto[0]	42	1			T125	1		T155	1		T253	1
auto[1610612736:1744830463]	auto[1]	48	1			T75	1		T35	1		T251	1
auto[1744830464:1879048191]	auto[0]	42	1			T2	1		T65	1		T132	1
auto[1744830464:1879048191]	auto[1]	62	1			T27	2		T155	1		T310	1
auto[1879048192:2013265919]	auto[0]	61	1			T15	1		T125	1		T60	1
auto[1879048192:2013265919]	auto[1]	54	1			T15	1		T105	1		T28	1
auto[2013265920:2147483647]	auto[0]	62	1			T5	1		T34	1		T125	1
auto[2013265920:2147483647]	auto[1]	47	1			T15	1		T102	2		T61	1
auto[2147483648:2281701375]	auto[0]	57	1			T198	1		T60	1		T64	1
auto[2147483648:2281701375]	auto[1]	61	1			T56	1		T130	1		T200	1
auto[2281701376:2415919103]	auto[0]	48	1			T20	1		T209	1		T108	1
auto[2281701376:2415919103]	auto[1]	60	1			T198	1		T154	1		T61	1
auto[2415919104:2550136831]	auto[0]	54	1			T36	1		T60	1		T130	1
auto[2415919104:2550136831]	auto[1]	72	1			T5	1		T19	1		T75	1
auto[2550136832:2684354559]	auto[0]	56	1			T60	1		T56	1		T8	1
auto[2550136832:2684354559]	auto[1]	51	1			T21	1		T153	1		T197	1
auto[2684354560:2818572287]	auto[0]	56	1			T34	1		T35	1		T65	1
auto[2684354560:2818572287]	auto[1]	70	1			T19	1		T21	1		T107	1
auto[2818572288:2952790015]	auto[0]	59	1			T20	1		T56	2		T253	2
auto[2818572288:2952790015]	auto[1]	59	1			T107	1		T153	1		T210	1
auto[2952790016:3087007743]	auto[0]	52	1			T27	1		T37	1		T92	1
auto[2952790016:3087007743]	auto[1]	54	1			T101	1		T76	1		T61	1
auto[3087007744:3221225471]	auto[0]	49	1			T3	1		T34	1		T35	1
auto[3087007744:3221225471]	auto[1]	56	1			T107	1		T269	1		T281	1
auto[3221225472:3355443199]	auto[0]	48	1			T35	1		T198	1		T37	1
auto[3221225472:3355443199]	auto[1]	49	1			T20	1		T75	2		T6	1
auto[3355443200:3489660927]	auto[0]	51	1			T24	1		T153	1		T45	1
auto[3355443200:3489660927]	auto[1]	55	1			T15	1		T27	1		T251	1
auto[3489660928:3623878655]	auto[0]	60	1			T75	1		T24	1		T38	1
auto[3489660928:3623878655]	auto[1]	61	1			T106	1		T128	1		T75	1
auto[3623878656:3758096383]	auto[0]	55	1			T128	1		T6	1		T56	1
auto[3623878656:3758096383]	auto[1]	59	1			T7	1		T108	1		T8	1
auto[3758096384:3892314111]	auto[0]	48	1			T56	1		T24	1		T62	1
auto[3758096384:3892314111]	auto[1]	61	1			T20	1		T101	1		T93	1
auto[3892314112:4026531839]	auto[0]	56	1			T20	1		T60	1		T248	1
auto[3892314112:4026531839]	auto[1]	49	1			T102	1		T132	1		T111	1
auto[4026531840:4160749567]	auto[0]	49	1			T2	1		T3	1		T128	1
auto[4026531840:4160749567]	auto[1]	53	1			T34	1		T76	1		T61	1
auto[4160749568:4294967295]	auto[0]	58	1			T62	1		T111	1		T190	1
auto[4160749568:4294967295]	auto[1]	67	1			T65	1		T37	1		T102	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1686

1

T2

4

T3

4

T5

2

auto[1]

1841

1

T3

1

T5

2

T15

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T24	1		T200	1		T109	1
auto[134217728:268435455]	112	1			T34	1		T60	1		T155	1
auto[268435456:402653183]	100	1			T75	1		T35	1		T45	1
auto[402653184:536870911]	112	1			T15	1		T20	1		T75	1
auto[536870912:671088639]	127	1			T5	1		T6	1		T198	1
auto[671088640:805306367]	112	1			T5	1		T15	2		T75	1
auto[805306368:939524095]	112	1			T34	1		T36	1		T75	1
auto[939524096:1073741823]	117	1			T19	1		T128	1		T6	1
auto[1073741824:1207959551]	91	1			T27	2		T37	1		T61	2
auto[1207959552:1342177279]	123	1			T19	1		T209	1		T102	1
auto[1342177280:1476395007]	106	1			T6	1		T65	1		T60	1
auto[1476395008:1610612735]	99	1			T5	1		T15	1		T101	1
auto[1610612736:1744830463]	115	1			T2	2		T60	1		T101	1
auto[1744830464:1879048191]	117	1			T36	1		T6	1		T21	2
auto[1879048192:2013265919]	109	1			T6	1		T65	1		T60	1
auto[2013265920:2147483647]	117	1			T15	1		T198	2		T130	1
auto[2147483648:2281701375]	100	1			T15	1		T6	1		T27	1
auto[2281701376:2415919103]	103	1			T34	1		T35	1		T76	2
auto[2415919104:2550136831]	116	1			T3	1		T37	1		T56	1
auto[2550136832:2684354559]	135	1			T3	1		T34	1		T106	1
auto[2684354560:2818572287]	103	1			T75	2		T28	2		T140	2
auto[2818572288:2952790015]	110	1			T2	1		T34	1		T56	1
auto[2952790016:3087007743]	102	1			T3	1		T15	1		T34	1
auto[3087007744:3221225471]	95	1			T3	1		T20	1		T198	1
auto[3221225472:3355443199]	108	1			T36	1		T125	1		T6	1
auto[3355443200:3489660927]	93	1			T128	1		T198	1		T92	1
auto[3489660928:3623878655]	116	1			T2	1		T20	1		T198	1
auto[3623878656:3758096383]	118	1			T3	1		T20	1		T125	1
auto[3758096384:3892314111]	122	1			T35	1		T27	1		T56	1
auto[3892314112:4026531839]	109	1			T5	1		T20	1		T106	1
auto[4026531840:4160749567]	116	1			T20	1		T21	1		T107	1
auto[4160749568:4294967295]	103	1			T56	1		T24	2		T102	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T24	1		T304	2		T132	2
auto[0:134217727]	auto[1]	53	1			T200	1		T109	1		T69	1
auto[134217728:268435455]	auto[0]	51	1			T34	1		T60	1		T155	1
auto[134217728:268435455]	auto[1]	61	1			T61	1		T132	1		T111	2
auto[268435456:402653183]	auto[0]	40	1			T75	1		T45	1		T281	1
auto[268435456:402653183]	auto[1]	60	1			T35	1		T93	1		T94	1
auto[402653184:536870911]	auto[0]	50	1			T62	1		T304	1		T132	1
auto[402653184:536870911]	auto[1]	62	1			T15	1		T20	1		T75	1
auto[536870912:671088639]	auto[0]	63	1			T5	1		T6	1		T198	1
auto[536870912:671088639]	auto[1]	64	1			T153	1		T111	1		T293	1
auto[671088640:805306367]	auto[0]	61	1			T5	1		T15	1		T27	1
auto[671088640:805306367]	auto[1]	51	1			T15	1		T75	1		T61	1
auto[805306368:939524095]	auto[0]	49	1			T36	1		T125	1		T56	1
auto[805306368:939524095]	auto[1]	63	1			T34	1		T75	1		T105	1
auto[939524096:1073741823]	auto[0]	59	1			T6	1		T93	1		T140	1
auto[939524096:1073741823]	auto[1]	58	1			T19	1		T128	1		T37	1
auto[1073741824:1207959551]	auto[0]	41	1			T37	1		T253	1		T126	1
auto[1073741824:1207959551]	auto[1]	50	1			T27	2		T61	2		T132	1
auto[1207959552:1342177279]	auto[0]	63	1			T209	1		T102	1		T94	1
auto[1207959552:1342177279]	auto[1]	60	1			T19	1		T76	1		T204	1
auto[1342177280:1476395007]	auto[0]	47	1			T60	1		T200	1		T253	1
auto[1342177280:1476395007]	auto[1]	59	1			T6	1		T65	1		T130	1
auto[1476395008:1610612735]	auto[0]	49	1			T61	1		T62	1		T8	1
auto[1476395008:1610612735]	auto[1]	50	1			T5	1		T15	1		T101	1
auto[1610612736:1744830463]	auto[0]	54	1			T2	2		T60	1		T153	1
auto[1610612736:1744830463]	auto[1]	61	1			T101	1		T107	1		T153	1
auto[1744830464:1879048191]	auto[0]	53	1			T36	1		T6	1		T130	1
auto[1744830464:1879048191]	auto[1]	64	1			T21	2		T269	2		T64	1
auto[1879048192:2013265919]	auto[0]	55	1			T60	1		T56	1		T253	1
auto[1879048192:2013265919]	auto[1]	54	1			T6	1		T65	1		T91	1
auto[2013265920:2147483647]	auto[0]	56	1			T198	1		T204	1		T281	1
auto[2013265920:2147483647]	auto[1]	61	1			T15	1		T198	1		T130	1
auto[2147483648:2281701375]	auto[0]	42	1			T15	1		T6	1		T27	1
auto[2147483648:2281701375]	auto[1]	58	1			T61	2		T289	1		T38	1
auto[2281701376:2415919103]	auto[0]	51	1			T34	1		T35	1		T155	1
auto[2281701376:2415919103]	auto[1]	52	1			T76	2		T61	1		T289	1
auto[2415919104:2550136831]	auto[0]	55	1			T3	1		T37	1		T56	1
auto[2415919104:2550136831]	auto[1]	61	1			T153	1		T200	1		T109	1
auto[2550136832:2684354559]	auto[0]	65	1			T3	1		T130	1		T108	1
auto[2550136832:2684354559]	auto[1]	70	1			T34	1		T106	1		T102	1
auto[2684354560:2818572287]	auto[0]	58	1			T75	1		T140	2		T278	1
auto[2684354560:2818572287]	auto[1]	45	1			T75	1		T28	2		T64	1
auto[2818572288:2952790015]	auto[0]	53	1			T2	1		T34	1		T56	1
auto[2818572288:2952790015]	auto[1]	57	1			T132	2		T395	1		T139	1
auto[2952790016:3087007743]	auto[0]	48	1			T15	1		T34	1		T45	1
auto[2952790016:3087007743]	auto[1]	54	1			T3	1		T128	1		T105	1
auto[3087007744:3221225471]	auto[0]	42	1			T3	1		T20	1		T198	1
auto[3087007744:3221225471]	auto[1]	53	1			T60	1		T56	1		T132	1
auto[3221225472:3355443199]	auto[0]	51	1			T36	1		T125	1		T155	1
auto[3221225472:3355443199]	auto[1]	57	1			T6	1		T198	1		T109	1
auto[3355443200:3489660927]	auto[0]	47	1			T128	1		T92	1		T248	1
auto[3355443200:3489660927]	auto[1]	46	1			T198	1		T352	1		T304	1
auto[3489660928:3623878655]	auto[0]	63	1			T2	1		T20	1		T198	1
auto[3489660928:3623878655]	auto[1]	53	1			T105	1		T434	1		T111	1
auto[3623878656:3758096383]	auto[0]	47	1			T3	1		T20	1		T125	1
auto[3623878656:3758096383]	auto[1]	71	1			T154	1		T61	1		T93	1
auto[3758096384:3892314111]	auto[0]	64	1			T35	1		T27	1		T56	1
auto[3758096384:3892314111]	auto[1]	58	1			T129	1		T352	1		T111	1
auto[3892314112:4026531839]	auto[0]	55	1			T20	1		T21	1		T56	1
auto[3892314112:4026531839]	auto[1]	54	1			T5	1		T106	1		T35	1
auto[4026531840:4160749567]	auto[0]	47	1			T20	1		T64	1		T301	1
auto[4026531840:4160749567]	auto[1]	69	1			T21	1		T107	1		T153	1
auto[4160749568:4294967295]	auto[0]	51	1			T56	1		T24	2		T62	1
auto[4160749568:4294967295]	auto[1]	52	1			T102	1		T91	1		T201	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1716

1

T2

3

T3

4

T5

2

auto[1]

1811

1

T2

1

T3

1

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	87	1			T125	1		T27	1		T76	1
auto[134217728:268435455]	119	1			T15	1		T20	1		T60	1
auto[268435456:402653183]	103	1			T20	1		T6	1		T35	1
auto[402653184:536870911]	111	1			T75	1		T35	1		T56	1
auto[536870912:671088639]	97	1			T6	1		T21	1		T60	1
auto[671088640:805306367]	115	1			T19	1		T61	2		T253	1
auto[805306368:939524095]	103	1			T6	1		T45	1		T91	1
auto[939524096:1073741823]	100	1			T3	1		T15	1		T209	1
auto[1073741824:1207959551]	106	1			T15	1		T20	1		T106	1
auto[1207959552:1342177279]	96	1			T5	1		T15	1		T75	1
auto[1342177280:1476395007]	98	1			T2	1		T3	1		T34	1
auto[1476395008:1610612735]	117	1			T15	1		T102	1		T130	1
auto[1610612736:1744830463]	102	1			T15	1		T20	1		T36	1
auto[1744830464:1879048191]	111	1			T21	1		T56	1		T24	2
auto[1879048192:2013265919]	109	1			T3	1		T5	1		T20	1
auto[2013265920:2147483647]	105	1			T3	1		T15	1		T19	1
auto[2147483648:2281701375]	124	1			T5	1		T65	1		T102	1
auto[2281701376:2415919103]	102	1			T125	1		T21	1		T56	2
auto[2415919104:2550136831]	102	1			T2	1		T155	2		T204	1
auto[2550136832:2684354559]	133	1			T6	1		T27	1		T102	1
auto[2684354560:2818572287]	116	1			T2	1		T128	1		T56	1
auto[2818572288:2952790015]	127	1			T65	1		T93	1		T108	1
auto[2952790016:3087007743]	121	1			T20	1		T27	1		T28	1
auto[3087007744:3221225471]	121	1			T36	1		T25	1		T289	1
auto[3221225472:3355443199]	106	1			T128	1		T6	2		T21	1
auto[3355443200:3489660927]	122	1			T34	1		T60	1		T37	1
auto[3489660928:3623878655]	115	1			T34	1		T35	1		T37	1
auto[3623878656:3758096383]	115	1			T2	1		T5	1		T34	1
auto[3758096384:3892314111]	90	1			T36	1		T35	1		T204	1
auto[3892314112:4026531839]	131	1			T3	1		T75	1		T198	1
auto[4026531840:4160749567]	109	1			T34	1		T75	1		T198	1
auto[4160749568:4294967295]	114	1			T34	1		T6	1		T198	2