Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4706

1

T2

6

T5

6

T15

12

auto[1]

2348

1

T2

2

T3

10

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	230	1			T2	2		T3	2		T20	2
auto[134217728:268435455]	264	1			T15	2		T34	2		T198	4
auto[268435456:402653183]	244	1			T3	2		T128	2		T6	2
auto[402653184:536870911]	220	1			T2	2		T15	2		T155	2
auto[536870912:671088639]	214	1			T56	2		T107	2		T155	4
auto[671088640:805306367]	228	1			T34	2		T36	2		T60	2
auto[805306368:939524095]	226	1			T125	2		T35	4		T24	2
auto[939524096:1073741823]	232	1			T15	4		T153	2		T92	2
auto[1073741824:1207959551]	212	1			T6	2		T27	2		T60	2
auto[1207959552:1342177279]	172	1			T24	4		T102	2		T28	2
auto[1342177280:1476395007]	212	1			T75	2		T6	2		T27	2
auto[1476395008:1610612735]	210	1			T19	2		T34	2		T106	2
auto[1610612736:1744830463]	224	1			T5	2		T60	2		T76	2
auto[1744830464:1879048191]	226	1			T209	2		T198	2		T101	2
auto[1879048192:2013265919]	252	1			T5	2		T15	2		T20	2
auto[2013265920:2147483647]	230	1			T2	2		T36	2		T130	4
auto[2147483648:2281701375]	218	1			T34	2		T35	2		T21	2
auto[2281701376:2415919103]	312	1			T3	2		T15	2		T20	4
auto[2415919104:2550136831]	202	1			T5	2		T6	2		T35	2
auto[2550136832:2684354559]	204	1			T75	2		T107	2		T61	4
auto[2684354560:2818572287]	204	1			T20	2		T128	2		T6	2
auto[2818572288:2952790015]	184	1			T15	2		T105	2		T61	2
auto[2952790016:3087007743]	206	1			T2	2		T198	2		T102	2
auto[3087007744:3221225471]	230	1			T19	2		T128	2		T6	2
auto[3221225472:3355443199]	220	1			T3	2		T75	2		T125	2
auto[3355443200:3489660927]	214	1			T20	2		T76	2		T61	2
auto[3489660928:3623878655]	218	1			T36	2		T56	2		T24	2
auto[3623878656:3758096383]	198	1			T75	2		T28	2		T61	2
auto[3758096384:3892314111]	192	1			T60	2		T37	2		T102	2
auto[3892314112:4026531839]	264	1			T34	2		T6	2		T60	2
auto[4026531840:4160749567]	174	1			T5	2		T34	2		T209	2
auto[4160749568:4294967295]	218	1			T3	2		T125	2		T198	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	156	1			T20	2		T75	2		T65	2
auto[0:134217727]	auto[1]	74	1			T2	2		T3	2		T75	2
auto[134217728:268435455]	auto[0]	176	1			T15	2		T34	2		T198	4
auto[134217728:268435455]	auto[1]	88	1			T129	2		T111	2		T293	2
auto[268435456:402653183]	auto[0]	166	1			T6	2		T21	2		T56	4
auto[268435456:402653183]	auto[1]	78	1			T3	2		T128	2		T61	2
auto[402653184:536870911]	auto[0]	148	1			T2	2		T155	2		T28	2
auto[402653184:536870911]	auto[1]	72	1			T15	2		T202	2		T435	2
auto[536870912:671088639]	auto[0]	156	1			T56	2		T107	2		T155	4
auto[536870912:671088639]	auto[1]	58	1			T440	2		T418	2		T441	2
auto[671088640:805306367]	auto[0]	156	1			T34	2		T36	2		T60	2
auto[671088640:805306367]	auto[1]	72	1			T105	2		T109	2		T310	4
auto[805306368:939524095]	auto[0]	136	1			T24	2		T91	2		T253	2
auto[805306368:939524095]	auto[1]	90	1			T125	2		T35	4		T248	2
auto[939524096:1073741823]	auto[0]	164	1			T15	4		T153	2		T281	2
auto[939524096:1073741823]	auto[1]	68	1			T92	2		T301	2		T417	2
auto[1073741824:1207959551]	auto[0]	128	1			T6	2		T27	2		T60	2
auto[1073741824:1207959551]	auto[1]	84	1			T24	2		T93	2		T269	2
auto[1207959552:1342177279]	auto[0]	118	1			T24	4		T102	2		T111	4
auto[1207959552:1342177279]	auto[1]	54	1			T28	2		T25	2		T301	2
auto[1342177280:1476395007]	auto[0]	144	1			T6	2		T27	2		T56	2
auto[1342177280:1476395007]	auto[1]	68	1			T75	2		T317	2		T84	2
auto[1476395008:1610612735]	auto[0]	134	1			T34	2		T198	2		T289	2
auto[1476395008:1610612735]	auto[1]	76	1			T19	2		T106	2		T21	2
auto[1610612736:1744830463]	auto[0]	148	1			T5	2		T76	2		T153	2
auto[1610612736:1744830463]	auto[1]	76	1			T60	2		T61	2		T132	2
auto[1744830464:1879048191]	auto[0]	150	1			T209	2		T198	2		T8	2
auto[1744830464:1879048191]	auto[1]	76	1			T101	2		T204	2		T8	2
auto[1879048192:2013265919]	auto[0]	176	1			T5	2		T15	2		T20	2
auto[1879048192:2013265919]	auto[1]	76	1			T106	2		T45	2		T94	2
auto[2013265920:2147483647]	auto[0]	166	1			T2	2		T36	2		T130	4
auto[2013265920:2147483647]	auto[1]	64	1			T69	2		T111	2		T294	2
auto[2147483648:2281701375]	auto[0]	124	1			T34	2		T198	2		T202	2
auto[2147483648:2281701375]	auto[1]	94	1			T35	2		T21	2		T101	2
auto[2281701376:2415919103]	auto[0]	220	1			T15	2		T20	4		T21	2
auto[2281701376:2415919103]	auto[1]	92	1			T3	2		T200	2		T132	2
auto[2415919104:2550136831]	auto[0]	140	1			T5	2		T6	2		T35	2
auto[2415919104:2550136831]	auto[1]	62	1			T7	2		T140	2		T144	2
auto[2550136832:2684354559]	auto[0]	118	1			T75	2		T107	2		T61	2
auto[2550136832:2684354559]	auto[1]	86	1			T61	2		T201	2		T132	2
auto[2684354560:2818572287]	auto[0]	132	1			T20	2		T128	2		T6	2
auto[2684354560:2818572287]	auto[1]	72	1			T153	2		T395	2		T190	2
auto[2818572288:2952790015]	auto[0]	132	1			T15	2		T61	2		T281	2
auto[2818572288:2952790015]	auto[1]	52	1			T105	2		T62	4		T140	2
auto[2952790016:3087007743]	auto[0]	136	1			T2	2		T198	2		T102	2
auto[2952790016:3087007743]	auto[1]	70	1			T107	2		T132	4		T317	2
auto[3087007744:3221225471]	auto[0]	152	1			T128	2		T6	2		T61	2
auto[3087007744:3221225471]	auto[1]	78	1			T19	2		T35	2		T142	2
auto[3221225472:3355443199]	auto[0]	146	1			T75	2		T65	4		T60	2
auto[3221225472:3355443199]	auto[1]	74	1			T3	2		T125	2		T38	2
auto[3355443200:3489660927]	auto[0]	166	1			T20	2		T61	2		T253	2
auto[3355443200:3489660927]	auto[1]	48	1			T76	2		T92	2		T94	2
auto[3489660928:3623878655]	auto[0]	128	1			T56	2		T24	2		T210	2
auto[3489660928:3623878655]	auto[1]	90	1			T36	2		T61	2		T109	2
auto[3623878656:3758096383]	auto[0]	144	1			T28	2		T62	2		T200	2
auto[3623878656:3758096383]	auto[1]	54	1			T75	2		T61	2		T111	4
auto[3758096384:3892314111]	auto[0]	128	1			T60	2		T37	2		T102	2
auto[3758096384:3892314111]	auto[1]	64	1			T109	2		T111	2		T191	4
auto[3892314112:4026531839]	auto[0]	164	1			T34	2		T60	2		T132	4
auto[3892314112:4026531839]	auto[1]	100	1			T6	2		T154	2		T61	2
auto[4026531840:4160749567]	auto[0]	118	1			T209	2		T8	2		T132	4
auto[4026531840:4160749567]	auto[1]	56	1			T5	2		T34	2		T61	2
auto[4160749568:4294967295]	auto[0]	136	1			T198	2		T24	2		T130	2
auto[4160749568:4294967295]	auto[1]	82	1			T3	2		T125	2		T102	2