Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3052

1

T2

4

T3

5

T5

4

auto[1]

309

1

T5

3

T75

2

T76

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T20	1		T6	1		T65	1
auto[134217728:268435455]	91	1			T5	1		T15	1		T20	1
auto[268435456:402653183]	90	1			T24	1		T102	1		T153	1
auto[402653184:536870911]	109	1			T35	1		T27	1		T102	1
auto[536870912:671088639]	97	1			T19	1		T35	2		T60	2
auto[671088640:805306367]	100	1			T2	1		T21	1		T24	1
auto[805306368:939524095]	105	1			T128	1		T75	1		T37	2
auto[939524096:1073741823]	125	1			T3	1		T20	1		T128	1
auto[1073741824:1207959551]	115	1			T75	1		T125	1		T209	1
auto[1207959552:1342177279]	99	1			T21	1		T61	2		T94	1
auto[1342177280:1476395007]	98	1			T36	1		T106	1		T125	1
auto[1476395008:1610612735]	87	1			T34	2		T128	1		T6	1
auto[1610612736:1744830463]	107	1			T3	1		T75	1		T35	1
auto[1744830464:1879048191]	104	1			T3	1		T102	2		T61	1
auto[1879048192:2013265919]	114	1			T15	1		T75	1		T27	2
auto[2013265920:2147483647]	116	1			T5	1		T36	1		T198	1
auto[2147483648:2281701375]	94	1			T5	1		T153	1		T109	1
auto[2281701376:2415919103]	98	1			T15	1		T34	1		T20	1
auto[2415919104:2550136831]	109	1			T34	1		T198	1		T153	1
auto[2550136832:2684354559]	111	1			T2	1		T19	1		T6	1
auto[2684354560:2818572287]	104	1			T65	1		T101	1		T153	1
auto[2818572288:2952790015]	96	1			T2	1		T3	1		T75	1
auto[2952790016:3087007743]	115	1			T34	1		T20	1		T75	1
auto[3087007744:3221225471]	123	1			T5	1		T198	2		T60	1
auto[3221225472:3355443199]	112	1			T75	1		T21	1		T107	1
auto[3355443200:3489660927]	90	1			T198	1		T56	1		T107	1
auto[3489660928:3623878655]	92	1			T5	1		T35	1		T27	1
auto[3623878656:3758096383]	115	1			T3	1		T34	1		T75	1
auto[3758096384:3892314111]	109	1			T2	1		T15	1		T56	1
auto[3892314112:4026531839]	106	1			T20	1		T130	1		T204	2
auto[4026531840:4160749567]	102	1			T5	1		T6	1		T107	1
auto[4160749568:4294967295]	119	1			T5	1		T209	1		T198	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	99	1			T20	1		T6	1		T65	1
auto[0:134217727]	auto[1]	10	1			T301	1		T250	2		T426	1
auto[134217728:268435455]	auto[0]	83	1			T15	1		T20	1		T62	1
auto[134217728:268435455]	auto[1]	8	1			T5	1		T76	1		T108	1
auto[268435456:402653183]	auto[0]	81	1			T24	1		T102	1		T153	1
auto[268435456:402653183]	auto[1]	9	1			T109	1		T359	1		T426	1
auto[402653184:536870911]	auto[0]	101	1			T35	1		T27	1		T102	1
auto[402653184:536870911]	auto[1]	8	1			T294	1		T359	1		T333	1
auto[536870912:671088639]	auto[0]	90	1			T19	1		T35	2		T60	2
auto[536870912:671088639]	auto[1]	7	1			T404	1		T333	1		T427	2
auto[671088640:805306367]	auto[0]	86	1			T2	1		T21	1		T24	1
auto[671088640:805306367]	auto[1]	14	1			T76	1		T108	1		T294	1
auto[805306368:939524095]	auto[0]	100	1			T128	1		T75	1		T37	2
auto[805306368:939524095]	auto[1]	5	1			T403	1		T313	1		T333	1
auto[939524096:1073741823]	auto[0]	117	1			T3	1		T20	1		T128	1
auto[939524096:1073741823]	auto[1]	8	1			T76	1		T108	1		T384	1
auto[1073741824:1207959551]	auto[0]	104	1			T125	1		T209	1		T155	1
auto[1073741824:1207959551]	auto[1]	11	1			T75	1		T108	1		T352	1
auto[1207959552:1342177279]	auto[0]	88	1			T21	1		T61	2		T94	1
auto[1207959552:1342177279]	auto[1]	11	1			T281	1		T294	1		T403	1
auto[1342177280:1476395007]	auto[0]	88	1			T36	1		T106	1		T125	1
auto[1342177280:1476395007]	auto[1]	10	1			T108	1		T312	1		T287	1
auto[1476395008:1610612735]	auto[0]	75	1			T34	2		T128	1		T6	1
auto[1476395008:1610612735]	auto[1]	12	1			T107	1		T403	1		T250	1
auto[1610612736:1744830463]	auto[0]	97	1			T3	1		T75	1		T35	1
auto[1610612736:1744830463]	auto[1]	10	1			T76	1		T352	1		T403	1
auto[1744830464:1879048191]	auto[0]	100	1			T3	1		T102	2		T61	1
auto[1744830464:1879048191]	auto[1]	4	1			T250	1		T429	1		T448	2
auto[1879048192:2013265919]	auto[0]	108	1			T15	1		T75	1		T27	2
auto[1879048192:2013265919]	auto[1]	6	1			T281	1		T301	2		T430	1
auto[2013265920:2147483647]	auto[0]	102	1			T36	1		T198	1		T92	1
auto[2013265920:2147483647]	auto[1]	14	1			T5	1		T108	2		T281	1
auto[2147483648:2281701375]	auto[0]	83	1			T5	1		T153	1		T129	1
auto[2147483648:2281701375]	auto[1]	11	1			T109	1		T281	1		T254	1
auto[2281701376:2415919103]	auto[0]	88	1			T15	1		T34	1		T20	1
auto[2281701376:2415919103]	auto[1]	10	1			T384	1		T359	1		T287	1
auto[2415919104:2550136831]	auto[0]	99	1			T34	1		T198	1		T153	1
auto[2415919104:2550136831]	auto[1]	10	1			T287	1		T426	2		T437	1
auto[2550136832:2684354559]	auto[0]	103	1			T2	1		T19	1		T6	1
auto[2550136832:2684354559]	auto[1]	8	1			T352	1		T294	1		T264	1
auto[2684354560:2818572287]	auto[0]	97	1			T65	1		T101	1		T153	1
auto[2684354560:2818572287]	auto[1]	7	1			T109	2		T254	1		T313	1
auto[2818572288:2952790015]	auto[0]	88	1			T2	1		T3	1		T60	1
auto[2818572288:2952790015]	auto[1]	8	1			T75	1		T76	1		T359	1
auto[2952790016:3087007743]	auto[0]	106	1			T34	1		T20	1		T75	1
auto[2952790016:3087007743]	auto[1]	9	1			T404	1		T291	1		T431	2
auto[3087007744:3221225471]	auto[0]	106	1			T198	2		T60	1		T62	1
auto[3087007744:3221225471]	auto[1]	17	1			T5	1		T76	1		T250	1
auto[3221225472:3355443199]	auto[0]	102	1			T75	1		T21	1		T93	1
auto[3221225472:3355443199]	auto[1]	10	1			T107	1		T294	1		T384	2
auto[3355443200:3489660927]	auto[0]	83	1			T198	1		T56	1		T107	1
auto[3355443200:3489660927]	auto[1]	7	1			T294	1		T403	1		T423	1
auto[3489660928:3623878655]	auto[0]	79	1			T5	1		T35	1		T27	1
auto[3489660928:3623878655]	auto[1]	13	1			T108	1		T281	1		T301	1
auto[3623878656:3758096383]	auto[0]	104	1			T3	1		T34	1		T75	1
auto[3623878656:3758096383]	auto[1]	11	1			T246	1		T287	1		T426	1
auto[3758096384:3892314111]	auto[0]	101	1			T2	1		T15	1		T56	1
auto[3758096384:3892314111]	auto[1]	8	1			T107	2		T281	1		T301	1
auto[3892314112:4026531839]	auto[0]	100	1			T20	1		T130	1		T204	2
auto[3892314112:4026531839]	auto[1]	6	1			T333	1		T427	1		T424	1
auto[4026531840:4160749567]	auto[0]	88	1			T5	1		T6	1		T107	1
auto[4026531840:4160749567]	auto[1]	14	1			T108	1		T313	2		T250	1
auto[4160749568:4294967295]	auto[0]	106	1			T5	1		T209	1		T198	1
auto[4160749568:4294967295]	auto[1]	13	1			T108	1		T260	1		T403	1