Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1732

1

T2

2

T3

4

T5

2

auto[1]

1796

1

T2

2

T3

1

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T36	1		T125	1		T153	1
auto[134217728:268435455]	120	1			T20	1		T128	1		T21	1
auto[268435456:402653183]	120	1			T2	1		T198	1		T65	1
auto[402653184:536870911]	107	1			T2	1		T34	1		T35	1
auto[536870912:671088639]	111	1			T6	1		T101	1		T93	1
auto[671088640:805306367]	130	1			T3	2		T24	1		T155	1
auto[805306368:939524095]	103	1			T5	1		T20	1		T198	1
auto[939524096:1073741823]	103	1			T101	1		T24	1		T310	1
auto[1073741824:1207959551]	94	1			T34	1		T20	1		T60	1
auto[1207959552:1342177279]	104	1			T15	1		T19	1		T198	1
auto[1342177280:1476395007]	123	1			T128	1		T24	2		T107	1
auto[1476395008:1610612735]	123	1			T15	1		T34	1		T20	1
auto[1610612736:1744830463]	100	1			T15	1		T35	1		T24	1
auto[1744830464:1879048191]	125	1			T24	2		T204	1		T61	2
auto[1879048192:2013265919]	101	1			T106	1		T27	1		T56	1
auto[2013265920:2147483647]	103	1			T34	1		T27	1		T65	1
auto[2147483648:2281701375]	111	1			T6	1		T21	1		T101	1
auto[2281701376:2415919103]	120	1			T3	1		T106	1		T27	1
auto[2415919104:2550136831]	107	1			T15	1		T21	1		T37	1
auto[2550136832:2684354559]	106	1			T3	1		T6	3		T35	1
auto[2684354560:2818572287]	98	1			T198	1		T56	1		T155	1
auto[2818572288:2952790015]	119	1			T5	1		T15	1		T75	2
auto[2952790016:3087007743]	107	1			T3	1		T15	1		T125	1
auto[3087007744:3221225471]	98	1			T34	1		T198	1		T61	1
auto[3221225472:3355443199]	104	1			T5	1		T56	1		T107	1
auto[3355443200:3489660927]	103	1			T75	1		T35	1		T198	1
auto[3489660928:3623878655]	120	1			T2	1		T36	1		T75	1
auto[3623878656:3758096383]	115	1			T75	1		T209	1		T105	1
auto[3758096384:3892314111]	103	1			T20	2		T128	1		T6	1
auto[3892314112:4026531839]	120	1			T5	1		T36	1		T75	1
auto[4026531840:4160749567]	111	1			T2	1		T19	1		T6	1
auto[4160749568:4294967295]	100	1			T15	1		T34	1		T37	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	62	1			T36	1		T125	1		T253	1
auto[0:134217727]	auto[1]	57	1			T153	1		T281	1		T132	1
auto[134217728:268435455]	auto[0]	65	1			T20	1		T128	1		T27	1
auto[134217728:268435455]	auto[1]	55	1			T21	1		T198	1		T102	1
auto[268435456:402653183]	auto[0]	59	1			T2	1		T60	1		T56	1
auto[268435456:402653183]	auto[1]	61	1			T198	1		T65	1		T76	1
auto[402653184:536870911]	auto[0]	58	1			T34	1		T35	1		T56	1
auto[402653184:536870911]	auto[1]	49	1			T2	1		T209	1		T28	2
auto[536870912:671088639]	auto[0]	61	1			T6	1		T101	1		T132	2
auto[536870912:671088639]	auto[1]	50	1			T93	1		T132	1		T111	1
auto[671088640:805306367]	auto[0]	69	1			T3	2		T24	1		T155	1
auto[671088640:805306367]	auto[1]	61	1			T61	1		T210	1		T251	1
auto[805306368:939524095]	auto[0]	57	1			T5	1		T20	1		T198	1
auto[805306368:939524095]	auto[1]	46	1			T154	1		T269	1		T64	1
auto[939524096:1073741823]	auto[0]	63	1			T24	1		T310	1		T304	1
auto[939524096:1073741823]	auto[1]	40	1			T101	1		T434	1		T296	2
auto[1073741824:1207959551]	auto[0]	48	1			T34	1		T20	1		T60	1
auto[1073741824:1207959551]	auto[1]	46	1			T56	1		T111	1		T84	1
auto[1207959552:1342177279]	auto[0]	51	1			T56	1		T204	1		T108	1
auto[1207959552:1342177279]	auto[1]	53	1			T15	1		T19	1		T198	1
auto[1342177280:1476395007]	auto[0]	59	1			T24	1		T130	1		T200	1
auto[1342177280:1476395007]	auto[1]	64	1			T128	1		T24	1		T107	1
auto[1476395008:1610612735]	auto[0]	68	1			T15	1		T20	1		T94	1
auto[1476395008:1610612735]	auto[1]	55	1			T34	1		T61	1		T92	1
auto[1610612736:1744830463]	auto[0]	47	1			T35	1		T24	1		T45	1
auto[1610612736:1744830463]	auto[1]	53	1			T15	1		T61	1		T91	1
auto[1744830464:1879048191]	auto[0]	61	1			T24	2		T61	1		T109	1
auto[1744830464:1879048191]	auto[1]	64	1			T204	1		T61	1		T200	1
auto[1879048192:2013265919]	auto[0]	42	1			T27	1		T56	1		T24	1
auto[1879048192:2013265919]	auto[1]	59	1			T106	1		T61	1		T352	2
auto[2013265920:2147483647]	auto[0]	57	1			T34	1		T61	1		T140	1
auto[2013265920:2147483647]	auto[1]	46	1			T27	1		T65	1		T61	1
auto[2147483648:2281701375]	auto[0]	57	1			T21	1		T101	1		T153	1
auto[2147483648:2281701375]	auto[1]	54	1			T6	1		T155	1		T7	1
auto[2281701376:2415919103]	auto[0]	58	1			T3	1		T27	1		T60	1
auto[2281701376:2415919103]	auto[1]	62	1			T106	1		T130	1		T94	1
auto[2415919104:2550136831]	auto[0]	41	1			T21	1		T91	1		T108	1
auto[2415919104:2550136831]	auto[1]	66	1			T15	1		T37	1		T101	1
auto[2550136832:2684354559]	auto[0]	57	1			T3	1		T6	1		T76	1
auto[2550136832:2684354559]	auto[1]	49	1			T6	2		T35	1		T27	1
auto[2684354560:2818572287]	auto[0]	36	1			T198	1		T56	1		T94	1
auto[2684354560:2818572287]	auto[1]	62	1			T155	1		T204	1		T108	1
auto[2818572288:2952790015]	auto[0]	54	1			T5	1		T15	1		T75	1
auto[2818572288:2952790015]	auto[1]	65	1			T75	1		T60	1		T28	1
auto[2952790016:3087007743]	auto[0]	46	1			T15	1		T125	1		T38	1
auto[2952790016:3087007743]	auto[1]	61	1			T3	1		T21	1		T105	1
auto[3087007744:3221225471]	auto[0]	38	1			T198	1		T61	1		T92	1
auto[3087007744:3221225471]	auto[1]	60	1			T34	1		T7	1		T108	1
auto[3221225472:3355443199]	auto[0]	44	1			T56	1		T45	1		T62	1
auto[3221225472:3355443199]	auto[1]	60	1			T5	1		T107	1		T201	1
auto[3355443200:3489660927]	auto[0]	44	1			T35	1		T198	1		T56	2
auto[3355443200:3489660927]	auto[1]	59	1			T75	1		T93	2		T200	1
auto[3489660928:3623878655]	auto[0]	56	1			T36	1		T125	1		T204	1
auto[3489660928:3623878655]	auto[1]	64	1			T2	1		T75	1		T102	1
auto[3623878656:3758096383]	auto[0]	63	1			T75	1		T61	1		T92	1
auto[3623878656:3758096383]	auto[1]	52	1			T209	1		T105	1		T155	1
auto[3758096384:3892314111]	auto[0]	46	1			T20	2		T6	1		T37	1
auto[3758096384:3892314111]	auto[1]	57	1			T128	1		T94	1		T111	1
auto[3892314112:4026531839]	auto[0]	59	1			T35	1		T248	1		T289	1
auto[3892314112:4026531839]	auto[1]	61	1			T5	1		T36	1		T75	1
auto[4026531840:4160749567]	auto[0]	53	1			T2	1		T6	1		T8	1
auto[4026531840:4160749567]	auto[1]	58	1			T19	1		T109	1		T251	1
auto[4160749568:4294967295]	auto[0]	53	1			T15	1		T34	1		T37	1
auto[4160749568:4294967295]	auto[1]	47	1			T108	1		T69	1		T64	1