Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7261

1

T2

14

T3

15

T5

8

auto[1]

254

1

T5

2

T75

1

T76

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3027	1			T2	6		T3	7		T5	4
auto[134217728:268435455]	178	1			T34	1		T20	1		T75	1
auto[268435456:402653183]	184	1			T2	2		T20	1		T75	1
auto[402653184:536870911]	151	1			T3	1		T15	2		T34	1
auto[536870912:671088639]	146	1			T209	1		T45	1		T204	1
auto[671088640:805306367]	155	1			T3	2		T34	1		T6	1
auto[805306368:939524095]	140	1			T2	1		T20	1		T106	1
auto[939524096:1073741823]	125	1			T20	1		T128	1		T6	1
auto[1073741824:1207959551]	135	1			T3	1		T27	1		T56	1
auto[1207959552:1342177279]	130	1			T19	1		T65	1		T24	1
auto[1342177280:1476395007]	136	1			T15	1		T20	1		T75	1
auto[1476395008:1610612735]	149	1			T75	1		T21	1		T24	1
auto[1610612736:1744830463]	125	1			T20	1		T6	1		T27	1
auto[1744830464:1879048191]	143	1			T20	2		T6	1		T35	1
auto[1879048192:2013265919]	150	1			T2	1		T5	1		T198	2
auto[2013265920:2147483647]	127	1			T5	1		T27	1		T102	1
auto[2147483648:2281701375]	130	1			T209	1		T76	1		T61	1
auto[2281701376:2415919103]	146	1			T2	1		T3	1		T5	1
auto[2415919104:2550136831]	175	1			T2	2		T5	1		T20	1
auto[2550136832:2684354559]	139	1			T20	1		T128	2		T107	1
auto[2684354560:2818572287]	129	1			T34	1		T106	1		T60	3
auto[2818572288:2952790015]	140	1			T15	1		T20	1		T102	1
auto[2952790016:3087007743]	142	1			T2	1		T15	1		T19	1
auto[3087007744:3221225471]	138	1			T3	1		T36	1		T24	1
auto[3221225472:3355443199]	149	1			T15	1		T35	1		T37	1
auto[3355443200:3489660927]	136	1			T3	1		T35	1		T27	1
auto[3489660928:3623878655]	150	1			T37	1		T56	1		T155	1
auto[3623878656:3758096383]	141	1			T27	1		T105	1		T153	1
auto[3758096384:3892314111]	161	1			T3	1		T24	1		T107	1
auto[3892314112:4026531839]	133	1			T20	1		T125	2		T6	1
auto[4026531840:4160749567]	154	1			T5	1		T75	2		T198	1
auto[4160749568:4294967295]	151	1			T5	1		T35	1		T102	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3018	1			T2	6		T3	7		T5	4
auto[0:134217727]	auto[1]	9	1			T423	2		T427	2		T436	1
auto[134217728:268435455]	auto[0]	171	1			T34	1		T20	1		T75	1
auto[134217728:268435455]	auto[1]	7	1			T384	1		T428	1		T437	1
auto[268435456:402653183]	auto[0]	168	1			T2	2		T20	1		T75	1
auto[268435456:402653183]	auto[1]	16	1			T294	1		T384	2		T246	2
auto[402653184:536870911]	auto[0]	144	1			T3	1		T15	2		T34	1
auto[402653184:536870911]	auto[1]	7	1			T76	1		T281	1		T301	1
auto[536870912:671088639]	auto[0]	139	1			T209	1		T45	1		T204	1
auto[536870912:671088639]	auto[1]	7	1			T313	1		T312	1		T333	1
auto[671088640:805306367]	auto[0]	147	1			T3	2		T34	1		T6	1
auto[671088640:805306367]	auto[1]	8	1			T423	1		T430	1		T333	1
auto[805306368:939524095]	auto[0]	132	1			T2	1		T20	1		T106	1
auto[805306368:939524095]	auto[1]	8	1			T294	1		T313	1		T250	1
auto[939524096:1073741823]	auto[0]	121	1			T20	1		T128	1		T6	1
auto[939524096:1073741823]	auto[1]	4	1			T250	1		T428	1		T431	1
auto[1073741824:1207959551]	auto[0]	131	1			T3	1		T27	1		T56	1
auto[1073741824:1207959551]	auto[1]	4	1			T108	1		T384	1		T425	1
auto[1207959552:1342177279]	auto[0]	119	1			T19	1		T65	1		T24	1
auto[1207959552:1342177279]	auto[1]	11	1			T76	1		T404	1		T260	1
auto[1342177280:1476395007]	auto[0]	133	1			T15	1		T20	1		T27	1
auto[1342177280:1476395007]	auto[1]	3	1			T75	1		T428	1		T245	1
auto[1476395008:1610612735]	auto[0]	136	1			T75	1		T21	1		T24	1
auto[1476395008:1610612735]	auto[1]	13	1			T301	2		T246	1		T428	1
auto[1610612736:1744830463]	auto[0]	120	1			T20	1		T6	1		T27	1
auto[1610612736:1744830463]	auto[1]	5	1			T301	2		T246	1		T438	1
auto[1744830464:1879048191]	auto[0]	133	1			T20	2		T6	1		T35	1
auto[1744830464:1879048191]	auto[1]	10	1			T76	1		T108	2		T281	1
auto[1879048192:2013265919]	auto[0]	148	1			T2	1		T5	1		T198	2
auto[1879048192:2013265919]	auto[1]	2	1			T426	1		T390	1		-	-
auto[2013265920:2147483647]	auto[0]	121	1			T5	1		T27	1		T102	1
auto[2013265920:2147483647]	auto[1]	6	1			T246	1		T427	1		T431	1
auto[2147483648:2281701375]	auto[0]	122	1			T209	1		T76	1		T61	1
auto[2147483648:2281701375]	auto[1]	8	1			T281	1		T246	1		T423	1
auto[2281701376:2415919103]	auto[0]	138	1			T2	1		T3	1		T5	1
auto[2281701376:2415919103]	auto[1]	8	1			T352	1		T294	1		T403	1
auto[2415919104:2550136831]	auto[0]	165	1			T2	2		T20	1		T198	1
auto[2415919104:2550136831]	auto[1]	10	1			T5	1		T281	1		T403	1
auto[2550136832:2684354559]	auto[0]	129	1			T20	1		T128	2		T204	1
auto[2550136832:2684354559]	auto[1]	10	1			T107	1		T428	1		T430	1
auto[2684354560:2818572287]	auto[0]	122	1			T34	1		T106	1		T60	3
auto[2684354560:2818572287]	auto[1]	7	1			T260	1		T287	1		T428	1
auto[2818572288:2952790015]	auto[0]	134	1			T15	1		T20	1		T102	1
auto[2818572288:2952790015]	auto[1]	6	1			T76	1		T107	1		T352	1
auto[2952790016:3087007743]	auto[0]	134	1			T2	1		T15	1		T19	1
auto[2952790016:3087007743]	auto[1]	8	1			T384	1		T313	2		T423	1
auto[3087007744:3221225471]	auto[0]	130	1			T3	1		T36	1		T24	1
auto[3087007744:3221225471]	auto[1]	8	1			T109	1		T246	1		T312	1
auto[3221225472:3355443199]	auto[0]	141	1			T15	1		T35	1		T37	1
auto[3221225472:3355443199]	auto[1]	8	1			T313	1		T428	2		T291	1
auto[3355443200:3489660927]	auto[0]	129	1			T3	1		T35	1		T27	1
auto[3355443200:3489660927]	auto[1]	7	1			T254	1		T359	1		T423	1
auto[3489660928:3623878655]	auto[0]	141	1			T37	1		T56	1		T155	1
auto[3489660928:3623878655]	auto[1]	9	1			T403	1		T250	1		T426	2
auto[3623878656:3758096383]	auto[0]	135	1			T27	1		T105	1		T153	1
auto[3623878656:3758096383]	auto[1]	6	1			T287	1		T333	1		T438	1
auto[3758096384:3892314111]	auto[0]	148	1			T3	1		T24	1		T61	2
auto[3758096384:3892314111]	auto[1]	13	1			T107	1		T403	1		T313	1
auto[3892314112:4026531839]	auto[0]	122	1			T20	1		T125	2		T6	1
auto[3892314112:4026531839]	auto[1]	11	1			T107	1		T301	1		T313	1
auto[4026531840:4160749567]	auto[0]	149	1			T5	1		T75	2		T198	1
auto[4026531840:4160749567]	auto[1]	5	1			T301	1		T291	1		T431	1
auto[4160749568:4294967295]	auto[0]	141	1			T35	1		T102	3		T155	1
auto[4160749568:4294967295]	auto[1]	10	1			T5	1		T246	1		T390	1