Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4792

1

T2

5

T3

8

T4

3

auto[1]

535

1

T4

5

T44

1

T18

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4792

1

T2

5

T3

8

T4

3

auto[1]

535

1

T4

5

T44

1

T18

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4786

1

T2

4

T3

5

T4

8

auto[1]

541

1

T2

1

T3

3

T5

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4786

1

T2

4

T3

5

T4

8

auto[1]

541

1

T2

1

T3

3

T5

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	431	1			T13	5		T18	1		T84	4
auto[OpGenId]	1153	1			T2	3		T5	1		T13	3
auto[OpGenSwOut]	1133	1			T2	1		T5	1		T13	2
auto[OpGenHwOut]	2530	1			T2	1		T3	8		T4	8
auto[OpDisable]	80	1			T18	2		T78	1		T66	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	431	1			T13	5		T18	1		T84	4
auto[OpGenId]	1153	1			T2	3		T5	1		T13	3
auto[OpGenSwOut]	1133	1			T2	1		T5	1		T13	2
auto[OpGenHwOut]	2530	1			T2	1		T3	8		T4	8
auto[OpDisable]	80	1			T18	2		T78	1		T66	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4812

1

T2

5

T3

8

T4

8

auto[1]

515

1

T13

5

T33

4

T18

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4812

1

T2

5

T3

8

T4

8

auto[1]

515

1

T13

5

T33

4

T18

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5023

1

T2

5

T3

8

T4

8

auto[1]

304

1

T13

10

T84

14

T108

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1792	1			T2	2		T3	3		T4	3
auto[1]	719	1			T2	2		T4	1		T5	1
auto[2]	698	1			T3	3		T4	2		T13	3
auto[3]	692	1			T3	1		T4	1		T13	1
auto[4]	381	1			T4	1		T33	1		T28	1
auto[5]	327	1			T16	1		T17	1		T18	1
auto[6]	359	1			T2	1		T16	1		T33	1
auto[7]	359	1			T3	1		T18	2		T74	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1426	1			T2	1		T3	1		T4	1
clear_one[1]	719	1			T2	2		T4	1		T5	1
clear_one[2]	698	1			T3	3		T4	2		T13	3
clear_one[3]	692	1			T3	1		T4	1		T13	1
clear_none	1792	1			T2	2		T3	3		T4	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	979	1			T2	2		T13	1		T15	2
auto[StInit]	616	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	583	1			T3	1		T4	1		T13	3
auto[StOwnerIntKey]	515	1			T2	1		T3	1		T4	1
auto[StOwnerKey]	459	1			T3	1		T4	1		T13	1
auto[StDisabled]	1881	1			T2	1		T3	4		T4	4
auto[StInvalid]	294	1			T17	1		T35	2		T134	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	979	1			T2	2		T13	1		T15	2
auto[StInit]	616	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	583	1			T3	1		T4	1		T13	3
auto[StOwnerIntKey]	515	1			T2	1		T3	1		T4	1
auto[StOwnerKey]	459	1			T3	1		T4	1		T13	1
auto[StDisabled]	1881	1			T2	1		T3	4		T4	4
auto[StInvalid]	294	1			T17	1		T35	2		T134	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T241	1		T242	1		T243	1
auto[0]	auto[StReset]	auto[OpGenId]	160	1			T2	1		T18	2		T99	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	160	1			T15	2		T17	1		T18	3
auto[0]	auto[StReset]	auto[OpGenHwOut]	232	1			T13	1		T28	2		T18	1
auto[0]	auto[StInit]	auto[OpAdvance]	35	1			T69	1		T205	1		T111	1
auto[0]	auto[StInit]	auto[OpGenId]	73	1			T44	1		T25	1		T209	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	88	1			T14	1		T16	1		T99	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	181	1			T3	1		T4	1		T15	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T13	2		T99	1		T126	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	58	1			T13	1		T18	1		T73	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	67	1			T67	1		T68	1		T244	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	70	1			T18	1		T104	1		T108	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	23	1			T207	1		T128	1		T189	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T2	1		T111	1		T245	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	40	1			T13	1		T68	1		T147	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	54	1			T3	1		T44	1		T74	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T246	1		T247	1		T242	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	23	1			T13	1		T69	1		T248	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T249	1		T250	2		T251	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T69	1		T252	1		T111	2
auto[0]	auto[StDisabled]	auto[OpAdvance]	27	1			T13	1		T67	1		T253	2
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T13	1		T67	1		T254	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T5	1		T211	1		T207	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T3	1		T4	2		T13	3
auto[0]	auto[StDisabled]	auto[OpDisable]	32	1			T78	1		T210	1		T68	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	9	1			T255	1		T256	1		T257	1
auto[0]	auto[StInvalid]	auto[OpGenId]	24	1			T35	1		T48	1		T71	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T134	1		T52	1		T70	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	26	1			T134	1		T52	1		T42	1
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T258	1		T68	1		T244	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	20	1			T18	1		T99	1		T145	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	47	1			T107	1		T214	1		T213	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T259	1		T23	1		T152	1
auto[1]	auto[StInit]	auto[OpGenId]	15	1			T2	1		T18	1		T69	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T68	2		T260	1		T7	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	14	1			T97	1		T261	1		T262	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T68	1		T263	1		T264	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	20	1			T25	1		T68	1		T116	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T206	1		T114	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T14	1		T77	1		T149	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T9	1		T113	1		T250	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T154	1		T116	1		T265	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T111	1		T249	1		T97	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T4	1		T33	1		T105	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T266	1		T267	1		T198	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T66	1		T67	1		T205	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T196	1		T268	1		T269	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T16	1		T75	1		T106	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	30	1			T84	3		T68	1		T113	1
auto[1]	auto[StDisabled]	auto[OpGenId]	60	1			T5	1		T73	1		T84	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T18	2		T84	1		T104	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T2	1		T33	2		T74	2
auto[1]	auto[StDisabled]	auto[OpDisable]	11	1			T18	1		T68	1		T189	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T270	1		T271	1		T272	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T48	1		T52	1		T53	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T35	1		T273	2		T146	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T17	1		T48	1		T46	1
auto[2]	auto[StReset]	auto[OpGenId]	24	1			T18	1		T254	1		T68	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	16	1			T244	1		T274	1		T275	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	39	1			T77	1		T48	1		T213	1
auto[2]	auto[StInit]	auto[OpAdvance]	2	1			T276	1		T277	1		-	-
auto[2]	auto[StInit]	auto[OpGenId]	17	1			T18	1		T211	1		T22	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	7	1			T13	1		T223	1		T23	2
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T13	1		T136	1		T278	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T154	1		T279	1		T280	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T111	1		T155	1		T251	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T147	1		T281	1		T154	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T4	1		T75	1		T105	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T282	1		T280	1		T283	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T18	1		T73	1		T66	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T16	1		T209	1		T260	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T107	1		T284	1		T188	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T285	1		T286	1		T287	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	7	1			T73	1		T69	1		T154	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T67	1		T97	2		T288	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T3	1		T4	1		T77	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	39	1			T13	1		T66	1		T126	1
auto[2]	auto[StDisabled]	auto[OpGenId]	63	1			T44	1		T104	1		T254	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T44	1		T66	1		T126	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T3	2		T33	1		T105	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T136	1		T196	1		T198	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T70	1		T289	1		T290	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T261	1		T291	1		T257	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T53	1		T70	1		T145	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T148	1		T273	1		T292	2
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T136	1		T293	1		T294	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	16	1			T66	1		T136	1		T258	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	49	1			T18	1		T191	1		T295	2
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T212	1		T293	1		T24	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T235	1		T296	1		T8	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T223	1		T7	1		T251	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	23	1			T69	1		T284	1		T188	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T66	1		T254	1		T80	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T26	1		T226	1		T31	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T246	1		T95	1		T24	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T33	1		T74	1		T106	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T196	1		T7	1		T297	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T298	1		T97	1		T296	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T108	1		T299	1		T97	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T75	1		T77	1		T84	3
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T115	1		T300	1		T247	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	8	1			T154	1		T301	1		T101	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T76	1		T66	1		T108	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T213	1		T149	1		T193	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	27	1			T13	1		T18	1		T84	1
auto[3]	auto[StDisabled]	auto[OpGenId]	64	1			T84	2		T66	1		T108	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T14	1		T84	3		T69	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	139	1			T3	1		T4	1		T77	1
auto[3]	auto[StDisabled]	auto[OpDisable]	15	1			T66	1		T302	1		T147	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T303	1		T304	1		T305	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T52	1		T274	1		T292	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T146	1		T306	1		T304	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T134	2		T307	1		T146	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T308	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T66	1		T309	1		T47	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	6	1			T28	1		T223	1		T310	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	27	1			T212	1		T80	1		T311	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T98	1		T312	1		T313	1
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T244	1		T54	1		T32	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T246	1		T314	1		T315	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	5	1			T68	1		T316	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T318	1		T319	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T44	1		T320	1		T321	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T154	1		T57	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T323	1		T284	1		T189	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T126	1		T324	1		T325	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T67	1		T300	1		T223	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T250	1		T8	1		T326	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T126	1		T327	1		T115	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T328	1		T329	1		T324	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T281	1		T96	1		T100	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T57	1		T330	1		T320	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T33	1		T107	1		T214	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	16	1			T69	1		T254	1		T114	2
auto[4]	auto[StDisabled]	auto[OpGenId]	33	1			T128	1		T189	1		T331	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	39	1			T215	1		T111	1		T285	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T4	1		T75	1		T77	1
auto[4]	auto[StDisabled]	auto[OpDisable]	3	1			T154	1		T332	1		T333	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T303	1		T334	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T274	1		T291	1		T335	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T50	1		T273	1		T274	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T71	1		T50	1		T307	1
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T136	1		T336	1		T147	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T17	1		T293	1		T321	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	23	1			T69	1		T68	1		T29	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T302	1		T22	1		T54	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T154	1		T146	1		T337	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	8	1			T338	1		T196	1		T337	2
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T109	1		T96	1		T55	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T192	1		T339	1		T237	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T69	1		T67	1		T68	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T69	1		T252	1		T340	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T248	1		T341	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T331	1		T154	1		T97	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T18	1		T7	1		T342	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T214	1		T343	1		T344	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T345	1		T346	1		T347	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T245	1		T348	1		T349	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T95	1		T350	1		T351	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T188	1		T192	1		T352	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	7	1			T353	1		T250	1		T8	1
auto[5]	auto[StDisabled]	auto[OpGenId]	28	1			T76	1		T204	1		T215	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T154	1		T114	2		T299	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	58	1			T16	1		T74	2		T105	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T7	1		T354	1		T355	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T257	1		T356	1		T357	1
auto[5]	auto[StInvalid]	auto[OpGenId]	9	1			T358	1		T307	1		T303	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T42	1		T291	1		T272	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T46	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T143	1		T309	1		T152	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T2	1		T18	1		T97	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	29	1			T107	1		T295	1		T147	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T113	1		T359	1		T360	1
auto[6]	auto[StInit]	auto[OpGenId]	1	1			T361	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T22	1		T362	1		T141	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	16	1			T77	1		T295	1		T22	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T241	1		T360	2		T363	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T97	1		T265	1		T321	2
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T16	1		T312	1		T360	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T76	1		T364	1		T113	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T110	1		T275	1		T326	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T76	1		T206	1		T57	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T109	1		T68	1		T233	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T365	1		T366	1		T367	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T110	1		T368	1		T319	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	12	1			T312	1		T369	1		T326	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T44	1		T370	1		T241	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T208	1		T327	1		T148	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	13	1			T154	1		T371	1		T114	1
auto[6]	auto[StDisabled]	auto[OpGenId]	18	1			T69	1		T189	1		T111	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T149	1		T189	1		T372	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T33	1		T75	2		T213	1
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T18	1		T155	1		T312	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T71	1		T373	1		T357	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T358	1		T374	1		T375	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T46	1		T376	1		T377	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T47	1		T378	1		T304	1
auto[7]	auto[StReset]	auto[OpGenId]	7	1			T66	1		T271	1		T379	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	5	1			T38	1		T69	1		T62	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	27	1			T69	1		T107	1		T284	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T326	1		T319	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T147	1		T95	1		T380	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T265	1		T381	1		T382	3
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T214	1		T213	1		T343	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T98	1		T383	1		T384	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T294	1		T380	1		T351	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T67	1		T247	1		T141	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T3	1		T248	1		T295	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T321	1		T351	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T244	2		T96	1		T385	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T324	2		T386	1		T351	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T323	1		T149	1		T191	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T68	1		T235	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	10	1			T258	1		T244	2		T387	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T104	1		T296	1		T388	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T74	1		T284	1		T340	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T298	1		T389	1		T390	1
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T18	2		T25	1		T147	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T204	1		T154	1		T97	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T75	1		T105	1		T66	1
auto[7]	auto[StDisabled]	auto[OpDisable]	2	1			T269	1		T391	1		-	-
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T51	1		T257	1		T392	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T46	1		T261	1		T271	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T50	1		T358	2		T24	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T273	1		T272	1		T393	1